diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | |
parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz |
stats: update stats for previous changes.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt')
-rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 424 |
1 files changed, 212 insertions, 212 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index fae2b58b3..48597bbbd 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026786 # Nu sim_ticks 26786364500 # Number of ticks simulated final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184396 # Simulator instruction rate (inst/s) -host_op_rate 185720 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54518089 # Simulator tick rate (ticks/s) -host_mem_usage 410024 # Number of bytes of host memory used -host_seconds 491.33 # Real time elapsed on the host +host_inst_rate 55091 # Simulator instruction rate (inst/s) +host_op_rate 55487 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16288150 # Simulator tick rate (ticks/s) +host_mem_usage 365372 # Number of bytes of host memory used +host_seconds 1644.53 # Real time elapsed on the host sim_insts 90599358 # Number of instructions simulated sim_ops 91249911 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26786185500 # Total gap between requests +system.physmem.totGap 26786186500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 45050979 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests +system.physmem.totQLat 45051479 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests system.physmem.totBusLat 62048000 # Total cycles spent in databus access system.physmem.totBankLat 172004000 # Total cycles spent in bank access -system.physmem.avgQLat 2904.27 # Average queueing delay per request +system.physmem.avgQLat 2904.30 # Average queueing delay per request system.physmem.avgBankLat 11088.45 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 17992.71 # Average memory access latency +system.physmem.avgMemAccLat 17992.75 # Average memory access latency system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 15087 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1726804.12 # Average gap between requests +system.physmem.avgGap 1726804.18 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -239,23 +239,23 @@ system.cpu.BPredUnit.BTBHits 11281654 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total) @@ -267,11 +267,11 @@ system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing @@ -283,19 +283,19 @@ system.cpu.rename.SquashCycles 3892391 # Nu system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running +system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer @@ -310,11 +310,11 @@ system.cpu.iq.iqSquashedInstsIssued 79722 # Nu system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle @@ -326,7 +326,7 @@ system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available @@ -399,7 +399,7 @@ system.cpu.iq.FU_type_0::total 105160593 # Ty system.cpu.iq.rate 1.962950 # Inst issue rate system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads @@ -422,7 +422,7 @@ system.cpu.iew.iewSquashCycles 3892391 # Nu system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions @@ -484,7 +484,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 162359257 # The number of ROB reads system.cpu.rob.rob_writes 240263976 # The number of ROB writes system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90599358 # Number of Instructions Simulated system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated @@ -513,36 +513,36 @@ system.cpu.icache.demand_hits::cpu.inst 13840965 # nu system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits system.cpu.icache.overall_hits::total 13840965 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses -system.cpu.icache.overall_misses::total 983 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses +system.cpu.icache.overall_misses::total 984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -551,12 +551,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses @@ -582,132 +582,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943495 # number of replacements -system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use -system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits -system.cpu.dcache.overall_hits::total 28133775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses -system.cpu.dcache.overall_misses::total 1370806 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks -system.cpu.dcache.writebacks::total 942892 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks. @@ -750,16 +624,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 708 # system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses system.cpu.l2cache.overall_misses::total 15523 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14541500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 50282500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14542000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 50283000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 602811500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 602811500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 35741000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 617353000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 653094000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 617353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 653094500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 35741000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 617353000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 653094000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 617353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 653094500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 904075 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904810 # number of ReadReq accesses(hits+misses) @@ -789,16 +663,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963265 system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016369 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50481.638418 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52496.389892 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.223350 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52498.194946 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.730964 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41464.541202 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41464.541202 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 42072.666366 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42072.698576 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 42072.666366 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42072.698576 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -829,19 +703,19 @@ system.cpu.l2cache.demand_mshr_misses::total 15512 system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15512 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819084 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819584 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10783379 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602463 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602963 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 420800342 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 420800342 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819084 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819584 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431583721 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 458402805 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819084 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 458403305 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819584 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431583721 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 458402805 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 458403305 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses @@ -855,19 +729,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016357 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016357 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37933.640736 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37934.347949 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40387.187266 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.738193 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 943495 # number of replacements +system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use +system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits +system.cpu.dcache.overall_hits::total 28133775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses +system.cpu.dcache.overall_misses::total 1370806 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks +system.cpu.dcache.writebacks::total 942892 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |