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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
tree | 64b85031cb791a21af6059778384d358d992b817 /tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | |
parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt')
-rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 5f24b4574..5f270b948 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026773 # Nu sim_ticks 26773408500 # Number of ticks simulated final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153523 # Simulator instruction rate (inst/s) -host_op_rate 154625 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45373007 # Simulator tick rate (ticks/s) -host_mem_usage 376436 # Number of bytes of host memory used -host_seconds 590.07 # Real time elapsed on the host +host_inst_rate 111467 # Simulator instruction rate (inst/s) +host_op_rate 112267 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32943427 # Simulator tick rate (ticks/s) +host_mem_usage 421388 # Number of bytes of host memory used +host_seconds 812.71 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory @@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 1726302.76 # Average gap between requests +system.cpu.branchPred.lookups 26672080 # Number of BP lookups +system.cpu.branchPred.condPredicted 21992542 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 842598 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11362388 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11268059 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.169814 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70167 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -231,14 +240,6 @@ system.cpu.workload.num_syscalls 442 # Nu system.cpu.numCycles 53546818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26672080 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21992542 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 842598 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11362388 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11268059 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 70167 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered |