diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/10.mcf/ref/arm/linux/o3-timing | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini | 2 | ||||
| -rwxr-xr-x | tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1171 |
3 files changed, 586 insertions, 595 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index dcc46b583..354c87304 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 60efd00ac..e2beccd27 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:32:09 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:41:22 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 25988864000 because target called exit() +Exiting @ tick 25878583500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 90f8077ba..507566fcc 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025989 # Number of seconds simulated -sim_ticks 25988864000 # Number of ticks simulated -final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025879 # Number of seconds simulated +sim_ticks 25878583500 # Number of ticks simulated +final_tick 25878583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141606 # Simulator instruction rate (inst/s) -host_op_rate 142623 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40620332 # Simulator tick rate (ticks/s) -host_mem_usage 364696 # Number of bytes of host memory used -host_seconds 639.80 # Real time elapsed on the host -sim_insts 90599356 # Number of instructions simulated -sim_ops 91249910 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 952896 # Number of bytes read from this memory -system.physmem.bytes_read::total 999040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory -system.physmem.bytes_written::total 2048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14889 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15610 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory -system.physmem.num_writes::total 32 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1775530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36665550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38441080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1775530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1775530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1775530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36665550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 38519883 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 220420 # Simulator instruction rate (inst/s) +host_op_rate 222002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62960153 # Simulator tick rate (ticks/s) +host_mem_usage 367872 # Number of bytes of host memory used +host_seconds 411.03 # Real time elapsed on the host +sim_insts 90599358 # Number of instructions simulated +sim_ops 91249911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory +system.physmem.bytes_read::total 992960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1758365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36611587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38369952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1758365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1758365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1758365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36611587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 38369952 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +70,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 51977729 # number of cpu cycles simulated +system.cpu.numCycles 51757168 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27100787 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22324909 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 913851 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11625204 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11498872 # Number of BTB hits +system.cpu.BPredUnit.lookups 26984015 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22232491 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 888214 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11580024 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11447482 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 61157 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 10323 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14508615 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 130146910 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27100787 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11560029 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24493529 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4999674 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8879281 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 50 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14156722 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 388066 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 51938784 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.527703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.247354 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 71474 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 416 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14414928 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 129560918 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26984015 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11518956 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24378433 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4928329 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8911472 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 24 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14076190 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 379999 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 51715551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.525564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.245999 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27487299 52.92% 52.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3456218 6.65% 59.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2037280 3.92% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1594827 3.07% 66.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1702478 3.28% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2979904 5.74% 75.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1536396 2.96% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1112311 2.14% 80.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10032071 19.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27375149 52.93% 52.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3448740 6.67% 59.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2025913 3.92% 63.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1592010 3.08% 66.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1693129 3.27% 69.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2969374 5.74% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1533811 2.97% 78.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1107315 2.14% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9970110 19.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 51938784 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.521392 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.503898 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17258666 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6822276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22930941 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 878432 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4048469 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4484484 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8960 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 128309268 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42973 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4048469 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19038937 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2026641 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 195067 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21988132 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4641538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124853766 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 286024 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3901771 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 441 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145615724 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 543819179 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 543813062 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6117 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429479 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38186245 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20008 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20006 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 11296413 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29738779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5601526 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2062082 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1203344 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119239629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22672 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105633795 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 86270 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27804178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69103102 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12544 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 51938784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.033813 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.918657 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 51715551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.521358 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.503246 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17151536 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6845661 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22836822 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 879705 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4001827 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4473928 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9005 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 127743952 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42919 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4001827 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18918146 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2041479 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 194552 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21908799 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4650748 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124387508 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 285864 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3910791 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145115578 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541729246 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541723014 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6232 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 37686096 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18180 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18178 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 11273342 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29662115 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5564551 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2120620 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1233720 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118944023 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22020 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105456921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 87203 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27512358 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68343356 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11890 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 51715551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.039172 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.917652 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 14084713 27.12% 27.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11449450 22.04% 49.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8003608 15.41% 64.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6710442 12.92% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5305637 10.22% 87.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2900837 5.59% 93.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2546575 4.90% 98.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 460556 0.89% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 476966 0.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13904878 26.89% 26.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11456546 22.15% 49.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7969137 15.41% 64.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6724396 13.00% 77.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5314058 10.28% 87.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2865211 5.54% 93.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2534987 4.90% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 474000 0.92% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 472338 0.91% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 51938784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 51715551 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 33927 5.08% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 354815 53.12% 58.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 279170 41.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33403 5.02% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 354808 53.31% 58.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277311 41.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74740578 70.75% 70.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10525 0.01% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 195 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 237 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25722669 24.35% 95.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5159588 4.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74629419 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10524 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 188 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 232 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25677872 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5138682 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105633795 # Type of FU issued -system.cpu.iq.rate 2.032290 # Inst issue rate -system.cpu.iq.fu_busy_cnt 667939 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006323 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263959647 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 147067415 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102938725 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 936 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1347 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 404 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106301267 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 467 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 423068 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105456921 # Type of FU issued +system.cpu.iq.rate 2.037533 # Inst issue rate +system.cpu.iq.fu_busy_cnt 665549 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006311 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263381228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146480266 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102833498 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 917 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1333 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 399 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106122017 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 453 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 424644 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7162902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8413 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3100 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 854772 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7086237 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8981 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4129 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 817795 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39235 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39333 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4048469 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 193737 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 33246 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119298911 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 399459 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29738779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5601526 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18769 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13636 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1014 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3100 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 499711 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 490212 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 989923 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104558374 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25377273 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1075421 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4001827 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 198669 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33921 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119002430 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 339181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29662115 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5564551 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18117 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13618 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1230 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4129 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 473445 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 489320 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 962765 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104433557 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25350982 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1023364 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 36610 # number of nop insts executed -system.cpu.iew.exec_refs 30470186 # number of memory reference insts executed -system.cpu.iew.exec_branches 21355608 # Number of branches executed -system.cpu.iew.exec_stores 5092913 # Number of stores executed -system.cpu.iew.exec_rate 2.011600 # Inst execution rate -system.cpu.iew.wb_sent 103258351 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102939129 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62202150 # num instructions producing a value -system.cpu.iew.wb_consumers 103963576 # num instructions consuming a value +system.cpu.iew.exec_nop 36387 # number of nop insts executed +system.cpu.iew.exec_refs 30425523 # number of memory reference insts executed +system.cpu.iew.exec_branches 21334984 # Number of branches executed +system.cpu.iew.exec_stores 5074541 # Number of stores executed +system.cpu.iew.exec_rate 2.017760 # Inst execution rate +system.cpu.iew.wb_sent 103141450 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102833897 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62142858 # num instructions producing a value +system.cpu.iew.wb_consumers 103855994 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.980447 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598307 # average fanout of values written-back +system.cpu.iew.wb_rate 1.986853 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598356 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 90611965 # The number of committed instructions -system.cpu.commit.commitCommittedOps 91262519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 28037719 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10128 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 916929 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 47890316 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.905657 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.507554 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 90611967 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262520 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27741223 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 891236 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 47713725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.912710 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.511102 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17540600 36.63% 36.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13534361 28.26% 64.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4502880 9.40% 74.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3873758 8.09% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1516151 3.17% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 799389 1.67% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 846315 1.77% 88.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253211 0.53% 89.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5023651 10.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17393373 36.45% 36.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13510296 28.32% 64.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4501215 9.43% 74.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3866271 8.10% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1517173 3.18% 85.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 785983 1.65% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 854820 1.79% 88.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253298 0.53% 89.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5031296 10.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 47890316 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611965 # Number of instructions committed -system.cpu.commit.committedOps 91262519 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 47713725 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611967 # Number of instructions committed +system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322631 # Number of memory references committed -system.cpu.commit.loads 22575877 # Number of loads committed +system.cpu.commit.refs 27322634 # Number of memory references committed +system.cpu.commit.loads 22575878 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722471 # Number of branches committed +system.cpu.commit.branches 18722472 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5023651 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5031296 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162161169 # The number of ROB reads -system.cpu.rob.rob_writes 242671240 # The number of ROB writes -system.cpu.timesIdled 1828 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38945 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599356 # Number of Instructions Simulated -system.cpu.committedOps 91249910 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599356 # Number of Instructions Simulated -system.cpu.cpi 0.573710 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.573710 # CPI: Total CPI of All Threads -system.cpu.ipc 1.743042 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.743042 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497076309 # number of integer regfile reads -system.cpu.int_regfile_writes 120895703 # number of integer regfile writes -system.cpu.fp_regfile_reads 198 # number of floating regfile reads -system.cpu.fp_regfile_writes 527 # number of floating regfile writes -system.cpu.misc_regfile_reads 183813486 # number of misc regfile reads -system.cpu.misc_regfile_writes 11604 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 649.670012 # Cycle average of tags in use -system.cpu.icache.total_refs 14155750 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 749 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18899.532710 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 161680438 # The number of ROB reads +system.cpu.rob.rob_writes 242031234 # The number of ROB writes +system.cpu.timesIdled 1832 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599358 # Number of Instructions Simulated +system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated +system.cpu.cpi 0.571275 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.571275 # CPI: Total CPI of All Threads +system.cpu.ipc 1.750470 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.750470 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496537855 # number of integer regfile reads +system.cpu.int_regfile_writes 120784900 # number of integer regfile writes +system.cpu.fp_regfile_reads 199 # number of floating regfile reads +system.cpu.fp_regfile_writes 517 # number of floating regfile writes +system.cpu.misc_regfile_reads 183129525 # number of misc regfile reads +system.cpu.misc_regfile_writes 11608 # number of misc regfile writes +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.tagsinuse 635.708091 # Cycle average of tags in use +system.cpu.icache.total_refs 14075225 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 737 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19097.998643 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 649.670012 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.317222 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.317222 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14155750 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14155750 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14155750 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14155750 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14155750 # number of overall hits -system.cpu.icache.overall_hits::total 14155750 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 972 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 972 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 972 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 972 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 972 # number of overall misses -system.cpu.icache.overall_misses::total 972 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33892500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33892500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33892500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33892500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33892500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33892500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14156722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14156722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14156722 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14156722 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 635.708091 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310404 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310404 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14075225 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14075225 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14075225 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14075225 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14075225 # number of overall hits +system.cpu.icache.overall_hits::total 14075225 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 965 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 965 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.icache.overall_misses::total 965 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33626500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33626500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33626500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33626500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33626500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33626500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14076190 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14076190 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14076190 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14076190 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14076190 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14076190 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34868.827160 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34868.827160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34868.827160 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34846.113990 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34846.113990 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34846.113990 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34846.113990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34846.113990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34846.113990 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,246 +394,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 749 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 749 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 749 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 749 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 749 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25625000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25625000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25625000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25625000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34212.283044 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 228 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 228 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 228 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 228 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 228 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25265000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25265000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25265000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25265000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25265000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25265000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34280.868385 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34280.868385 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34280.868385 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34280.868385 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34280.868385 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34280.868385 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943602 # number of replacements -system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use -system.cpu.dcache.total_refs 28436874 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947698 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.006261 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8214901000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3646.405021 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.890236 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.890236 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23866253 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23866253 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4558926 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4558926 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5797 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5797 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28425179 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28425179 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28425179 # number of overall hits -system.cpu.dcache.overall_hits::total 28425179 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1004103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1004103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 176055 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 176055 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1180158 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1180158 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1180158 # number of overall misses -system.cpu.dcache.overall_misses::total 1180158 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5784178500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5784178500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4612267011 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4612267011 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 129000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10396445511 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10396445511 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10396445511 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10396445511 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24870356 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24870356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943587 # number of replacements +system.cpu.dcache.tagsinuse 3648.438272 # Cycle average of tags in use +system.cpu.dcache.total_refs 28413602 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947683 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.982180 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8139620000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3648.438272 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.890732 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.890732 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23842486 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23842486 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4559459 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4559459 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5858 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5858 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28401945 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28401945 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28401945 # number of overall hits +system.cpu.dcache.overall_hits::total 28401945 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1005618 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1005618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 175522 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 175522 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1181140 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1181140 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1181140 # number of overall misses +system.cpu.dcache.overall_misses::total 1181140 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5786835500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5786835500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4609409990 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4609409990 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10396245490 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10396245490 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10396245490 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10396245490 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24848104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24848104 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29605337 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29605337 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040373 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037182 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001355 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039863 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039863 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5760.542992 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26197.875726 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8809.367484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8809.367484 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5865 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5865 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29583085 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29583085 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29583085 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29583085 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040471 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037069 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037069 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001194 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001194 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039926 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039926 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039926 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039926 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5754.506681 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5754.506681 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26261.152391 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26261.152391 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18571.428571 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18571.428571 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8801.874028 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8801.874028 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8801.874028 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8801.874028 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23117548 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8084 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2859.666997 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks -system.cpu.dcache.writebacks::total 942908 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 99918 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 99918 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 132542 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 232460 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 232460 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 232460 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 232460 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904185 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904185 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43513 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43513 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947698 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947698 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947698 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947698 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2402147500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2402147500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1077084130 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1077084130 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3479231630 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036356 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009190 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032011 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032011 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2656.699127 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2656.699127 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24753.157217 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942950 # number of writebacks +system.cpu.dcache.writebacks::total 942950 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101118 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132339 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 132339 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 233457 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 233457 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 233457 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 233457 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904500 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904500 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43183 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43183 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947683 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947683 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947683 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947683 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2400819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2400819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1075610609 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1075610609 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3476430109 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3476430109 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3476430109 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3476430109 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009120 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009120 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2654.305694 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2654.305694 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24908.195563 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24908.195563 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3668.347020 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3668.347020 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3668.347020 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3668.347020 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 770 # number of replacements -system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1600694 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15595 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 102.641488 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 10511.051990 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1830916 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15498 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.138857 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9634.775304 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 182.147356 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 200.243688 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.294030 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.005559 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006111 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.305700 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 902746 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 902773 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942908 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.325962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 268 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14536 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14536 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 711 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15515 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22107000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460482500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 482589500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.327779 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.327779 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31092.827004 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31208.955224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31124.616956 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.364062 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31103.364062 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |