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authorNilay Vaish <nilay@cs.wisc.edu>2015-03-09 09:39:09 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-03-09 09:39:09 -0500
commit99fb8f81407efa54008ddf443718e492f583b142 (patch)
tree48e79a13dc012864045058f6ca3aadc3b9a767a8 /tests/long/se/10.mcf/ref/arm/linux/o3-timing
parent0c8e025c3bd208e516f1c4247fdf3af7aebb2300 (diff)
downloadgem5-99fb8f81407efa54008ddf443718e492f583b142.tar.xz
stats: changes to due to recent set of patches
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/o3-timing')
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt1
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 8fe6f61b1..0eb73f5eb 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -676,7 +676,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 217986125 # The number of ROB reads
system.cpu.rob.rob_writes 219581178 # The number of ROB writes
system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself