stats: update stats for insts/ops and master id changes

1 files changed, 244 insertions, 154 deletions

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index d6f3be234..27b93150e 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds                                  0.148086                       # Nu
 sim_ticks                                148086239000                       # Number of ticks simulated
 final_tick                               148086239000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1300672                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2111359212                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 351948                       # Number of bytes of host memory used
-host_seconds                                    70.14                       # Real time elapsed on the host
-sim_insts                                    91226321                       # Number of instructions simulated
+host_inst_rate                                1696896                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1709063                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2774293546                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354444                       # Number of bytes of host memory used
+host_seconds                                    53.38                       # Real time elapsed on the host
+sim_insts                                    90576869                       # Number of instructions simulated
+sim_ops                                      91226321                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      986112                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  36992                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                  442                       # Nu
 system.cpu.numCycles                        296172478                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         91226321                       # Number of instructions executed
+system.cpu.committedInsts                    90576869                       # Number of instructions committed
+system.cpu.committedOps                      91226321                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
 system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs                107830181                       # To
 system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               180016.996661                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.335448                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.249187                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              107830181                       # number of ReadReq hits
-system.cpu.icache.demand_hits               107830181                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              107830181                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  599                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   599                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  599                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       32662000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        32662000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       32662000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          107830780                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           107830780                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          107830780                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54527.545910                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54527.545910                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     510.335448                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    107830181                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       107830181                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     107830181                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        107830181                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    107830181                       # number of overall hits
+system.cpu.icache.overall_hits::total       107830181                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          599                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           599                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          599                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            599                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          599                       # number of overall misses
+system.cpu.icache.overall_misses::total           599                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32662000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32662000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32662000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32662000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32662000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32662000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    107830780                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    107830780                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    107830780                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    107830780                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    107830780                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    107830780                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000006                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000006                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000006                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             599                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              599                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             599                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     30865000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     30865000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000006                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          599                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          599                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          599                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          599                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     30865000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     30865000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     30865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     30865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 942702                       # number of replacements
 system.cpu.dcache.tagsinuse               3568.549501                       # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs                 26345365                       # To
 system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  27.825751                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            54479156000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3568.549501                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.871228                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               21649219                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               4688372                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             3887                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                26337591                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               26337591                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               900189                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               46609                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                946798                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               946798                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    12614490000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    1263542000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     13878032000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    13878032000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           22549408                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            27284389                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           27284389                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.039921                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.034701                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.034701                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14657.859438                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14657.859438                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3568.549501                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     21649219                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21649219                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4688372                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      26337591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26337591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26337591                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26337591                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       900189                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        900189                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        46609                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        46609                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       946798                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         946798                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       946798                       # number of overall misses
+system.cpu.dcache.overall_misses::total        946798                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  13878032000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  13878032000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.039921                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009844                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.034701                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.034701                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   942309                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          900189                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           946798                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          946798                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9913923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  11037638000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  11037638000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.039921                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.034701                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.034701                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       942309                       # number of writebacks
+system.cpu.dcache.writebacks::total            942309                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.039921                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                   634                       # number of replacements
 system.cpu.l2cache.tagsinuse              9235.307693                       # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs                 1594542                       # To
 system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                103.595504                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           325.097811                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8910.209882                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.009921                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.271918                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                899928                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              942309                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               32061                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 931989                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                931989                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 860                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             14548                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                15408                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               15408                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      44720000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    756496000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      801216000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     801216000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            900788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          942309                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           46609                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             947397                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            947397                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.000955                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.312129                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.016264                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.016264                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  8910.209882                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    165.071875                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    160.025936                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.271918                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.005038                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.004884                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.281839                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           21                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       899907                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         899928                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       942309                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       942309                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        32061                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32061                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           21                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       931968                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          931989                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           21                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       931968                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         931989                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          578                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          282                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          860                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        14548                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14548                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          578                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14830                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15408                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          578                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14830                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15408                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     30056000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14664000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     44720000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     30056000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    771160000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    801216000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     30056000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    771160000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    801216000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          599                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       900189                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       900788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       942309                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       942309                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          599                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       946798                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       947397                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          599                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       946798                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       947397                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.964942                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000313                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.964942                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015663                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.964942                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015663                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                      32                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            860                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           15408                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          15408                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     34400000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    581920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    616320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    616320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000955                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312129                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.016264                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.016264                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks           32                       # number of writebacks
+system.cpu.l2cache.writebacks::total               32                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          578                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          282                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          860                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          578                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14830                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15408                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          578                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14830                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15408                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     11280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     34400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    581920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    581920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    593200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    616320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    593200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    616320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000313                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.312129                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015663                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015663                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------