stats: Update stats for unified cache configuration

This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.

1 files changed, 7 insertions, 7 deletions

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 9850fa37f..91d2f15f8 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.147136                       # Nu
 sim_ticks                                147135976000                       # Number of ticks simulated
 final_tick                               147135976000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1039833                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1047288                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1689137215                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 366884                       # Number of bytes of host memory used
-host_seconds                                    87.11                       # Real time elapsed on the host
+host_inst_rate                                1200528                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1209136                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1950176496                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 364464                       # Number of bytes of host memory used
+host_seconds                                    75.45                       # Real time elapsed on the host
 sim_insts                                    90576861                       # Number of instructions simulated
 sim_ops                                      91226312                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             36992                       # Number of bytes read from this memory
@@ -280,9 +280,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              9565.271881                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1827210                       # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs                 1827177                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 15323                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                119.246231                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                119.244078                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.occ_blocks::writebacks  8876.925013                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.inst    495.124137                       # Average occupied blocks per requestor