stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 40 insertions, 5 deletions

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 866d0f0d0..bffef2d47 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.147136                       # Nu
 sim_ticks                                147135976000                       # Number of ticks simulated
 final_tick                               147135976000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 836188                       # Simulator instruction rate (inst/s)
-host_op_rate                                   842183                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1358330065                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 420368                       # Number of bytes of host memory used
-host_seconds                                   108.32                       # Real time elapsed on the host
+host_inst_rate                                 662214                       # Simulator instruction rate (inst/s)
+host_op_rate                                   666963                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1075722156                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 375060                       # Number of bytes of host memory used
+host_seconds                                   136.78                       # Real time elapsed on the host
 sim_insts                                    90576861                       # Number of instructions simulated
 sim_ops                                      91226312                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             36992                       # Number of bytes read from this memory
@@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total             251414                       # In
 system.physmem.bw_total::cpu.inst              251414                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data             6421054                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                6672467                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                      6672467                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 792                       # Transaction distribution
+system.membus.trans_dist::ReadResp                792                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             14548                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            14548                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side        30680                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count                         30680                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side       981760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size                     981760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 981760                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            15340000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          138060000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               821979690                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         900788                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        900788                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       942334                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        46609                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        46609                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         1198                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side      2835930                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                  2837128                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        38336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side    120904448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size             120942784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         120942784                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     1887199500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        898500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    1420197000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------