stats: update stats for no_value -> nan

Lots of accumulated older changes too.

3 files changed, 21 insertions, 20 deletions

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index f9dbf6b5f..98847a36c 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -178,14 +177,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -206,8 +205,10 @@ master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index d8b8bc833..10d881c1d 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 17 2012 11:46:05
-gem5 started Mar 17 2012 17:03:45
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
+gem5 compiled May  8 2012 15:17:37
+gem5 started May  8 2012 16:24:48
+gem5 executing on piton
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index f3ad4a424..d20615e1d 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.148086                       # Nu
 sim_ticks                                148086239000                       # Number of ticks simulated
 final_tick                               148086239000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1876733                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1890189                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3068313156                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 355600                       # Number of bytes of host memory used
-host_seconds                                    48.26                       # Real time elapsed on the host
+host_inst_rate                                 549790                       # Simulator instruction rate (inst/s)
+host_op_rate                                   553732                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              898863423                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 362780                       # Number of bytes of host memory used
+host_seconds                                   164.75                       # Real time elapsed on the host
 sim_insts                                    90576869                       # Number of instructions simulated
 sim_ops                                      91226321                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      986112                       # Number of bytes read from this memory
@@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          599                       # number of ReadReq MSHR misses
@@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       942309                       # number of writebacks
@@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks           32                       # number of writebacks