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authorCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
committerCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
commit84f138ba96201431513eb2ae5f847389ac731aa2 (patch)
tree3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/se/10.mcf/ref/arm/linux
parenta288c94387b110112461ff5686fa727a43ddbe9c (diff)
downloadgem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz
stats: update references
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux')
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini113
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/minor-timing/simout10
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt798
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini84
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt12
8 files changed, 607 insertions, 420 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
index 8b738959d..20272ec5e 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -55,6 +64,7 @@ decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -99,12 +109,17 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
+threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -120,11 +135,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -132,13 +154,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -148,6 +175,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -156,8 +184,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -180,9 +213,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.dtb]
@@ -196,9 +234,14 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -591,13 +634,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -607,6 +655,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -615,8 +664,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -626,6 +680,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
+decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@@ -673,9 +728,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.itb]
@@ -689,9 +749,14 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -701,13 +766,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -717,6 +787,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -725,19 +796,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -745,6 +828,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -759,9 +849,9 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
@@ -791,9 +881,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -837,6 +933,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -848,7 +945,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:268435455
ranks_per_channel=2
read_buffer_size=32
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr
index e9c9539d6..36f24465c 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr
@@ -1,2 +1,3 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
index d0ca2b5a8..1a3679afb 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 15 2015 02:29:01
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 15:03:02
+gem5 executing on e108600-lin, pid 24162
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -26,4 +26,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 61240850500 because target called exit()
+Exiting @ tick 62408957500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index c8a3d5425..ef2534218 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,49 +1,49 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.061235 # Number of seconds simulated
-sim_ticks 61234797500 # Number of ticks simulated
-final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.062409 # Number of seconds simulated
+sim_ticks 62408957500 # Number of ticks simulated
+final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 433531 # Simulator instruction rate (inst/s)
-host_op_rate 435690 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 293005809 # Simulator tick rate (ticks/s)
-host_mem_usage 447448 # Number of bytes of host memory used
-host_seconds 208.99 # Real time elapsed on the host
+host_inst_rate 176281 # Simulator instruction rate (inst/s)
+host_op_rate 177159 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 121425676 # Simulator tick rate (ticks/s)
+host_mem_usage 399932 # Number of bytes of host memory used
+host_seconds 513.97 # Real time elapsed on the host
sim_insts 90602850 # Number of instructions simulated
sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
-system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory
+system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 807907 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 15468329 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 16276236 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 807907 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 807907 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 807907 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 15468329 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 16276236 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15573 # Number of read requests accepted
+system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15574 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 15573 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 996672 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 996672 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 993 # Per bank write bursts
-system.physmem.perBankRdBursts::1 890 # Per bank write bursts
+system.physmem.perBankRdBursts::1 891 # Per bank write bursts
system.physmem.perBankRdBursts::2 949 # Per bank write bursts
system.physmem.perBankRdBursts::3 1027 # Per bank write bursts
system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
@@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 61234703000 # Total gap between requests
+system.physmem.totGap 62408863500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 15573 # Read request sizes (log2)
+system.physmem.readPktSize::6 15574 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -187,86 +187,86 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1535 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 648.213681 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 443.714701 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 401.012846 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 241 15.70% 15.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 186 12.12% 27.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 88 5.73% 33.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 73 4.76% 38.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 71 4.63% 42.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 84 5.47% 48.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 36 2.35% 50.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 51 3.32% 54.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 705 45.93% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1535 # Bytes accessed per row activation
-system.physmem.totQLat 72594750 # Total ticks spent queuing
-system.physmem.totMemAccLat 364588500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 77865000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 4661.58 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation
+system.physmem.totQLat 75120250 # Total ticks spent queuing
+system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23411.58 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.13 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.12 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 14028 # Number of row buffer hits during reads
+system.physmem.readRowHits 14020 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.08 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 3932107.04 # Average gap between requests
-system.physmem.pageHitRate 90.08 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 63679200 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 4007246.92 # Average gap between requests
+system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 2519893620 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 34528365000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 41120963895 # Total energy per rank (pJ)
-system.physmem_0.averagePower 671.567381 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 57430990750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2044640000 # Time in different power states
+system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ)
+system.physmem_0.averagePower 671.544396 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1755713000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 2548962765 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ)
-system.physmem_1.averagePower 671.499745 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states
+system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ)
+system.physmem_1.averagePower 671.428274 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 20750031 # Number of BP lookups
-system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted
+system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 20808236 # Number of BP lookups
+system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses.
+system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 61234797500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 122469595 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 124817915 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602850 # Number of instructions committed
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.351719 # CPI: cycles per instruction
-system.cpu.ipc 0.739799 # IPC: instructions per cycle
+system.cpu.cpi 1.377638 # CPI: cycles per instruction
+system.cpu.ipc 0.725880 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
@@ -432,60 +432,60 @@ system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91054081 # Class of committed instruction
-system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 946097 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy
+system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements 946101 # number of replacements
+system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 26254404 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26254404 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26254912 # number of overall hits
-system.cpu.dcache.overall_hits::total 26254912 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 74289 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 74289 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits
+system.cpu.dcache.overall_hits::total 26267146 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 989215 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 989215 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 989219 # number of overall misses
-system.cpu.dcache.overall_misses::total 989219 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919140000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11919140000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2539899500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2539899500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 14459039500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 14459039500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 14459039500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 14459039500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 22508638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 22508638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses
+system.cpu.dcache.overall_misses::total 980615 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
@@ -494,139 +494,139 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 27243619 # number of demand (read+write) accesses
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -641,254 +641,256 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801
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-system.cpu.l2cache.demand_mshr_miss_latency::total 990185500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50052500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940133000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 990185500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.016375 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.016375 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2848090 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846495 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 2848102 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182656 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 121234240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 950994 # Request fanout histogram
+system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 950998 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 950828 99.98% 99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 950832 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1029 # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp 1030 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 15573 # Request fanout histogram
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 15574 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 15573 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 15573 # Request fanout histogram
-system.membus.reqLayer0.occupancy 21737000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 15574 # Request fanout histogram
+system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 82128750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 7fcb96393..763fea8df 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=2
decodeWidth=3
+default_p_state=UNDEFINED
dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
@@ -110,6 +116,10 @@ numPhysIntRegs=128
numROBEntries=40
numRobs=1
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -166,12 +176,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -190,8 +205,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=32768
@@ -214,9 +234,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.dtb]
@@ -230,9 +255,14 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -508,12 +538,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=1
@@ -532,8 +567,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=32768
@@ -591,9 +631,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.itb]
@@ -607,9 +652,14 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -620,12 +670,17 @@ addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
response_latency=12
@@ -643,6 +698,7 @@ mem_side=system.membus.slave[1]
type=StridePrefetcher
cache_snoop=false
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
degree=8
eventq_index=0
latency=1
@@ -653,6 +709,10 @@ on_inst=true
on_miss=false
on_read=true
on_write=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
queue_filter=true
queue_size=32
queue_squash=true
@@ -669,8 +729,13 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=1048576
@@ -678,10 +743,15 @@ size=1048576
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -712,9 +782,9 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
@@ -744,10 +814,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -791,6 +866,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -802,7 +878,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:268435455
ranks_per_channel=2
read_buffer_size=32
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
index d9d33c634..4184e8f67 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
@@ -1,3 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 1617c9a7a..67b5f0b3c 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 15 2016 19:53:43
-gem5 started Mar 15 2016 19:54:42
-gem5 executing on dinar2c11, pid 10367
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 15:07:19
+gem5 executing on e108600-lin, pid 24393
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 6265572cd..5f4859c30 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.058199 # Nu
sim_ticks 58199030500 # Number of ticks simulated
final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 220490 # Simulator instruction rate (inst/s)
-host_op_rate 221588 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 141652578 # Simulator tick rate (ticks/s)
-host_mem_usage 534836 # Number of bytes of host memory used
-host_seconds 410.86 # Real time elapsed on the host
+host_inst_rate 123305 # Simulator instruction rate (inst/s)
+host_op_rate 123919 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 79216719 # Simulator tick rate (ticks/s)
+host_mem_usage 487100 # Number of bytes of host memory used
+host_seconds 734.68 # Real time elapsed on the host
sim_insts 90589799 # Number of instructions simulated
sim_ops 91041030 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -1180,6 +1180,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 319939 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 11456 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram
@@ -1212,6 +1213,7 @@ system.membus.pkt_count::total 33275 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 16759 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram