diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/10.mcf/ref/arm/linux | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux')
6 files changed, 672 insertions, 672 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 354c87304..a0763b2c7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index e2beccd27..48d145b85 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:41:22 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:39:45 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 25878583500 because target called exit() +Exiting @ tick 28553466500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 507566fcc..8d85ceff7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025879 # Number of seconds simulated -sim_ticks 25878583500 # Number of ticks simulated -final_tick 25878583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.028553 # Number of seconds simulated +sim_ticks 28553466500 # Number of ticks simulated +final_tick 28553466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220420 # Simulator instruction rate (inst/s) -host_op_rate 222002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62960153 # Simulator tick rate (ticks/s) -host_mem_usage 367872 # Number of bytes of host memory used -host_seconds 411.03 # Real time elapsed on the host -sim_insts 90599358 # Number of instructions simulated -sim_ops 91249911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory -system.physmem.bytes_read::total 992960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1758365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36611587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38369952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1758365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1758365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1758365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36611587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 38369952 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 181848 # Simulator instruction rate (inst/s) +host_op_rate 183154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57311644 # Simulator tick rate (ticks/s) +host_mem_usage 367800 # Number of bytes of host memory used +host_seconds 498.21 # Real time elapsed on the host +sim_insts 90599368 # Number of instructions simulated +sim_ops 91249921 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory +system.physmem.bytes_read::total 992896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45312 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 708 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1586918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33186303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34773221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1586918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1586918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1586918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33186303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 34773221 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,322 +70,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 51757168 # number of cpu cycles simulated +system.cpu.numCycles 57106934 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26984015 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22232491 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 888214 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11580024 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11447482 # Number of BTB hits +system.cpu.BPredUnit.lookups 27012699 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22277532 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 889694 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11653286 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11426819 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 71474 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 416 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14414928 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 129560918 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26984015 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11518956 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24378433 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4928329 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8911472 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 72452 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 358 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14542606 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 129803697 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27012699 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11499271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24399920 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5015488 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 14039908 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 24 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14076190 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 379999 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 51715551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.525564 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.245999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14144138 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 347071 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 57042317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.294103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.179417 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27375149 52.93% 52.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3448740 6.67% 59.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2025913 3.92% 63.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1592010 3.08% 66.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1693129 3.27% 69.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2969374 5.74% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1533811 2.97% 78.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1107315 2.14% 80.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9970110 19.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 32680363 57.29% 57.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3435885 6.02% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2022812 3.55% 66.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1588688 2.79% 69.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1698003 2.98% 72.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3014546 5.28% 77.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1479172 2.59% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1109191 1.94% 82.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10013657 17.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 51715551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.521358 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.503246 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17151536 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6845661 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22836822 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 879705 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4001827 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4473928 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9005 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 127743952 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42919 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4001827 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18918146 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2041479 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 194552 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21908799 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4650748 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124387508 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 285864 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3910791 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145115578 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541729246 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541723014 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6232 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37686096 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18180 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18178 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 11273342 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29662115 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5564551 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2120620 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1233720 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118944023 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22020 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105456921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 87203 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27512358 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68343356 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11890 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 51715551 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.039172 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.917652 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 57042317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.473020 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.272994 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17762369 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11471319 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22339470 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1418238 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4050921 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4486769 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9087 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 127953392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42856 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4050921 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19506799 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5508085 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 206847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21544530 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6225135 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124612804 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1000 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 540301 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4835980 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10850 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145164650 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 542855215 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 542847680 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7535 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 37735152 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18216 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18214 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14341922 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29837938 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5556896 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2142306 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1236219 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119143027 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22051 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105690693 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78779 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27699280 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68606056 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11919 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 57042317 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.852847 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.854849 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13904878 26.89% 26.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11456546 22.15% 49.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7969137 15.41% 64.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6724396 13.00% 77.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5314058 10.28% 87.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2865211 5.54% 93.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2534987 4.90% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 474000 0.92% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 472338 0.91% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17381718 30.47% 30.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13049544 22.88% 53.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8518143 14.93% 68.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6991208 12.26% 80.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5292177 9.28% 89.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2744999 4.81% 94.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2144277 3.76% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 490134 0.86% 99.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 430117 0.75% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 51715551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 57042317 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 33403 5.02% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 354808 53.31% 58.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277311 41.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 40944 6.13% 6.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 349072 52.27% 58.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277751 41.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74629419 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10524 0.01% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 188 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 232 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25677872 24.35% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5138682 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74708862 70.69% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10518 0.01% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 221 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 275 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25829491 24.44% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5141321 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105456921 # Type of FU issued -system.cpu.iq.rate 2.037533 # Inst issue rate -system.cpu.iq.fu_busy_cnt 665549 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006311 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263381228 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146480266 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102833498 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 917 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1333 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 399 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106122017 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 453 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 424644 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105690693 # Type of FU issued +system.cpu.iq.rate 1.850751 # Inst issue rate +system.cpu.iq.fu_busy_cnt 667794 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006318 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 269169203 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146866507 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102954305 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1073 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1626 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 453 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106357959 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 528 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 425504 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7086237 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8981 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4129 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 817795 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7262058 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7178 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4608 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 810138 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39333 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 165527 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4001827 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 198669 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 33921 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119002430 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 339181 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29662115 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5564551 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18117 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13618 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1230 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4129 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 473445 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 489320 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 962765 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104433557 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25350982 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1023364 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4050921 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 893670 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 117044 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119201460 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342636 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29837938 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5556896 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18147 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49262 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15777 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4608 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 477903 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 486113 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 964016 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104633146 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25499061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1057547 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 36387 # number of nop insts executed -system.cpu.iew.exec_refs 30425523 # number of memory reference insts executed -system.cpu.iew.exec_branches 21334984 # Number of branches executed -system.cpu.iew.exec_stores 5074541 # Number of stores executed -system.cpu.iew.exec_rate 2.017760 # Inst execution rate -system.cpu.iew.wb_sent 103141450 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102833897 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62142858 # num instructions producing a value -system.cpu.iew.wb_consumers 103855994 # num instructions consuming a value +system.cpu.iew.exec_nop 36382 # number of nop insts executed +system.cpu.iew.exec_refs 30575453 # number of memory reference insts executed +system.cpu.iew.exec_branches 21352915 # Number of branches executed +system.cpu.iew.exec_stores 5076392 # Number of stores executed +system.cpu.iew.exec_rate 1.832232 # Inst execution rate +system.cpu.iew.wb_sent 103240911 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102954758 # cumulative count of insts written-back +system.cpu.iew.wb_producers 61949538 # num instructions producing a value +system.cpu.iew.wb_consumers 102898807 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.986853 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598356 # average fanout of values written-back +system.cpu.iew.wb_rate 1.802842 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.602043 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 90611967 # The number of committed instructions -system.cpu.commit.commitCommittedOps 91262520 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27741223 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 891236 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 47713725 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.912710 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.511102 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 90611977 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262530 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27941572 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892650 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 52991397 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.722214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.475842 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17393373 36.45% 36.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13510296 28.32% 64.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4501215 9.43% 74.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3866271 8.10% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1517173 3.18% 85.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 785983 1.65% 87.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 854820 1.79% 88.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253298 0.53% 89.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5031296 10.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23013346 43.43% 43.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13498664 25.47% 68.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4267920 8.05% 76.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3605539 6.80% 83.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1555941 2.94% 86.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 706178 1.33% 88.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 916105 1.73% 89.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 261507 0.49% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5166197 9.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 47713725 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611967 # Number of instructions committed -system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 52991397 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611977 # Number of instructions committed +system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322634 # Number of memory references committed -system.cpu.commit.loads 22575878 # Number of loads committed +system.cpu.commit.refs 27322638 # Number of memory references committed +system.cpu.commit.loads 22575880 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722472 # Number of branches committed +system.cpu.commit.branches 18722474 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533330 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5031296 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5166197 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 161680438 # The number of ROB reads -system.cpu.rob.rob_writes 242031234 # The number of ROB writes -system.cpu.timesIdled 1832 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41617 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599358 # Number of Instructions Simulated -system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated -system.cpu.cpi 0.571275 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.571275 # CPI: Total CPI of All Threads -system.cpu.ipc 1.750470 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.750470 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 496537855 # number of integer regfile reads -system.cpu.int_regfile_writes 120784900 # number of integer regfile writes -system.cpu.fp_regfile_reads 199 # number of floating regfile reads -system.cpu.fp_regfile_writes 517 # number of floating regfile writes -system.cpu.misc_regfile_reads 183129525 # number of misc regfile reads -system.cpu.misc_regfile_writes 11608 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 635.708091 # Cycle average of tags in use -system.cpu.icache.total_refs 14075225 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 737 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19097.998643 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 167023568 # The number of ROB reads +system.cpu.rob.rob_writes 242480145 # The number of ROB writes +system.cpu.timesIdled 16985 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599368 # Number of Instructions Simulated +system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated +system.cpu.cpi 0.630324 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.630324 # CPI: Total CPI of All Threads +system.cpu.ipc 1.586486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.586486 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 497500268 # number of integer regfile reads +system.cpu.int_regfile_writes 120842597 # number of integer regfile writes +system.cpu.fp_regfile_reads 229 # number of floating regfile reads +system.cpu.fp_regfile_writes 593 # number of floating regfile writes +system.cpu.misc_regfile_reads 183620284 # number of misc regfile reads +system.cpu.misc_regfile_writes 11612 # number of misc regfile writes +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 638.455928 # Cycle average of tags in use +system.cpu.icache.total_refs 14143171 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 734 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19268.625341 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 635.708091 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310404 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310404 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14075225 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14075225 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14075225 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14075225 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14075225 # number of overall hits -system.cpu.icache.overall_hits::total 14075225 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 965 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 965 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 965 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 965 # number of overall misses -system.cpu.icache.overall_misses::total 965 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33626500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33626500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33626500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33626500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33626500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33626500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14076190 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14076190 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14076190 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14076190 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14076190 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14076190 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34846.113990 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34846.113990 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34846.113990 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34846.113990 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34846.113990 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34846.113990 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 638.455928 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.311746 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.311746 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14143171 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14143171 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14143171 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14143171 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14143171 # number of overall hits +system.cpu.icache.overall_hits::total 14143171 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 967 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 967 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 967 # number of overall misses +system.cpu.icache.overall_misses::total 967 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35020500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35020500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35020500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35020500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35020500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35020500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14144138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14144138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14144138 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14144138 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14144138 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14144138 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000068 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000068 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000068 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36215.615305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36215.615305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36215.615305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36215.615305 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,246 +394,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 228 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 228 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 228 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 228 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 228 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25265000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25265000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25265000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25265000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25265000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25265000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 233 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 233 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 233 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 233 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 233 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 233 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 734 # 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mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34280.868385 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34280.868385 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34280.868385 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34280.868385 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34280.868385 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34280.868385 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36027.247956 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36027.247956 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943587 # number of replacements -system.cpu.dcache.tagsinuse 3648.438272 # Cycle average of tags in use -system.cpu.dcache.total_refs 28413602 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947683 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.982180 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8139620000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3648.438272 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.890732 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.890732 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23842486 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23842486 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4559459 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4559459 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5858 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5858 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28401945 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28401945 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943512 # number of replacements +system.cpu.dcache.tagsinuse 3689.791275 # Cycle average of tags in use +system.cpu.dcache.total_refs 28381642 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.950826 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8154700000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3689.791275 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.900828 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.900828 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23801988 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23801988 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4567984 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4567984 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5869 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5869 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28369972 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28369972 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28369972 # number of overall hits +system.cpu.dcache.overall_hits::total 28369972 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1060525 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1060525 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 166997 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 166997 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1227522 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1227522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1227522 # number of overall misses +system.cpu.dcache.overall_misses::total 1227522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 21965060500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 21965060500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6217004264 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6217004264 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 153500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 153500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28182064764 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28182064764 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28182064764 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28182064764 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24862513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24862513 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5865 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5865 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29583085 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29583085 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29583085 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29583085 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040471 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040471 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037069 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037069 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001194 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001194 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039926 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039926 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039926 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039926 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5754.506681 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5754.506681 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26261.152391 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26261.152391 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8801.874028 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8801.874028 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8801.874028 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8801.874028 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23117548 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5877 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5877 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29597494 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29597494 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29597494 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29597494 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042656 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042656 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.035269 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001361 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001361 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.497136 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.497136 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37228.239214 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37228.239214 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22958.500755 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22958.500755 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 78852438 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8084 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9147 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2859.666997 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8620.579206 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942950 # number of writebacks -system.cpu.dcache.writebacks::total 942950 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101118 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132339 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 132339 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 233457 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 233457 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 233457 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 233457 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904500 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904500 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43183 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43183 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947683 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947683 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947683 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947683 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2400819500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2400819500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1075610609 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1075610609 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3476430109 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3476430109 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3476430109 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3476430109 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009120 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009120 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032035 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2654.305694 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2654.305694 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24908.195563 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24908.195563 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3668.347020 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3668.347020 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3668.347020 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3668.347020 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942869 # number of writebacks +system.cpu.dcache.writebacks::total 942869 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148009 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 148009 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131905 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 131905 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 279914 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 279914 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 279914 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 279914 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912516 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 912516 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35092 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 35092 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947608 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947608 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947608 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947608 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16755802500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16755802500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751499399 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751499399 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18507301899 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18507301899 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18507301899 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18507301899 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036702 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036702 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007411 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007411 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032016 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032016 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18362.201320 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18362.201320 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49911.643651 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49911.643651 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10511.051990 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1830916 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15498 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.138857 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10958.956435 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1839863 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15497 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.723818 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9660.066682 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 620.063738 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 230.921571 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.294802 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018923 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007047 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.320772 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903058 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903083 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942950 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942950 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 29811 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 29811 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932869 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932894 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932869 # number of overall hits -system.cpu.l2cache.overall_hits::total 932894 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 712 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 990 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 14536 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14536 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 712 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses +system.cpu.l2cache.occ_blocks::writebacks 10102.128367 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 622.173685 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 234.654384 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.308292 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018987 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34421.672516 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34481.160634 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35722.535211 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34421.672516 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34481.160634 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,59 +642,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31092.827004 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31208.955224 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31124.616956 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.364062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31103.364062 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32607.344633 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33704.797048 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32911.133810 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.353629 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.353629 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 8e4e9dec7..172c79802 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 78b502a64..092850ece 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:44:41 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:40:44 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 148083373000 because target called exit() +Exiting @ tick 148267705000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 63806d746..4b16c09c3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148083 # Number of seconds simulated -sim_ticks 148083373000 # Number of ticks simulated -final_tick 148083373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148268 # Number of seconds simulated +sim_ticks 148267705000 # Number of ticks simulated +final_tick 148267705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1433979 # Simulator instruction rate (inst/s) -host_op_rate 1444261 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2344399916 # Simulator tick rate (ticks/s) -host_mem_usage 365828 # Number of bytes of host memory used -host_seconds 63.16 # Real time elapsed on the host +host_inst_rate 1021914 # Simulator instruction rate (inst/s) +host_op_rate 1029241 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1672798092 # Simulator tick rate (ticks/s) +host_mem_usage 365748 # Number of bytes of host memory used +host_seconds 88.63 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 36992 # Nu system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 249805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6379974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6629779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 249805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 249805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 249805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6379974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6629779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 249495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6372042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6621536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 249495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 249495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 249495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6372042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6621536 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 296166746 # number of cpu cycles simulated +system.cpu.numCycles 296535410 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576861 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 27318810 # nu system.cpu.num_load_insts 22573966 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 296166746 # Number of busy cycles +system.cpu.num_busy_cycles 296535410 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 510.334547 # Cycle average of tags in use +system.cpu.icache.tagsinuse 510.369252 # Cycle average of tags in use system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.334547 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 510.369252 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.249204 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.249204 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32709000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32709000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32709000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32709000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32709000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32709000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54527.545910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54527.545910 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54606.010017 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54606.010017 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54606.010017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54606.010017 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30912000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30912000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30912000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30912000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30912000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30912000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51606.010017 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51606.010017 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements -system.cpu.dcache.tagsinuse 3568.539568 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3568.972050 # Cycle average of tags in use system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54479146000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3568.539568 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.871225 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.871225 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 54491057000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3568.972050 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.871331 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.871331 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses system.cpu.dcache.overall_misses::total 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12611634000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12611634000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13875176000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13875176000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13875176000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13875176000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12648933000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12648933000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1288595000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1288595000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13937528000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13937528000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13937528000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13937528000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.984570 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.984570 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14654.842955 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14654.842955 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14051.419202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14051.419202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27646.913686 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27646.913686 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14720.698607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14720.698607 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798 system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9948366000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9948366000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148768000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148768000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11097134000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11097134000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11097134000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11097134000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11051.419202 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11051.419202 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24646.913686 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24646.913686 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9598.880462 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 9602.986186 # Cycle average of tags in use system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8910.241595 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 495.387120 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 193.251747 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.271919 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.015118 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 8914.312589 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 495.421771 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 193.251826 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.272043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.015119 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.292935 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.293060 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits |