diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/se/10.mcf/ref/arm | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm')
4 files changed, 1261 insertions, 1107 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index a4eaa28e3..52746e018 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061494 # Nu sim_ticks 61493732000 # Number of ticks simulated final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 280016 # Simulator instruction rate (inst/s) -host_op_rate 281410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 190051649 # Simulator tick rate (ticks/s) -host_mem_usage 385752 # Number of bytes of host memory used -host_seconds 323.56 # Real time elapsed on the host +host_inst_rate 271090 # Simulator instruction rate (inst/s) +host_op_rate 272440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 183993432 # Simulator tick rate (ticks/s) +host_mem_usage 445016 # Number of bytes of host memory used +host_seconds 334.22 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # By system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation -system.physmem.totQLat 73246500 # Total ticks spent queuing -system.physmem.totMemAccLat 365277750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 73247750 # Total ticks spent queuing +system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.83 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.83 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 90.09 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 3948227.51 # Average gap between requests system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 56242943250 # Time in different power states -system.physmem.memoryStateTime::REF 2053220000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 3193793750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6320160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 5261760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3448500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2871000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 63663600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 57462600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2490497865 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2514078765 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34708310250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 34687625250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41288338695 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41283397695 # Total energy per rank (pJ) -system.physmem.averagePower::0 671.483256 # Core power per rank (mW) -system.physmem.averagePower::1 671.402899 # Core power per rank (mW) +system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.483541 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.402933 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20789429 # Number of BP lookups system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 98.812096 # BT system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -383,14 +420,14 @@ system.cpu.dcache.demand_misses::cpu.inst 988866 # n system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910311744 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11910311744 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345697500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2345697500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14256009244 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14256009244 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14256009244 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14256009244 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 14256024494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) @@ -411,14 +448,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14416.522809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14416.522809 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.315542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.478920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,14 +482,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958869756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958869756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333434750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333434750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292304506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11292304506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292304506 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11292304506 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses @@ -461,22 +498,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.411179 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.411179 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id @@ -556,13 +593,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10247.121792 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236502 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885294 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy @@ -593,14 +630,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 15583 # system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71718500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71718500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958069250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 958069250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1029787750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1029787750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1029787750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1029787750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71704250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958084250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1029788500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1029788500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) @@ -619,14 +656,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,14 +686,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58344750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58344750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774500250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774500250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832845000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 832845000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832845000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 832845000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses @@ -665,14 +702,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution @@ -705,7 +742,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # La system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428672494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1031 # Transaction distribution @@ -728,7 +765,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 15575 # Request fanout histogram system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 146202000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 3f4662e45..ea993d96c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057713 # Number of seconds simulated -sim_ticks 57712782000 # Number of ticks simulated -final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057719 # Number of seconds simulated +sim_ticks 57719377000 # Number of ticks simulated +final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133110 # Simulator instruction rate (inst/s) -host_op_rate 133773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84801314 # Simulator tick rate (ticks/s) -host_mem_usage 388280 # Number of bytes of host memory used -host_seconds 680.56 # Real time elapsed on the host +host_inst_rate 125223 # Simulator instruction rate (inst/s) +host_op_rate 125847 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79786059 # Simulator tick rate (ticks/s) +host_mem_usage 443544 # Number of bytes of host memory used +host_seconds 723.43 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory -system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory -system.physmem.bytes_written::total 73600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory -system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 17490 # Number of read requests accepted -system.physmem.writeReqs 1150 # Number of write requests accepted -system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory +system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory +system.physmem.bytes_written::total 19776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory +system.physmem.num_writes::total 309 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15872 # Number of read requests accepted +system.physmem.writeReqs 309 # Number of write requests accepted +system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue +system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1094 # Per bank write bursts -system.physmem.perBankRdBursts::1 953 # Per bank write bursts -system.physmem.perBankRdBursts::2 1083 # Per bank write bursts -system.physmem.perBankRdBursts::3 1113 # Per bank write bursts -system.physmem.perBankRdBursts::4 1125 # Per bank write bursts -system.physmem.perBankRdBursts::5 1235 # Per bank write bursts -system.physmem.perBankRdBursts::6 1314 # Per bank write bursts -system.physmem.perBankRdBursts::7 1243 # Per bank write bursts -system.physmem.perBankRdBursts::8 1060 # Per bank write bursts +system.physmem.perBankRdBursts::0 999 # Per bank write bursts +system.physmem.perBankRdBursts::1 876 # Per bank write bursts +system.physmem.perBankRdBursts::2 956 # Per bank write bursts +system.physmem.perBankRdBursts::3 1023 # Per bank write bursts +system.physmem.perBankRdBursts::4 1064 # Per bank write bursts +system.physmem.perBankRdBursts::5 1127 # Per bank write bursts +system.physmem.perBankRdBursts::6 1115 # Per bank write bursts +system.physmem.perBankRdBursts::7 1101 # Per bank write bursts +system.physmem.perBankRdBursts::8 1033 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 1021 # Per bank write bursts -system.physmem.perBankRdBursts::11 923 # Per bank write bursts -system.physmem.perBankRdBursts::12 921 # Per bank write bursts -system.physmem.perBankRdBursts::13 987 # Per bank write bursts -system.physmem.perBankRdBursts::14 1105 # Per bank write bursts -system.physmem.perBankRdBursts::15 1049 # Per bank write bursts -system.physmem.perBankWrBursts::0 72 # Per bank write bursts +system.physmem.perBankRdBursts::10 937 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 910 # Per bank write bursts +system.physmem.perBankRdBursts::13 886 # Per bank write bursts +system.physmem.perBankRdBursts::14 919 # Per bank write bursts +system.physmem.perBankRdBursts::15 912 # Per bank write bursts +system.physmem.perBankWrBursts::0 23 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 62 # Per bank write bursts -system.physmem.perBankWrBursts::3 19 # Per bank write bursts -system.physmem.perBankWrBursts::4 14 # Per bank write bursts -system.physmem.perBankWrBursts::5 111 # Per bank write bursts -system.physmem.perBankWrBursts::6 193 # Per bank write bursts -system.physmem.perBankWrBursts::7 122 # Per bank write bursts -system.physmem.perBankWrBursts::8 49 # Per bank write bursts +system.physmem.perBankWrBursts::2 4 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 9 # Per bank write bursts +system.physmem.perBankWrBursts::5 29 # Per bank write bursts +system.physmem.perBankWrBursts::6 62 # Per bank write bursts +system.physmem.perBankWrBursts::7 30 # Per bank write bursts +system.physmem.perBankWrBursts::8 15 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 68 # Per bank write bursts -system.physmem.perBankWrBursts::11 20 # Per bank write bursts -system.physmem.perBankWrBursts::12 15 # Per bank write bursts -system.physmem.perBankWrBursts::13 94 # Per bank write bursts -system.physmem.perBankWrBursts::14 168 # Per bank write bursts -system.physmem.perBankWrBursts::15 110 # Per bank write bursts +system.physmem.perBankWrBursts::10 10 # Per bank write bursts +system.physmem.perBankWrBursts::11 1 # Per bank write bursts +system.physmem.perBankWrBursts::12 9 # Per bank write bursts +system.physmem.perBankWrBursts::13 27 # Per bank write bursts +system.physmem.perBankWrBursts::14 48 # Per bank write bursts +system.physmem.perBankWrBursts::15 21 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57712604500 # Total gap between requests +system.physmem.totGap 57719226000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 17490 # Read request sizes (log2) +system.physmem.readPktSize::6 15872 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1150 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,118 +197,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads -system.physmem.totQLat 228948216 # Total ticks spent queuing -system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads +system.physmem.totQLat 179464908 # Total ticks spent queuing +system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.16 # Data bus utilization in percentage -system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing -system.physmem.readRowHits 14950 # Number of row buffer hits during reads -system.physmem.writeRowHits 375 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes -system.physmem.avgGap 3096169.77 # Average gap between requests -system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states -system.physmem.memoryStateTime::REF 1927120000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 11854080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 10636920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 6468000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 5803875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 71299800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 62602800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3842640 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3395520 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2993861160 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3031288785 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 32001000000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 31968168750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 38857772400 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 38851343370 # Total energy per rank (pJ) -system.physmem.averagePower::0 673.305017 # Core power per rank (mW) -system.physmem.averagePower::1 673.193618 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 17158 # Transaction distribution -system.membus.trans_dist::ReadResp 17158 # Transaction distribution -system.membus.trans_dist::Writeback 1150 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 332 # Transaction distribution -system.membus.trans_dist::ReadExResp 332 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 18642 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18642 # Request fanout histogram -system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 28272297 # Number of BP lookups -system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing +system.physmem.readRowHits 14166 # Number of row buffer hits during reads +system.physmem.writeRowHits 92 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes +system.physmem.avgGap 3567098.82 # Average gap between requests +system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.607894 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states +system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.433104 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states +system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 28271166 # Number of BP lookups +system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -330,6 +316,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -351,6 +345,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -372,6 +374,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -394,83 +404,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 115425565 # number of cpu cycles simulated +system.cpu.numCycles 115438755 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679445 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -478,9 +488,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available @@ -509,12 +519,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued @@ -537,90 +547,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued -system.cpu.iq.rate 0.878733 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued +system.cpu.iq.rate 0.878644 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12666 # number of nop insts executed -system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed -system.cpu.iew.exec_branches 20629033 # Number of branches executed -system.cpu.iew.exec_stores 4918889 # Number of stores executed -system.cpu.iew.exec_rate 0.867621 # Inst execution rate -system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59710820 # num instructions producing a value -system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value +system.cpu.iew.exec_nop 12667 # number of nop insts executed +system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed +system.cpu.iew.exec_branches 20629236 # Number of branches executed +system.cpu.iew.exec_stores 4918943 # Number of stores executed +system.cpu.iew.exec_rate 0.867532 # Inst execution rate +system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59706662 # num instructions producing a value +system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back +system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -666,396 +676,79 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction -system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 217038076 # The number of ROB reads -system.cpu.rob.rob_writes 219583065 # The number of ROB writes -system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 217026090 # The number of ROB reads +system.cpu.rob.rob_writes 219584249 # The number of ROB writes +system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads -system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108123923 # number of integer regfile reads -system.cpu.int_regfile_writes 58738896 # number of integer regfile writes +system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads +system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108125012 # number of integer regfile reads +system.cpu.int_regfile_writes 58739124 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 100 # number of floating regfile writes -system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads -system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes -system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads +system.cpu.fp_regfile_writes 99 # number of floating regfile writes +system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads +system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes +system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 28370 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 456 # number of replacements -system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits -system.cpu.icache.overall_hits::total 32315555 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses -system.cpu.icache.overall_misses::total 1024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 1672 # number of replacements -system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10807.797190 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 104.008842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 299.224972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1347.657528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.659656 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006348 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.018263 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082254 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.766522 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1557 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1370 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 12200 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.095032 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.872864 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 174560305 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 174560305 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 753 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5260483 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5261236 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 5407164 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 5407164 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224791 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224791 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 753 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5485274 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5486027 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 753 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5485274 # number of overall hits -system.cpu.l2cache.overall_hits::total 5486027 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 993 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1156 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 496 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 496 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1489 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1652 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1489 # number of overall misses -system.cpu.l2cache.overall_misses::total 1652 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12439500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59393247 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71832747 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31513998 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 31513998 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12439500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 90907245 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 103346745 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12439500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 90907245 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 103346745 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 916 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 5261476 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5262392 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 5407164 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 5407164 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 225287 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 225287 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 916 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5486763 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5487679 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 916 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5486763 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5487679 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177948 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000189 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000220 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002202 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002202 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177948 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000271 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000301 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177948 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000271 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000301 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76315.950920 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59811.930514 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62139.054498 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63536.286290 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63536.286290 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62558.562349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62558.562349 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 50 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16.400000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1150 # number of writebacks -system.cpu.l2cache.writebacks::total 1150 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 256 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 418 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 442 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 418 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 442 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 139 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26554 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10286000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 72273751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 5486251 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5486247 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits -system.cpu.dcache.overall_hits::total 18263549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits +system.cpu.dcache.overall_hits::total 18263472 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses -system.cpu.dcache.overall_misses::total 9970085 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses +system.cpu.dcache.overall_misses::total 9970594 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) @@ -1064,92 +757,452 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks -system.cpu.dcache.writebacks::total 5407164 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks +system.cpu.dcache.writebacks::total 5460017 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154868 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4483830 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4483830 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4483830 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4483830 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263967 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5263967 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222789 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222789 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194331 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.194331 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7256.749186 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7256.749186 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9715.487663 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9715.487663 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50100 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50100 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7356.585936 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7356.585936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 447 # number of replacements +system.cpu.icache.tags.tagsinuse 428.924531 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32314402 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35667.110375 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 64631998 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64631998 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32314402 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32314402 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32314402 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32314402 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32314402 # number of overall hits +system.cpu.icache.overall_hits::total 32314402 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1144 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1144 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 214 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1059 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 21606 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36534500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16113750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52648250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 777111161 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 22591778 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 22591778 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36534500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 38705528 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 75240028 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36534500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 38705528 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 852351189 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 22341 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 15531 # Transaction distribution +system.membus.trans_dist::ReadResp 15531 # Transaction distribution +system.membus.trans_dist::Writeback 309 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 341 # Transaction distribution +system.membus.trans_dist::ReadExResp 341 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 16183 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 16183 # Request fanout histogram +system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 0aa02b40d..16d507b60 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000000 # Number of ticks simulated final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2068738 # Simulator instruction rate (inst/s) -host_op_rate 2079040 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1236208278 # Simulator tick rate (ticks/s) -host_mem_usage 428768 # Number of bytes of host memory used -host_seconds 43.80 # Real time elapsed on the host +host_inst_rate 1669323 # Simulator instruction rate (inst/s) +host_op_rate 1677636 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 997531404 # Simulator tick rate (ticks/s) +host_mem_usage 433488 # Number of bytes of host memory used +host_seconds 54.28 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 349238802 # Wr system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 130287905 # Transaction distribution -system.membus.trans_dist::ReadResp 130291792 # Transaction distribution -system.membus.trans_dist::WriteReq 4734981 # Transaction distribution -system.membus.trans_dist::WriteResp 4734981 # Transaction distribution -system.membus.trans_dist::SoftPFReq 510 # Transaction distribution -system.membus.trans_dist::SoftPFResp 510 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 135031170 # Request fanout histogram -system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 135031170 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction +system.membus.trans_dist::ReadReq 130287905 # Transaction distribution +system.membus.trans_dist::ReadResp 130291792 # Transaction distribution +system.membus.trans_dist::WriteReq 4734981 # Transaction distribution +system.membus.trans_dist::WriteResp 4734981 # Transaction distribution +system.membus.trans_dist::SoftPFReq 510 # Transaction distribution +system.membus.trans_dist::SoftPFResp 510 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 135031170 # Request fanout histogram +system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 135031170 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index b163f38c3..3f9742fb4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147041 # Nu sim_ticks 147041218000 # Number of ticks simulated final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130471 # Simulator instruction rate (inst/s) -host_op_rate 1136089 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1835190843 # Simulator tick rate (ticks/s) -host_mem_usage 438268 # Number of bytes of host memory used -host_seconds 80.12 # Real time elapsed on the host +host_inst_rate 1114927 # Simulator instruction rate (inst/s) +host_op_rate 1120467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1809956176 # Simulator tick rate (ticks/s) +host_mem_usage 442716 # Number of bytes of host memory used +host_seconds 81.24 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 251576 # In system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 792 # Transaction distribution -system.membus.trans_dist::ReadResp 792 # Transaction distribution -system.membus.trans_dist::ReadExReq 14548 # Transaction distribution -system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15340 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,144 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits +system.cpu.dcache.overall_hits::total 26245827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses +system.cpu.dcache.overall_misses::total 946799 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks +system.cpu.dcache.writebacks::total 942334 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. @@ -429,144 +576,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits -system.cpu.dcache.overall_hits::total 26245827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses -system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks -system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution @@ -600,5 +609,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 898500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 792 # Transaction distribution +system.membus.trans_dist::ReadResp 792 # Transaction distribution +system.membus.trans_dist::ReadExReq 14548 # Transaction distribution +system.membus.trans_dist::ReadExResp 14548 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15340 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15340 # Request fanout histogram +system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |