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authorSteve Reinhardt <stever@gmail.com>2013-09-28 15:25:17 -0400
committerSteve Reinhardt <stever@gmail.com>2013-09-28 15:25:17 -0400
commitfbc1feb39ac19379983ca714f4c7fadcd9fdabf6 (patch)
tree59e49142d5930eb044e9fc09d94c5060a810d545 /tests/long/se/10.mcf/ref/arm
parente5c319db43751f45b2bcca1d018fc39d4561ef9c (diff)
downloadgem5-fbc1feb39ac19379983ca714f4c7fadcd9fdabf6.tar.xz
tests: update reference outputs
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm')
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini91
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini43
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout6
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini83
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-timing/simout6
6 files changed, 169 insertions, 68 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index c6185ffda..108881308 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
+simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
-globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
-localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
[system.cpu.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
response_latency=2
size=262144
system=system
+tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
[system.cpu.dtb]
type=ArmTLB
children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
[system.cpu.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
response_latency=2
size=131072
system=system
+tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
[system.cpu.interrupts]
type=ArmInterrupts
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
response_latency=20
size=2097152
system=system
+tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
[system.cpu.toL2Bus]
type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -528,9 +559,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -539,10 +570,14 @@ simpoint=55300000000
system=system
uid=100
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
[system.membus]
type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
banks_per_rank=8
+burst_length=8
channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
in_addr_map=true
-lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:268435455
ranks_per_channel=2
read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
tBURST=5000
tCL=13750
tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
-zero=false
port=system.membus.master[0]
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 276747f08..9be633e93 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 01:31:22
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:20:51
+gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -25,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 26780899500 because target called exit()
+Exiting @ tick 26877484000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 4ab5b0af3..e8dafcae9 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
-branchPred=Null
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -120,9 +129,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -131,11 +140,16 @@ simpoint=55300000000
system=system
uid=100
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
[system.membus]
type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
-zero=false
port=system.membus.master[0]
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
index 6c1085aa7..a5dbe98d0 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:04:57
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:18:17
+gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 75d632a3d..08fdda12e 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+simpoint_start_insts=
switched_out=false
system=system
tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
response_latency=2
size=262144
system=system
+tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
[system.cpu.dtb]
type=ArmTLB
children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
response_latency=2
size=131072
system=system
+tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
[system.cpu.interrupts]
type=ArmInterrupts
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
response_latency=20
size=2097152
system=system
+tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
[system.cpu.toL2Bus]
type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@@ -192,9 +225,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -203,11 +236,16 @@ simpoint=55300000000
system=system
uid=100
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
[system.membus]
type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
-zero=false
port=system.membus.master[0]
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index ceb59a6aa..c84bc1d04 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:06:05
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:24:43
+gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...