diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/10.mcf/ref/arm | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm')
9 files changed, 631 insertions, 406 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index cbe079647..ae17312a7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,14 +508,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 3ae44ae93..bc658a4d7 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:22 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:46:15 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 833e2ce53..0264f97d4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.033081 # Nu sim_ticks 33080570000 # Number of ticks simulated final_tick 33080570000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45520 # Simulator instruction rate (inst/s) -host_tick_rate 16502276 # Simulator tick rate (ticks/s) -host_mem_usage 388968 # Number of bytes of host memory used -host_seconds 2004.61 # Real time elapsed on the host -sim_insts 91249885 # Number of instructions simulated +host_inst_rate 183696 # Simulator instruction rate (inst/s) +host_op_rate 185015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67072888 # Simulator tick rate (ticks/s) +host_mem_usage 356156 # Number of bytes of host memory used +host_seconds 493.20 # Real time elapsed on the host +sim_insts 90599331 # Number of instructions simulated +sim_ops 91249885 # Number of ops (including micro ops) simulated system.physmem.bytes_read 997440 # Number of bytes read from this memory system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 90611940 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262494 # The number of committed instructions system.cpu.commit.commitSquashedInsts 26696996 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle -system.cpu.commit.count 91262494 # Number of instructions committed +system.cpu.commit.committedInsts 90611940 # Number of instructions committed +system.cpu.commit.committedOps 91262494 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 27322621 # Number of memory references committed system.cpu.commit.loads 22575872 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 175546960 # Th system.cpu.rob.rob_writes 239939856 # The number of ROB writes system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 91249885 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated -system.cpu.cpi 0.725055 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.725055 # CPI: Total CPI of All Threads -system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads +system.cpu.committedInsts 90599331 # Number of Instructions Simulated +system.cpu.committedOps 91249885 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599331 # Number of Instructions Simulated +system.cpu.cpi 0.730261 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.730261 # CPI: Total CPI of All Threads +system.cpu.ipc 1.369374 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.369374 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 496902735 # number of integer regfile reads system.cpu.int_regfile_writes 120936098 # number of integer regfile writes system.cpu.fp_regfile_reads 197 # number of floating regfile reads @@ -336,26 +341,39 @@ system.cpu.icache.total_refs 14743811 # To system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 20420.790859 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 611.587679 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 14743811 # number of ReadReq hits -system.cpu.icache.demand_hits 14743811 # number of demand (read+write) hits -system.cpu.icache.overall_hits 14743811 # number of overall hits -system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses -system.cpu.icache.demand_misses 916 # number of demand (read+write) misses -system.cpu.icache.overall_misses 916 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 14744727 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 14744727 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 14744727 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35344.978166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35344.978166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35344.978166 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 611.587679 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.298627 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.298627 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14743811 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14743811 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14743811 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14743811 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14743811 # number of overall hits +system.cpu.icache.overall_hits::total 14743811 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 916 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 916 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 916 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 916 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 916 # number of overall misses +system.cpu.icache.overall_misses::total 916 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32376000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32376000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32376000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32376000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32376000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32376000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14744727 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14744727 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14744727 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14744727 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14744727 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14744727 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000062 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000062 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000062 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35344.978166 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,27 +382,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 194 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 194 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 24887000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 24887000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 24887000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 194 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 194 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 194 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 194 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24887000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24887000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24887000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24887000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24887000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24887000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34469.529086 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 943456 # number of replacements system.cpu.dcache.tagsinuse 3558.808733 # Cycle average of tags in use @@ -392,40 +413,63 @@ system.cpu.dcache.total_refs 28819271 # To system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 30.414448 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3558.808733 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24247440 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 28806682 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 28806682 # number of overall hits -system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1165006 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5475545000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4498707428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 9974252428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9974252428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 25236707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 29971688 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 29971688 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 5534.951636 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 25598.799515 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 8561.545973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 8561.545973 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3558.808733 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.868850 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.868850 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 24247440 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24247440 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4559242 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4559242 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6797 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6797 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5792 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5792 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28806682 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28806682 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28806682 # number of overall hits +system.cpu.dcache.overall_hits::total 28806682 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 989267 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 989267 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 175739 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 175739 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1165006 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1165006 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1165006 # number of overall misses +system.cpu.dcache.overall_misses::total 1165006 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5475545000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5475545000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4498707428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4498707428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 124500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 124500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9974252428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9974252428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9974252428 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9974252428 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 25236707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 25236707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6804 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6804 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5792 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5792 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29971688 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29971688 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29971688 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29971688 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039200 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037115 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001029 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038870 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038870 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5534.951636 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25598.799515 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17785.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked @@ -434,33 +478,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942907 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 86240 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 131213 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 217453 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 217453 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 903027 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 44526 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2253076500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1081063056 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3334139556 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3334139556 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.026727 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.366123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 942907 # number of writebacks +system.cpu.dcache.writebacks::total 942907 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86240 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 86240 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131213 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 131213 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 217453 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 217453 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 217453 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 217453 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903027 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903027 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 44526 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 44526 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947553 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947553 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947553 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947553 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2253076500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2253076500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1081063056 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1081063056 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3334139556 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3334139556 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3334139556 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3334139556 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035782 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009404 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2495.026727 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24279.366123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 744 # number of replacements system.cpu.l2cache.tagsinuse 9229.669691 # Cycle average of tags in use @@ -468,36 +521,75 @@ system.cpu.l2cache.total_refs 1596774 # To system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 392.792276 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8836.877415 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942907 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 31267 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 932680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 932680 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1057 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 14538 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.317389 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34304.071818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34304.071818 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 8836.877415 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 199.760007 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 193.032269 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.269680 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.006096 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24071000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 36209000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 498763000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 498763000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24071000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 510901000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 534972000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24071000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 510901000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 534972000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 901748 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 902470 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942907 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942907 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 45805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 45805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947553 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948275 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947553 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948275 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.972299 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000394 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.317389 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.972299 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015717 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.972299 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015717 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.173789 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34191.549296 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34307.538864 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -506,31 +598,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 32 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1047 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15585 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 32560500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 484338000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 484338000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001160 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016435 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016435 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks +system.cpu.l2cache.writebacks::total 32 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 701 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 346 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1047 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14884 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14884 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15585 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21793500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10767000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32560500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451777500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451777500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21793500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 484338000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21793500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 484338000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000384 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.317389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31089.158345 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31118.497110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31075.629385 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 67a5d19a5..75c90b82c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index 902784594..f67da13a2 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:47:31 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:51:19 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 66ab48bd5..393a58e49 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.054241 # Nu sim_ticks 54240666000 # Number of ticks simulated final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2777644 # Simulator instruction rate (inst/s) -host_tick_rate 1651027932 # Simulator tick rate (ticks/s) -host_mem_usage 342980 # Number of bytes of host memory used -host_seconds 32.85 # Real time elapsed on the host -sim_insts 91252969 # Number of instructions simulated +host_inst_rate 3177444 # Simulator instruction rate (inst/s) +host_op_rate 3200257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1902228216 # Simulator tick rate (ticks/s) +host_mem_usage 345536 # Number of bytes of host memory used +host_seconds 28.51 # Real time elapsed on the host +sim_insts 90602415 # Number of instructions simulated +sim_ops 91252969 # Number of ops (including micro ops) simulated system.physmem.bytes_read 521339715 # Number of bytes read from this memory system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory system.physmem.bytes_written 18908138 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 442 # Nu system.cpu.numCycles 108481333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91252969 # Number of instructions executed +system.cpu.committedInsts 90602415 # Number of instructions committed +system.cpu.committedOps 91252969 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 2f73411a5..14eb2c781 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 959967602..d74925785 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:48:15 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:51:58 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index d6f3be234..27b93150e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.148086 # Nu sim_ticks 148086239000 # Number of ticks simulated final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1300672 # Simulator instruction rate (inst/s) -host_tick_rate 2111359212 # Simulator tick rate (ticks/s) -host_mem_usage 351948 # Number of bytes of host memory used -host_seconds 70.14 # Real time elapsed on the host -sim_insts 91226321 # Number of instructions simulated +host_inst_rate 1696896 # Simulator instruction rate (inst/s) +host_op_rate 1709063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2774293546 # Simulator tick rate (ticks/s) +host_mem_usage 354444 # Number of bytes of host memory used +host_seconds 53.38 # Real time elapsed on the host +sim_insts 90576869 # Number of instructions simulated +sim_ops 91226321 # Number of ops (including micro ops) simulated system.physmem.bytes_read 986112 # Number of bytes read from this memory system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 442 # Nu system.cpu.numCycles 296172478 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91226321 # Number of instructions executed +system.cpu.committedInsts 90576869 # Number of instructions committed +system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 107830181 # To system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits -system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits -system.cpu.icache.overall_hits 107830181 # number of overall hits -system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses -system.cpu.icache.demand_misses 599 # number of demand (read+write) misses -system.cpu.icache.overall_misses 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits +system.cpu.icache.overall_hits::total 107830181 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses +system.cpu.icache.overall_misses::total 599 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 26345365 # To system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26337591 # number of overall hits -system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses -system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits +system.cpu.dcache.overall_hits::total 26337591 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses +system.cpu.dcache.overall_misses::total 946798 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12614490000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12614490000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13878032000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13878032000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13878032000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13878032000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22549408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22549408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27284389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27284389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942309 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks +system.cpu.dcache.writebacks::total 942309 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9913923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9913923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11037638000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 634 # number of replacements system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 1594542 # To system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 899928 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 32061 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 931989 # number of overall hits -system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 14548 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15408 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 756496000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 900788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 8910.209882 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 165.071875 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 160.025936 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.271918 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.005038 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004884 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.281839 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 899907 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 899928 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942309 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942309 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 931968 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 931989 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 931968 # number of overall hits +system.cpu.l2cache.overall_hits::total 931989 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 860 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14830 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15408 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14830 # number of overall misses +system.cpu.l2cache.overall_misses::total 15408 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14664000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 44720000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 771160000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 801216000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 771160000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 801216000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942309 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942309 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 32 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks +system.cpu.l2cache.writebacks::total 32 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 282 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 860 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14830 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14830 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15408 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 593200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 616320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |