diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/se/10.mcf/ref/arm | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini | 29 | ||||
| -rwxr-xr-x | tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout | 12 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1273 |
3 files changed, 660 insertions, 654 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index fd7ad70a0..239f60df1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,9 +699,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/mcf +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:268435455 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index c4b7fa411..f37d93ec9 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:10:45 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:33:12 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x50d0380 + 0: system.cpu.isa: ISA system set to: 0 0x666d940 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -24,4 +24,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 26911921000 because target called exit() +Exiting @ tick 26894328500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index a24a01894..b6a9feb5d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026909 # Number of seconds simulated -sim_ticks 26909234500 # Number of ticks simulated -final_tick 26909234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026894 # Number of seconds simulated +sim_ticks 26894328500 # Number of ticks simulated +final_tick 26894328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142304 # Simulator instruction rate (inst/s) -host_op_rate 143325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42270537 # Simulator tick rate (ticks/s) -host_mem_usage 446544 # Number of bytes of host memory used -host_seconds 636.60 # Real time elapsed on the host +host_inst_rate 165934 # Simulator instruction rate (inst/s) +host_op_rate 167125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49262466 # Simulator tick rate (ticks/s) +host_mem_usage 394132 # Number of bytes of host memory used +host_seconds 545.94 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 45184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory system.physmem.bytes_read::total 992640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 45184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45184 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1671991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35216461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36888452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1671991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1671991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1671991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35216461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36888452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1680057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35228840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36908897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1680057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1680057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1680057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35228840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36908897 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15510 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue @@ -40,22 +40,22 @@ system.physmem.bytesReadSys 992640 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 987 # Per bank write bursts system.physmem.perBankRdBursts::1 885 # Per bank write bursts system.physmem.perBankRdBursts::2 942 # Per bank write bursts -system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::3 1029 # Per bank write bursts +system.physmem.perBankRdBursts::4 1048 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1080 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 957 # Per bank write bursts -system.physmem.perBankRdBursts::10 935 # Per bank write bursts +system.physmem.perBankRdBursts::10 936 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 905 # Per bank write bursts -system.physmem.perBankRdBursts::13 865 # Per bank write bursts -system.physmem.perBankRdBursts::14 877 # Per bank write bursts +system.physmem.perBankRdBursts::13 863 # Per bank write bursts +system.physmem.perBankRdBursts::14 876 # Per bank write bursts system.physmem.perBankRdBursts::15 896 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26909036500 # Total gap between requests +system.physmem.totGap 26894128500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 726.491563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 533.334896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.223532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 140 10.27% 10.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 158 11.59% 21.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56 4.11% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.99% 30.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 4.18% 35.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.86% 38.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 1.76% 39.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.86% 42.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 782 57.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1363 # Bytes accessed per row activation -system.physmem.totQLat 83369750 # Total ticks spent queuing -system.physmem.totMemAccLat 374182250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 726.489019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 530.637647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.552146 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 153 11.20% 11.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146 10.69% 21.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 54 3.95% 25.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 4.76% 30.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 4.17% 34.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 3.00% 37.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 2.56% 40.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.42% 42.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 782 57.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1366 # Bytes accessed per row activation +system.physmem.totQLat 88775250 # Total ticks spent queuing +system.physmem.totMemAccLat 379587750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5375.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5723.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24125.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24473.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage @@ -216,44 +216,44 @@ system.physmem.busUtilRead 0.29 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14137 # Number of row buffer hits during reads +system.physmem.readRowHits 14143 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads +system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734947.55 # Average gap between requests -system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 24303660500 # Time in different power states -system.physmem.memoryStateTime::REF 898300000 # Time in different power states +system.physmem.avgGap 1733986.36 # Average gap between requests +system.physmem.pageHitRate 91.19 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 24303280500 # Time in different power states +system.physmem.memoryStateTime::REF 898040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1704463000 # Time in different power states +system.physmem.memoryStateTime::ACT 1692660750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 36888452 # Throughput (bytes/s) +system.membus.throughput 36908897 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 972 # Transaction distribution system.membus.trans_dist::ReadResp 972 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31026 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31026 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31022 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 992640 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19094500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 18401000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145899997 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145166999 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 26684247 # Number of BP lookups -system.cpu.branchPred.condPredicted 22003797 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 841589 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11372801 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11278925 # Number of BTB hits +system.cpu.branchPred.lookups 27364118 # Number of BP lookups +system.cpu.branchPred.condPredicted 22575249 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 843312 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11626081 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11546341 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.174557 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69990 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.314128 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70079 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 187 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,239 +339,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53818470 # number of cpu cycles simulated +system.cpu.numCycles 53788658 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14166768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127874482 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26684247 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11348915 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24030832 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4761225 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11326508 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14474692 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 130915195 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27364118 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11616420 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24576695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5106515 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 9886759 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13838942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329737 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53427318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409937 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14156505 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 349331 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53187301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.478661 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.235073 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29434889 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3387974 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2027945 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1552978 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1665988 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2918810 5.46% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1512193 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1089826 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9836715 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 28648969 53.86% 53.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3469200 6.52% 60.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2052434 3.86% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1567853 2.95% 67.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1679873 3.16% 70.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3021837 5.68% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1566641 2.95% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1116795 2.10% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10063699 18.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53427318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495820 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.376033 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16930628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9172800 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22402161 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1027234 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3894495 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4441775 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8644 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126055074 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42561 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3894495 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18710503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3595532 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 186271 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21547494 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5493023 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123139917 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 426575 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4604902 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1527 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143588109 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536432016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499923969 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 641 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53187301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.508734 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.433881 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16310855 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8657573 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23455900 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 522552 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4240421 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4543490 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8671 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 129206748 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42514 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4240421 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17921369 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2850180 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 191379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 22351654 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5632298 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 126131712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1889841 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 3251328 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 563418 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3246 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 146876533 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 549573070 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 512042051 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 826 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36173923 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4624 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4622 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12547663 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29472846 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5519091 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2169224 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1269381 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118159243 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8489 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105145248 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78272 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26728441 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65602174 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 271 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53427318 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968005 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908888 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 39462347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4633 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4631 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9072079 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30275485 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5599467 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2184620 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1363504 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 120806561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8485 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105954089 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 91175 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 29372689 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73925597 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 267 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53187301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.992094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.919550 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15370604 28.77% 28.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11662585 21.83% 50.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8230563 15.41% 66.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6832993 12.79% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4979120 9.32% 88.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2926966 5.48% 93.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2444206 4.57% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 536236 1.00% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 444045 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15526622 29.19% 29.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10753574 20.22% 49.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8641028 16.25% 65.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6157106 11.58% 77.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5949684 11.19% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2742880 5.16% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2429206 4.57% 98.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 538839 1.01% 99.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 448362 0.84% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53427318 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53187301 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 46059 6.94% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 26 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 341162 51.43% 58.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276052 41.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 44574 8.99% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 174239 35.13% 44.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277108 55.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74418244 70.78% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 122 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 157 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25603497 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5112252 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 75094311 70.87% 70.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10550 0.01% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 140 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 196 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25720178 24.27% 95.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5128709 4.84% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105145248 # Type of FU issued -system.cpu.iq.rate 1.953702 # Inst issue rate -system.cpu.iq.fu_busy_cnt 663299 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006308 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264458762 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144900942 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102674293 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 623 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 845 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 263 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105808235 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 312 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 440410 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105954089 # Type of FU issued +system.cpu.iq.rate 1.969822 # Inst issue rate +system.cpu.iq.fu_busy_cnt 495948 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004681 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 265681854 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 150192687 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 103425723 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 748 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1061 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 319 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106449666 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 371 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 469381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6898880 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6071 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6331 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 774247 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7701519 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7870 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6982 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 854623 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31563 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 30068 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3894495 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 960394 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127228 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118180427 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309851 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29472846 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5519091 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4601 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65954 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6808 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6331 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446096 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445462 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891558 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104169534 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25284727 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 975714 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4240421 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 731718 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 478226 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 120827778 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309730 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30275485 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5599467 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4597 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 72415 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 359917 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6982 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447833 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 447193 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 895026 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104954211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25387781 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 999878 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12695 # number of nop insts executed -system.cpu.iew.exec_refs 30339844 # number of memory reference insts executed -system.cpu.iew.exec_branches 21324580 # Number of branches executed -system.cpu.iew.exec_stores 5055117 # Number of stores executed -system.cpu.iew.exec_rate 1.935572 # Inst execution rate -system.cpu.iew.wb_sent 102952816 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102674556 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62244775 # num instructions producing a value -system.cpu.iew.wb_consumers 104288684 # num instructions consuming a value +system.cpu.iew.exec_nop 12732 # number of nop insts executed +system.cpu.iew.exec_refs 30458601 # number of memory reference insts executed +system.cpu.iew.exec_branches 21526378 # Number of branches executed +system.cpu.iew.exec_stores 5070820 # Number of stores executed +system.cpu.iew.exec_rate 1.951233 # Inst execution rate +system.cpu.iew.wb_sent 103717343 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 103426042 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62672484 # num instructions producing a value +system.cpu.iew.wb_consumers 105780863 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907794 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596851 # average fanout of values written-back +system.cpu.iew.wb_rate 1.922823 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.592475 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26930418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 29588025 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833018 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49532823 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842273 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541112 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834722 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 48946880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.864326 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.553843 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20056290 40.49% 40.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13134081 26.52% 67.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4165062 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431851 6.93% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1531687 3.09% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 719294 1.45% 86.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 966848 1.95% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 252784 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5274926 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19590544 40.02% 40.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13003525 26.57% 66.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4154420 8.49% 75.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3492472 7.14% 82.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1473630 3.01% 85.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 727145 1.49% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 923215 1.89% 88.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 261788 0.53% 89.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5320141 10.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49532823 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 48946880 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -617,238 +618,236 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction -system.cpu.commit.bw_lim_events 5274926 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5320141 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162435541 # The number of ROB reads -system.cpu.rob.rob_writes 240280947 # The number of ROB writes -system.cpu.timesIdled 46113 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 391152 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 164461990 # The number of ROB reads +system.cpu.rob.rob_writes 245943119 # The number of ROB writes +system.cpu.timesIdled 58216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 601357 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.594090 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594090 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683247 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683247 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495503749 # number of integer regfile reads -system.cpu.int_regfile_writes 120538753 # number of integer regfile writes -system.cpu.fp_regfile_reads 136 # number of floating regfile reads -system.cpu.fp_regfile_writes 324 # number of floating regfile writes -system.cpu.misc_regfile_reads 29202777 # number of misc regfile reads +system.cpu.cpi 0.593761 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.593761 # CPI: Total CPI of All Threads +system.cpu.ipc 1.684180 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.684180 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 499033245 # number of integer regfile reads +system.cpu.int_regfile_writes 121427335 # number of integer regfile writes +system.cpu.fp_regfile_reads 166 # number of floating regfile reads +system.cpu.fp_regfile_writes 402 # number of floating regfile writes +system.cpu.misc_regfile_reads 29301616 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4498112646 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904542 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942913 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43808 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838157 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888546500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4500548582 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 907410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 907410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 40933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 40933 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120992384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121039168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121039168 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888514500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1214249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1215999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424437743 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424171240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 629.782020 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13837957 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 727 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19034.328748 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 631.006365 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14155509 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 731 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19364.581395 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 629.782020 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.307511 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.307511 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 723 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 671 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.353027 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27678613 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27678613 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13837957 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13837957 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13837957 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13837957 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13837957 # number of overall hits -system.cpu.icache.overall_hits::total 13837957 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses -system.cpu.icache.overall_misses::total 984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66510498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66510498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66510498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66510498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66510498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66510498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13838941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13838941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13838941 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13838941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13838941 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13838941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67591.969512 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67591.969512 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67591.969512 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67591.969512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67591.969512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67591.969512 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 649 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 631.006365 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308109 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308109 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 728 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.355469 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 28313740 # Number of tag accesses +system.cpu.icache.tags.data_accesses 28313740 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 14155509 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14155509 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14155509 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14155509 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14155509 # number of overall hits +system.cpu.icache.overall_hits::total 14155509 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 995 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 995 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 995 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 995 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 995 # number of overall misses +system.cpu.icache.overall_misses::total 995 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67178998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67178998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67178998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67178998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67178998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67178998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14156504 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14156504 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14156504 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14156504 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14156504 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14156504 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67516.580905 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67516.580905 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 593 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.083333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 252 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 252 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 252 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 252 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 252 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 263 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 263 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 263 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 263 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 732 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50737500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50737500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50737500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50737500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50737500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50737500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69313.524590 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69313.524590 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69313.524590 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69313.524590 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69313.524590 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69313.524590 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50814250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50814250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50814250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50814250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50814250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50814250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # 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Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 461 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3114 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 521 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 452 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3133 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 59974850 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 59974850 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23597129 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23597129 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532332 # 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number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28129461 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28129461 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28129461 # number of overall hits -system.cpu.dcache.overall_hits::total 28129461 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173693 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173693 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202649 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202649 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1376342 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1376342 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1376342 # number of overall misses -system.cpu.dcache.overall_misses::total 1376342 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13892857479 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13892857479 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8552070346 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8552070346 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22444927825 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22444927825 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22444927825 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22444927825 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24770822 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24770822 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 28221779 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28221779 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28221779 # number of overall hits +system.cpu.dcache.overall_hits::total 28221779 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1169644 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1169644 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 190007 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 190007 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1359651 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1359651 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1359651 # number of overall misses +system.cpu.dcache.overall_misses::total 1359651 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13867675477 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13867675477 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8610605390 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8610605390 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 264500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 264500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22478280867 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22478280867 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22478280867 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22478280867 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24846449 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24846449 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29505803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29505803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29505803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29505803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047382 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047382 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042798 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042798 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001783 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001783 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046646 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046646 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046646 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046646 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.875127 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.875127 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42201.394263 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42201.394263 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16307.667589 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16307.667589 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16307.667589 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16307.667589 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154301 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29581430 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29581430 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29581430 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29581430 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047075 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047075 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040128 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040128 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.045963 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.045963 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.045963 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.045963 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16532.390199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16532.390199 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 136970 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23947 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 24472 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.443438 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.597009 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942913 # number of writebacks -system.cpu.dcache.writebacks::total 942913 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269863 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269863 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158857 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158857 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903830 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903830 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43792 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43792 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947622 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947622 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947622 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947622 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9993578260 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9993578260 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1330001932 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1330001932 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323580192 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11323580192 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323580192 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11323580192 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036488 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036488 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009249 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009249 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.922496 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.922496 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30370.888107 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30370.888107 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.469506 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.469506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.469506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.469506 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942895 # number of writebacks +system.cpu.dcache.writebacks::total 942895 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262958 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 262958 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 149081 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 149081 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 412039 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 412039 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 412039 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 412039 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906686 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906686 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40926 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 40926 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947612 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947612 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947612 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947612 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10019308761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10019308761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1304642257 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1304642257 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323951018 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11323951018 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323951018 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11323951018 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008643 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008643 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032034 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |