diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/10.mcf/ref/arm | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm')
4 files changed, 1321 insertions, 1289 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index afbdccd37..e061f70cd 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr index 4184e8f67..5b248e07d 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,5 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 07887a4ce..b22552f23 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:52:57 -gem5 executing on e108600-lin, pid 17480 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:10:17 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56685 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 58675371500 because target called exit() +Exiting @ tick 58521086000 because exiting with last active thread context diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 57821b2e6..7a51f9c37 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,1262 +1,1262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058521 # Number of seconds simulated -sim_ticks 58521086000 # Number of ticks simulated -final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243648 # Simulator instruction rate (inst/s) -host_op_rate 244862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 157397000 # Simulator tick rate (ticks/s) -host_mem_usage 492140 # Number of bytes of host memory used -host_seconds 371.81 # Real time elapsed on the host -sim_insts 90589799 # Number of instructions simulated -sim_ops 91041030 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory -system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory -system.physmem.bytes_written::total 4736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory -system.physmem.num_writes::total 74 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18546 # Number of read requests accepted -system.physmem.writeReqs 74 # Number of write requests accepted -system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue -system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 3297 # Per bank write bursts -system.physmem.perBankRdBursts::1 920 # Per bank write bursts -system.physmem.perBankRdBursts::2 949 # Per bank write bursts -system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1067 # Per bank write bursts -system.physmem.perBankRdBursts::5 1119 # Per bank write bursts -system.physmem.perBankRdBursts::6 1093 # Per bank write bursts -system.physmem.perBankRdBursts::7 1097 # Per bank write bursts -system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 961 # Per bank write bursts -system.physmem.perBankRdBursts::10 934 # Per bank write bursts -system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 902 # Per bank write bursts -system.physmem.perBankRdBursts::13 895 # Per bank write bursts -system.physmem.perBankRdBursts::14 1399 # Per bank write bursts -system.physmem.perBankRdBursts::15 903 # Per bank write bursts -system.physmem.perBankWrBursts::0 1 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 2 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 1 # Per bank write bursts -system.physmem.perBankWrBursts::5 14 # Per bank write bursts -system.physmem.perBankWrBursts::6 9 # Per bank write bursts -system.physmem.perBankWrBursts::7 3 # Per bank write bursts -system.physmem.perBankWrBursts::8 1 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 2 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 1 # Per bank write bursts -system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 5 # Per bank write bursts -system.physmem.perBankWrBursts::15 1 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58521077500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18546 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 74 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads -system.physmem.totQLat 837911216 # Total ticks spent queuing -system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.16 # Data bus utilization in percentage -system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing -system.physmem.readRowHits 15512 # Number of row buffer hits during reads -system.physmem.writeRowHits 18 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes -system.physmem.avgGap 3142915.01 # Average gap between requests -system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ) -system.physmem_0.averagePower 339.947098 # Core power per rank (mW) -system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states -system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states -system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states -system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ) -system.physmem_1.averagePower 254.906533 # Core power per rank (mW) -system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states -system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states -system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28121660 # Number of BP lookups -system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117042173 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued -system.cpu.iq.rate 0.865106 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12823 # number of nop insts executed -system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed -system.cpu.iew.exec_branches 20644390 # Number of branches executed -system.cpu.iew.exec_stores 4947526 # Number of stores executed -system.cpu.iew.exec_rate 0.854978 # Inst execution rate -system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59603520 # num instructions producing a value -system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value -system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90602408 # Number of instructions committed -system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27220755 # Number of memory references committed -system.cpu.commit.loads 22475911 # Number of loads committed -system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18732305 # Number of branches committed -system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. -system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218426787 # The number of ROB reads -system.cpu.rob.rob_writes 219173124 # The number of ROB writes -system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90589799 # Number of Instructions Simulated -system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads -system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108095256 # number of integer regfile reads -system.cpu.int_regfile_writes 58597145 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 127 # number of floating regfile writes -system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads -system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes -system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads -system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470632 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits -system.cpu.dcache.overall_hits::total 18235318 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses -system.cpu.dcache.overall_misses::total 9969606 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks -system.cpu.dcache.writebacks::total 5470632 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 449 # number of replacements -system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.833706 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64174375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64174375 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32085580 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32085580 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32085580 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32085580 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32085580 # number of overall hits -system.cpu.icache.overall_hits::total 32085580 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses -system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81624480 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81624480 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81624480 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81624480 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81624480 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32086734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32086734 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32086734 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32086734 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32086734 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70731.785095 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21770 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1853 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 449 # number of writebacks -system.cpu.icache.writebacks::total 449 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61609984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61609984 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14076270 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 99 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11218.637670 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5292117 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14656 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 361.088769 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.680659 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.684731 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 67 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180525307 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5460197 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 7956 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 7956 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225753 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225753 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 207 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5241769 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 207 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5467522 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5467729 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 207 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5467522 # number of overall hits -system.cpu.l2cache.overall_hits::total 5467729 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 3123 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3622 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4323 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3622 # number of overall misses -system.cpu.l2cache.overall_misses::total 4323 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 105500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 66196000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 683496000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 742803500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 683496000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 742803500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 5460197 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 7956 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 7956 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 226252 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 5244892 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5472052 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5472052 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks -system.cpu.l2cache.writebacks::total 74 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 316332 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3442 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 320474 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318326 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18205 # Transaction distribution -system.membus.trans_dist::WritebackDirty 74 # Transaction distribution -system.membus.trans_dist::CleanEvict 25 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 340 # Transaction distribution -system.membus.trans_dist::ReadExResp 340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18552 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18552 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18552 # Request fanout histogram -system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +sim_seconds 0.058521 +sim_ticks 58521086000 +final_tick 58521086000 +sim_freq 1000000000000 +host_inst_rate 103970 +host_op_rate 104488 +host_tick_rate 67164623 +host_mem_usage 503044 +host_seconds 871.31 +sim_insts 90589799 +sim_ops 91041030 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.physmem.bytes_read::cpu.inst 44736 +system.physmem.bytes_read::cpu.data 220224 +system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 +system.physmem.bytes_read::total 1186880 +system.physmem.bytes_inst_read::cpu.inst 44736 +system.physmem.bytes_inst_read::total 44736 +system.physmem.bytes_written::writebacks 4736 +system.physmem.bytes_written::total 4736 +system.physmem.num_reads::cpu.inst 699 +system.physmem.num_reads::cpu.data 3441 +system.physmem.num_reads::cpu.l2cache.prefetcher 14405 +system.physmem.num_reads::total 18545 +system.physmem.num_writes::writebacks 74 +system.physmem.num_writes::total 74 +system.physmem.bw_read::cpu.inst 764442 +system.physmem.bw_read::cpu.data 3763156 +system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 +system.physmem.bw_read::total 20281237 +system.physmem.bw_inst_read::cpu.inst 764442 +system.physmem.bw_inst_read::total 764442 +system.physmem.bw_write::writebacks 80928 +system.physmem.bw_write::total 80928 +system.physmem.bw_total::writebacks 80928 +system.physmem.bw_total::cpu.inst 764442 +system.physmem.bw_total::cpu.data 3763156 +system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 +system.physmem.bw_total::total 20362165 +system.physmem.readReqs 18546 +system.physmem.writeReqs 74 +system.physmem.readBursts 18546 +system.physmem.writeBursts 74 +system.physmem.bytesReadDRAM 1183360 +system.physmem.bytesReadWrQ 3584 +system.physmem.bytesWritten 3328 +system.physmem.bytesReadSys 1186944 +system.physmem.bytesWrittenSys 4736 +system.physmem.servicedByWrQ 56 +system.physmem.mergedWrBursts 4 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 3297 +system.physmem.perBankRdBursts::1 920 +system.physmem.perBankRdBursts::2 949 +system.physmem.perBankRdBursts::3 1031 +system.physmem.perBankRdBursts::4 1067 +system.physmem.perBankRdBursts::5 1119 +system.physmem.perBankRdBursts::6 1093 +system.physmem.perBankRdBursts::7 1097 +system.physmem.perBankRdBursts::8 1024 +system.physmem.perBankRdBursts::9 961 +system.physmem.perBankRdBursts::10 934 +system.physmem.perBankRdBursts::11 899 +system.physmem.perBankRdBursts::12 902 +system.physmem.perBankRdBursts::13 895 +system.physmem.perBankRdBursts::14 1399 +system.physmem.perBankRdBursts::15 903 +system.physmem.perBankWrBursts::0 1 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 2 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 1 +system.physmem.perBankWrBursts::5 14 +system.physmem.perBankWrBursts::6 9 +system.physmem.perBankWrBursts::7 3 +system.physmem.perBankWrBursts::8 1 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 2 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 1 +system.physmem.perBankWrBursts::13 12 +system.physmem.perBankWrBursts::14 5 +system.physmem.perBankWrBursts::15 1 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 58521077500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 18546 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 74 +system.physmem.rdQLenPdf::0 12593 +system.physmem.rdQLenPdf::1 3390 +system.physmem.rdQLenPdf::2 500 +system.physmem.rdQLenPdf::3 409 +system.physmem.rdQLenPdf::4 319 +system.physmem.rdQLenPdf::5 301 +system.physmem.rdQLenPdf::6 297 +system.physmem.rdQLenPdf::7 299 +system.physmem.rdQLenPdf::8 279 +system.physmem.rdQLenPdf::9 103 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 1 +system.physmem.wrQLenPdf::1 1 +system.physmem.wrQLenPdf::2 1 +system.physmem.wrQLenPdf::3 1 +system.physmem.wrQLenPdf::4 1 +system.physmem.wrQLenPdf::5 1 +system.physmem.wrQLenPdf::6 1 +system.physmem.wrQLenPdf::7 1 +system.physmem.wrQLenPdf::8 1 +system.physmem.wrQLenPdf::9 1 +system.physmem.wrQLenPdf::10 1 +system.physmem.wrQLenPdf::11 1 +system.physmem.wrQLenPdf::12 1 +system.physmem.wrQLenPdf::13 1 +system.physmem.wrQLenPdf::14 1 +system.physmem.wrQLenPdf::15 3 +system.physmem.wrQLenPdf::16 3 +system.physmem.wrQLenPdf::17 4 +system.physmem.wrQLenPdf::18 3 +system.physmem.wrQLenPdf::19 3 +system.physmem.wrQLenPdf::20 3 +system.physmem.wrQLenPdf::21 3 +system.physmem.wrQLenPdf::22 3 +system.physmem.wrQLenPdf::23 3 +system.physmem.wrQLenPdf::24 3 +system.physmem.wrQLenPdf::25 3 +system.physmem.wrQLenPdf::26 3 +system.physmem.wrQLenPdf::27 3 +system.physmem.wrQLenPdf::28 3 +system.physmem.wrQLenPdf::29 3 +system.physmem.wrQLenPdf::30 3 +system.physmem.wrQLenPdf::31 3 +system.physmem.wrQLenPdf::32 3 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 3004 +system.physmem.bytesPerActivate::mean 394.652463 +system.physmem.bytesPerActivate::gmean 214.589229 +system.physmem.bytesPerActivate::stdev 405.543781 +system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% +system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% +system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% +system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% +system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% +system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% +system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% +system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% +system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% +system.physmem.bytesPerActivate::total 3004 +system.physmem.rdPerTurnAround::samples 3 +system.physmem.rdPerTurnAround::mean 6161.333333 +system.physmem.rdPerTurnAround::gmean 2123.401593 +system.physmem.rdPerTurnAround::stdev 8586.829993 +system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% +system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% +system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% +system.physmem.rdPerTurnAround::total 3 +system.physmem.wrPerTurnAround::samples 3 +system.physmem.wrPerTurnAround::mean 17.333333 +system.physmem.wrPerTurnAround::gmean 17.306995 +system.physmem.wrPerTurnAround::stdev 1.154701 +system.physmem.wrPerTurnAround::16 1 33.33% 33.33% +system.physmem.wrPerTurnAround::18 2 66.67% 100.00% +system.physmem.wrPerTurnAround::total 3 +system.physmem.totQLat 837911216 +system.physmem.totMemAccLat 1184598716 +system.physmem.totBusLat 92450000 +system.physmem.avgQLat 45316.99 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 64066.99 +system.physmem.avgRdBW 20.22 +system.physmem.avgWrBW 0.06 +system.physmem.avgRdBWSys 20.28 +system.physmem.avgWrBWSys 0.08 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 0.16 +system.physmem.busUtilRead 0.16 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.04 +system.physmem.avgWrQLen 13.38 +system.physmem.readRowHits 15512 +system.physmem.writeRowHits 18 +system.physmem.readRowHitRate 83.89 +system.physmem.writeRowHitRate 25.71 +system.physmem.avgGap 3142915.01 +system.physmem.pageHitRate 83.67 +system.physmem_0.actEnergy 16243500 +system.physmem_0.preEnergy 8614650 +system.physmem_0.readEnergy 75484080 +system.physmem_0.writeEnergy 156600 +system.physmem_0.refreshEnergy 1895549760.000000 +system.physmem_0.actBackEnergy 464945010 +system.physmem_0.preBackEnergy 99199680 +system.physmem_0.actPowerDownEnergy 4173482430 +system.physmem_0.prePowerDownEnergy 3272736480 +system.physmem_0.selfRefreshEnergy 9883191315 +system.physmem_0.totalEnergy 19894073865 +system.physmem_0.averagePower 339.947098 +system.physmem_0.totalIdleTime 57233116090 +system.physmem_0.memoryStateTime::IDLE 194944250 +system.physmem_0.memoryStateTime::REF 806364000 +system.physmem_0.memoryStateTime::SREF 39558059500 +system.physmem_0.memoryStateTime::PRE_PDN 8522710566 +system.physmem_0.memoryStateTime::ACT 286661660 +system.physmem_0.memoryStateTime::ACT_PDN 9152346024 +system.physmem_1.actEnergy 5255040 +system.physmem_1.preEnergy 2785530 +system.physmem_1.readEnergy 56527380 +system.physmem_1.writeEnergy 114840 +system.physmem_1.refreshEnergy 247699920.000000 +system.physmem_1.actBackEnergy 125328180 +system.physmem_1.preBackEnergy 13397280 +system.physmem_1.actPowerDownEnergy 772336890 +system.physmem_1.prePowerDownEnergy 242624160 +system.physmem_1.selfRefreshEnergy 13451278005 +system.physmem_1.totalEnergy 14917407225 +system.physmem_1.averagePower 254.906533 +system.physmem_1.totalIdleTime 58211272096 +system.physmem_1.memoryStateTime::IDLE 21634250 +system.physmem_1.memoryStateTime::REF 105218000 +system.physmem_1.memoryStateTime::SREF 55885668250 +system.physmem_1.memoryStateTime::PRE_PDN 631842954 +system.physmem_1.memoryStateTime::ACT 182961654 +system.physmem_1.memoryStateTime::ACT_PDN 1693760892 +system.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.branchPred.lookups 28121660 +system.cpu.branchPred.condPredicted 23134709 +system.cpu.branchPred.condIncorrect 844714 +system.cpu.branchPred.BTBLookups 11731332 +system.cpu.branchPred.BTBHits 11630363 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 99.139322 +system.cpu.branchPred.usedRAS 80725 +system.cpu.branchPred.RASInCorrect 95 +system.cpu.branchPred.indirectLookups 28301 +system.cpu.branchPred.indirectHits 25845 +system.cpu.branchPred.indirectMisses 2456 +system.cpu.branchPredindirectMispredicted 243 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 442 +system.cpu.pwrStateResidencyTicks::ON 58521086000 +system.cpu.numCycles 117042173 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 755365 +system.cpu.fetch.Insts 134380549 +system.cpu.fetch.Branches 28121660 +system.cpu.fetch.predictedBranches 11736933 +system.cpu.fetch.Cycles 115370240 +system.cpu.fetch.SquashCycles 1692792 +system.cpu.fetch.MiscStallCycles 848 +system.cpu.fetch.IcacheWaitRetryStallCycles 1033 +system.cpu.fetch.CacheLines 32086744 +system.cpu.fetch.IcacheSquashes 572 +system.cpu.fetch.rateDist::samples 116973882 +system.cpu.fetch.rateDist::mean 1.154260 +system.cpu.fetch.rateDist::stdev 1.318237 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% +system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% +system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% +system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 3 +system.cpu.fetch.rateDist::total 116973882 +system.cpu.fetch.branchRate 0.240269 +system.cpu.fetch.rate 1.148138 +system.cpu.decode.IdleCycles 8865418 +system.cpu.decode.BlockedCycles 65026599 +system.cpu.decode.RunCycles 32710680 +system.cpu.decode.UnblockCycles 9589004 +system.cpu.decode.SquashCycles 782181 +system.cpu.decode.BranchResolved 9831266 +system.cpu.decode.BranchMispred 64876 +system.cpu.decode.DecodedInsts 113761457 +system.cpu.decode.SquashedInsts 2108425 +system.cpu.rename.SquashCycles 782181 +system.cpu.rename.IdleCycles 15316274 +system.cpu.rename.BlockCycles 50229704 +system.cpu.rename.serializeStallCycles 114341 +system.cpu.rename.RunCycles 35119945 +system.cpu.rename.UnblockCycles 15411437 +system.cpu.rename.RenamedInsts 110456918 +system.cpu.rename.SquashedInsts 1289549 +system.cpu.rename.ROBFullEvents 11149602 +system.cpu.rename.IQFullEvents 1576334 +system.cpu.rename.LQFullEvents 2138216 +system.cpu.rename.SQFullEvents 510190 +system.cpu.rename.RenamedOperands 129202611 +system.cpu.rename.RenameLookups 481340709 +system.cpu.rename.int_rename_lookups 118978784 +system.cpu.rename.fp_rename_lookups 633 +system.cpu.rename.CommittedMaps 107312919 +system.cpu.rename.UndoneMaps 21889692 +system.cpu.rename.serializingInsts 4408 +system.cpu.rename.tempSerializingInsts 4400 +system.cpu.rename.skidInsts 21529051 +system.cpu.memDep0.insertedLoads 26813393 +system.cpu.memDep0.insertedStores 5308956 +system.cpu.memDep0.conflictingLoads 540635 +system.cpu.memDep0.conflictingStores 272789 +system.cpu.iq.iqInstsAdded 109383305 +system.cpu.iq.iqNonSpecInstsAdded 8282 +system.cpu.iq.iqInstsIssued 101253910 +system.cpu.iq.iqSquashedInstsIssued 993650 +system.cpu.iq.iqSquashedInstsExamined 18350556 +system.cpu.iq.iqSquashedOperandsExamined 40868291 +system.cpu.iq.iqSquashedNonSpecRemoved 64 +system.cpu.iq.issued_per_cycle::samples 116973882 +system.cpu.iq.issued_per_cycle::mean 0.865611 +system.cpu.iq.issued_per_cycle::stdev 0.989909 +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% +system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% +system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% +system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% +system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% +system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% +system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::min_value 0 +system.cpu.iq.issued_per_cycle::max_value 5 +system.cpu.iq.issued_per_cycle::total 116973882 +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% +system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% +system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% +system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% +system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% +system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% +system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% +system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% +system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% +system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% +system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% +system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% +system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::total 101253910 +system.cpu.iq.rate 0.865106 +system.cpu.iq.fu_busy_cnt 20139291 +system.cpu.iq.fu_busy_rate 0.198899 +system.cpu.iq.int_inst_queue_reads 340613998 +system.cpu.iq.int_inst_queue_writes 127742532 +system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 +system.cpu.iq.fp_inst_queue_reads 645 +system.cpu.iq.fp_inst_queue_writes 896 +system.cpu.iq.fp_inst_queue_wakeup_accesses 147 +system.cpu.iq.int_alu_accesses 121392865 +system.cpu.iq.fp_alu_accesses 336 +system.cpu.iew.lsq.thread0.forwLoads 289487 +system.cpu.iew.lsq.thread0.invAddrLoads 0 +system.cpu.iew.lsq.thread0.squashedLoads 4337482 +system.cpu.iew.lsq.thread0.ignoredResponses 2085 +system.cpu.iew.lsq.thread0.memOrderViolation 1323 +system.cpu.iew.lsq.thread0.squashedStores 564112 +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 +system.cpu.iew.lsq.thread0.blockedLoads 0 +system.cpu.iew.lsq.thread0.rescheduledLoads 7586 +system.cpu.iew.lsq.thread0.cacheBlocked 131115 +system.cpu.iew.iewIdleCycles 0 +system.cpu.iew.iewSquashCycles 782181 +system.cpu.iew.iewBlockCycles 8303656 +system.cpu.iew.iewUnblockCycles 706645 +system.cpu.iew.iewDispatchedInsts 109404410 +system.cpu.iew.iewDispSquashedInsts 0 +system.cpu.iew.iewDispLoadInsts 26813393 +system.cpu.iew.iewDispStoreInsts 5308956 +system.cpu.iew.iewDispNonSpecInsts 4394 +system.cpu.iew.iewIQFullEvents 183005 +system.cpu.iew.iewLSQFullEvents 362995 +system.cpu.iew.memOrderViolationEvents 1323 +system.cpu.iew.predictedTakenIncorrect 354101 +system.cpu.iew.predictedNotTakenIncorrect 451870 +system.cpu.iew.branchMispredicts 805971 +system.cpu.iew.iewExecutedInsts 100068536 +system.cpu.iew.iewExecLoadInsts 23799476 +system.cpu.iew.iewExecSquashedInsts 1185374 +system.cpu.iew.exec_swp 0 +system.cpu.iew.exec_nop 12823 +system.cpu.iew.exec_refs 28747002 +system.cpu.iew.exec_branches 20644390 +system.cpu.iew.exec_stores 4947526 +system.cpu.iew.exec_rate 0.854978 +system.cpu.iew.wb_sent 99653444 +system.cpu.iew.wb_count 99568306 +system.cpu.iew.wb_producers 59603520 +system.cpu.iew.wb_consumers 95472454 +system.cpu.iew.wb_rate 0.850705 +system.cpu.iew.wb_fanout 0.624301 +system.cpu.commit.commitSquashedInsts 17204380 +system.cpu.commit.commitNonSpecStalls 8218 +system.cpu.commit.branchMispredicts 780499 +system.cpu.commit.committed_per_cycle::samples 114317449 +system.cpu.commit.committed_per_cycle::mean 0.796498 +system.cpu.commit.committed_per_cycle::stdev 1.736161 +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% +system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% +system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% +system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% +system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% +system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% +system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% +system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% +system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% +system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% +system.cpu.commit.committed_per_cycle::min_value 0 +system.cpu.commit.committed_per_cycle::max_value 8 +system.cpu.commit.committed_per_cycle::total 114317449 +system.cpu.commit.committedInsts 90602408 +system.cpu.commit.committedOps 91053639 +system.cpu.commit.swp_count 0 +system.cpu.commit.refs 27220755 +system.cpu.commit.loads 22475911 +system.cpu.commit.membars 3888 +system.cpu.commit.branches 18732305 +system.cpu.commit.fp_insts 48 +system.cpu.commit.int_insts 72326352 +system.cpu.commit.function_calls 56148 +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% +system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% +system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% +system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% +system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% +system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% +system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% +system.cpu.commit.op_class_0::total 91053639 +system.cpu.commit.bw_lim_events 4142947 +system.cpu.rob.rob_reads 218426787 +system.cpu.rob.rob_writes 219173123 +system.cpu.timesIdled 593 +system.cpu.idleCycles 68291 +system.cpu.committedInsts 90589799 +system.cpu.committedOps 91041030 +system.cpu.cpi 1.292002 +system.cpu.cpi_total 1.292002 +system.cpu.ipc 0.773993 +system.cpu.ipc_total 0.773993 +system.cpu.int_regfile_reads 108095256 +system.cpu.int_regfile_writes 58597145 +system.cpu.fp_regfile_reads 58 +system.cpu.fp_regfile_writes 127 +system.cpu.cc_regfile_reads 368871207 +system.cpu.cc_regfile_writes 58517884 +system.cpu.misc_regfile_reads 28439348 +system.cpu.misc_regfile_writes 7784 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.dcache.tags.replacements 5470632 +system.cpu.dcache.tags.tagsinuse 511.768178 +system.cpu.dcache.tags.total_refs 18243100 +system.cpu.dcache.tags.sampled_refs 5471144 +system.cpu.dcache.tags.avg_refs 3.334421 +system.cpu.dcache.tags.warmup_cycle 38187500 +system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 +system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 +system.cpu.dcache.tags.occ_percent::total 0.999547 +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 61896540 +system.cpu.dcache.tags.data_accesses 61896540 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.dcache.ReadReq_hits::cpu.data 13880582 +system.cpu.dcache.ReadReq_hits::total 13880582 +system.cpu.dcache.WriteReq_hits::cpu.data 4354214 +system.cpu.dcache.WriteReq_hits::total 4354214 +system.cpu.dcache.SoftPFReq_hits::cpu.data 522 +system.cpu.dcache.SoftPFReq_hits::total 522 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 +system.cpu.dcache.LoadLockedReq_hits::total 3873 +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 +system.cpu.dcache.StoreCondReq_hits::total 3887 +system.cpu.dcache.demand_hits::cpu.data 18234796 +system.cpu.dcache.demand_hits::total 18234796 +system.cpu.dcache.overall_hits::cpu.data 18235318 +system.cpu.dcache.overall_hits::total 18235318 +system.cpu.dcache.ReadReq_misses::cpu.data 9588832 +system.cpu.dcache.ReadReq_misses::total 9588832 +system.cpu.dcache.WriteReq_misses::cpu.data 380767 +system.cpu.dcache.WriteReq_misses::total 380767 +system.cpu.dcache.SoftPFReq_misses::cpu.data 7 +system.cpu.dcache.SoftPFReq_misses::total 7 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 +system.cpu.dcache.LoadLockedReq_misses::total 14 +system.cpu.dcache.demand_misses::cpu.data 9969599 +system.cpu.dcache.demand_misses::total 9969599 +system.cpu.dcache.overall_misses::cpu.data 9969606 +system.cpu.dcache.overall_misses::total 9969606 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 +system.cpu.dcache.ReadReq_miss_latency::total 89393317500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 +system.cpu.dcache.WriteReq_miss_latency::total 4103772083 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 +system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 +system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 +system.cpu.dcache.demand_miss_latency::total 93497089583 +system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 +system.cpu.dcache.overall_miss_latency::total 93497089583 +system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 +system.cpu.dcache.ReadReq_accesses::total 23469414 +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 +system.cpu.dcache.WriteReq_accesses::total 4734981 +system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 +system.cpu.dcache.SoftPFReq_accesses::total 529 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 +system.cpu.dcache.LoadLockedReq_accesses::total 3887 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 +system.cpu.dcache.StoreCondReq_accesses::total 3887 +system.cpu.dcache.demand_accesses::cpu.data 28204395 +system.cpu.dcache.demand_accesses::total 28204395 +system.cpu.dcache.overall_accesses::cpu.data 28204924 +system.cpu.dcache.overall_accesses::total 28204924 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 +system.cpu.dcache.ReadReq_miss_rate::total 0.408567 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 +system.cpu.dcache.WriteReq_miss_rate::total 0.080416 +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 +system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 +system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 +system.cpu.dcache.demand_miss_rate::total 0.353477 +system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 +system.cpu.dcache.overall_miss_rate::total 0.353470 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 +system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 +system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 +system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 +system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 +system.cpu.dcache.blocked_cycles::no_mshrs 331670 +system.cpu.dcache.blocked_cycles::no_targets 131340 +system.cpu.dcache.blocked::no_mshrs 121646 +system.cpu.dcache.blocked::no_targets 12838 +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 +system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 +system.cpu.dcache.writebacks::writebacks 5470632 +system.cpu.dcache.writebacks::total 5470632 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 +system.cpu.dcache.ReadReq_mshr_hits::total 4340269 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 +system.cpu.dcache.WriteReq_mshr_hits::total 158185 +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 +system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 +system.cpu.dcache.demand_mshr_hits::total 4498454 +system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 +system.cpu.dcache.overall_mshr_hits::total 4498454 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 +system.cpu.dcache.ReadReq_mshr_misses::total 5248563 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 +system.cpu.dcache.WriteReq_mshr_misses::total 222582 +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 +system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 +system.cpu.dcache.demand_mshr_misses::total 5471145 +system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 +system.cpu.dcache.overall_mshr_misses::total 5471149 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 +system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 +system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 +system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 +system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.icache.tags.replacements 449 +system.cpu.icache.tags.tagsinuse 426.857560 +system.cpu.icache.tags.total_refs 32085580 +system.cpu.icache.tags.sampled_refs 907 +system.cpu.icache.tags.avg_refs 35375.501654 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 +system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 +system.cpu.icache.tags.occ_percent::total 0.833706 +system.cpu.icache.tags.occ_task_id_blocks::1024 458 +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 +system.cpu.icache.tags.age_task_id_blocks_1024::2 50 +system.cpu.icache.tags.age_task_id_blocks_1024::3 22 +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 +system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 +system.cpu.icache.tags.tag_accesses 64174375 +system.cpu.icache.tags.data_accesses 64174375 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.icache.ReadReq_hits::cpu.inst 32085580 +system.cpu.icache.ReadReq_hits::total 32085580 +system.cpu.icache.demand_hits::cpu.inst 32085580 +system.cpu.icache.demand_hits::total 32085580 +system.cpu.icache.overall_hits::cpu.inst 32085580 +system.cpu.icache.overall_hits::total 32085580 +system.cpu.icache.ReadReq_misses::cpu.inst 1154 +system.cpu.icache.ReadReq_misses::total 1154 +system.cpu.icache.demand_misses::cpu.inst 1154 +system.cpu.icache.demand_misses::total 1154 +system.cpu.icache.overall_misses::cpu.inst 1154 +system.cpu.icache.overall_misses::total 1154 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 +system.cpu.icache.ReadReq_miss_latency::total 81624480 +system.cpu.icache.demand_miss_latency::cpu.inst 81624480 +system.cpu.icache.demand_miss_latency::total 81624480 +system.cpu.icache.overall_miss_latency::cpu.inst 81624480 +system.cpu.icache.overall_miss_latency::total 81624480 +system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 +system.cpu.icache.ReadReq_accesses::total 32086734 +system.cpu.icache.demand_accesses::cpu.inst 32086734 +system.cpu.icache.demand_accesses::total 32086734 +system.cpu.icache.overall_accesses::cpu.inst 32086734 +system.cpu.icache.overall_accesses::total 32086734 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 +system.cpu.icache.ReadReq_miss_rate::total 0.000036 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 +system.cpu.icache.demand_miss_rate::total 0.000036 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 +system.cpu.icache.overall_miss_rate::total 0.000036 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 +system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 +system.cpu.icache.demand_avg_miss_latency::total 70731.785095 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 +system.cpu.icache.overall_avg_miss_latency::total 70731.785095 +system.cpu.icache.blocked_cycles::no_mshrs 21770 +system.cpu.icache.blocked_cycles::no_targets 1853 +system.cpu.icache.blocked::no_mshrs 229 +system.cpu.icache.blocked::no_targets 7 +system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 +system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 +system.cpu.icache.writebacks::writebacks 449 +system.cpu.icache.writebacks::total 449 +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 +system.cpu.icache.ReadReq_mshr_hits::total 246 +system.cpu.icache.demand_mshr_hits::cpu.inst 246 +system.cpu.icache.demand_mshr_hits::total 246 +system.cpu.icache.overall_mshr_hits::cpu.inst 246 +system.cpu.icache.overall_mshr_hits::total 246 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 +system.cpu.icache.ReadReq_mshr_misses::total 908 +system.cpu.icache.demand_mshr_misses::cpu.inst 908 +system.cpu.icache.demand_mshr_misses::total 908 +system.cpu.icache.overall_mshr_misses::cpu.inst 908 +system.cpu.icache.overall_mshr_misses::total 908 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984 +system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984 +system.cpu.icache.demand_mshr_miss_latency::total 61609984 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 +system.cpu.icache.overall_mshr_miss_latency::total 61609984 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 +system.cpu.icache.demand_mshr_miss_rate::total 0.000028 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 +system.cpu.icache.overall_mshr_miss_rate::total 0.000028 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 +system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 +system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 +system.cpu.l2cache.prefetcher.pfIdentified 5295978 +system.cpu.l2cache.prefetcher.pfBufferHit 268023 +system.cpu.l2cache.prefetcher.pfInCache 0 +system.cpu.l2cache.prefetcher.pfRemovedFull 0 +system.cpu.l2cache.prefetcher.pfSpanPage 14076270 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.l2cache.tags.replacements 99 +system.cpu.l2cache.tags.tagsinuse 11218.637670 +system.cpu.l2cache.tags.total_refs 5292117 +system.cpu.l2cache.tags.sampled_refs 14656 +system.cpu.l2cache.tags.avg_refs 361.088769 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658 +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012 +system.cpu.l2cache.tags.occ_percent::writebacks 0.680659 +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072 +system.cpu.l2cache.tags.occ_percent::total 0.684731 +system.cpu.l2cache.tags.occ_task_id_blocks::1022 67 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490 +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 +system.cpu.l2cache.tags.tag_accesses 180525307 +system.cpu.l2cache.tags.data_accesses 180525307 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197 +system.cpu.l2cache.WritebackDirty_hits::total 5460197 +system.cpu.l2cache.WritebackClean_hits::writebacks 7956 +system.cpu.l2cache.WritebackClean_hits::total 7956 +system.cpu.l2cache.ReadExReq_hits::cpu.data 225753 +system.cpu.l2cache.ReadExReq_hits::total 225753 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207 +system.cpu.l2cache.ReadCleanReq_hits::total 207 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769 +system.cpu.l2cache.ReadSharedReq_hits::total 5241769 +system.cpu.l2cache.demand_hits::cpu.inst 207 +system.cpu.l2cache.demand_hits::cpu.data 5467522 +system.cpu.l2cache.demand_hits::total 5467729 +system.cpu.l2cache.overall_hits::cpu.inst 207 +system.cpu.l2cache.overall_hits::cpu.data 5467522 +system.cpu.l2cache.overall_hits::total 5467729 +system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 +system.cpu.l2cache.UpgradeReq_misses::total 5 +system.cpu.l2cache.ReadExReq_misses::cpu.data 499 +system.cpu.l2cache.ReadExReq_misses::total 499 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 +system.cpu.l2cache.ReadCleanReq_misses::total 701 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123 +system.cpu.l2cache.ReadSharedReq_misses::total 3123 +system.cpu.l2cache.demand_misses::cpu.inst 701 +system.cpu.l2cache.demand_misses::cpu.data 3622 +system.cpu.l2cache.demand_misses::total 4323 +system.cpu.l2cache.overall_misses::cpu.inst 701 +system.cpu.l2cache.overall_misses::cpu.data 3622 +system.cpu.l2cache.overall_misses::total 4323 +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500 +system.cpu.l2cache.UpgradeReq_miss_latency::total 105500 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000 +system.cpu.l2cache.ReadExReq_miss_latency::total 66196000 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000 +system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500 +system.cpu.l2cache.demand_miss_latency::cpu.data 683496000 +system.cpu.l2cache.demand_miss_latency::total 742803500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500 +system.cpu.l2cache.overall_miss_latency::cpu.data 683496000 +system.cpu.l2cache.overall_miss_latency::total 742803500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197 +system.cpu.l2cache.WritebackDirty_accesses::total 5460197 +system.cpu.l2cache.WritebackClean_accesses::writebacks 7956 +system.cpu.l2cache.WritebackClean_accesses::total 7956 +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 +system.cpu.l2cache.UpgradeReq_accesses::total 5 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252 +system.cpu.l2cache.ReadExReq_accesses::total 226252 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908 +system.cpu.l2cache.ReadCleanReq_accesses::total 908 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892 +system.cpu.l2cache.ReadSharedReq_accesses::total 5244892 +system.cpu.l2cache.demand_accesses::cpu.inst 908 +system.cpu.l2cache.demand_accesses::cpu.data 5471144 +system.cpu.l2cache.demand_accesses::total 5472052 +system.cpu.l2cache.overall_accesses::cpu.inst 908 +system.cpu.l2cache.overall_accesses::cpu.data 5471144 +system.cpu.l2cache.overall_accesses::total 5472052 +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662 +system.cpu.l2cache.demand_miss_rate::total 0.000790 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 +system.cpu.l2cache.overall_miss_rate::total 0.000790 +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100 +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828 +system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828 +system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.unused_prefetches 1 +system.cpu.l2cache.writebacks::writebacks 74 +system.cpu.l2cache.writebacks::total 74 +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 +system.cpu.l2cache.ReadExReq_mshr_hits::total 158 +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 +system.cpu.l2cache.demand_mshr_hits::cpu.data 180 +system.cpu.l2cache.demand_mshr_hits::total 181 +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 +system.cpu.l2cache.overall_mshr_hits::cpu.data 180 +system.cpu.l2cache.overall_mshr_hits::total 181 +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332 +system.cpu.l2cache.HardPFReq_mshr_misses::total 316332 +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 +system.cpu.l2cache.ReadExReq_mshr_misses::total 341 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 +system.cpu.l2cache.demand_mshr_misses::cpu.data 3442 +system.cpu.l2cache.demand_mshr_misses::total 4142 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 +system.cpu.l2cache.overall_mshr_misses::cpu.data 3442 +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332 +system.cpu.l2cache.overall_mshr_misses::total 320474 +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507 +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500 +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500 +system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 +system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 +system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 +system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.toL2Bus.trans_dist::ReadResp 5245799 +system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 +system.cpu.toL2Bus.trans_dist::WritebackClean 10884 +system.cpu.toL2Bus.trans_dist::CleanEvict 25 +system.cpu.toL2Bus.trans_dist::HardPFReq 318221 +system.cpu.toL2Bus.trans_dist::HardPFResp 6 +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 +system.cpu.toL2Bus.trans_dist::ReadExReq 226252 +system.cpu.toL2Bus.trans_dist::ReadExResp 226252 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 +system.cpu.toL2Bus.pkt_count::total 16415200 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 +system.cpu.toL2Bus.pkt_size::total 700360832 +system.cpu.toL2Bus.snoops 318326 +system.cpu.toL2Bus.snoopTraffic 5120 +system.cpu.toL2Bus.snoop_fanout::samples 5790377 +system.cpu.toL2Bus.snoop_fanout::mean 0.052651 +system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% +system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 5790377 +system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 +system.cpu.toL2Bus.reqLayer0.utilization 18.7 +system.cpu.toL2Bus.snoopLayer0.occupancy 9032 +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 1362995 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 8206721993 +system.cpu.toL2Bus.respLayer1.utilization 14.0 +system.membus.snoop_filter.tot_requests 18651 +system.membus.snoop_filter.hit_single_requests 3037 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.membus.trans_dist::ReadResp 18205 +system.membus.trans_dist::WritebackDirty 74 +system.membus.trans_dist::CleanEvict 25 +system.membus.trans_dist::UpgradeReq 6 +system.membus.trans_dist::ReadExReq 340 +system.membus.trans_dist::ReadExResp 340 +system.membus.trans_dist::ReadSharedReq 18206 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 +system.membus.pkt_count::total 37196 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 +system.membus.pkt_size::total 1191616 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 18552 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 18552 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 18552 +system.membus.reqLayer0.occupancy 29380556 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 97369032 +system.membus.respLayer1.utilization 0.2 ---------- End Simulation Statistics ---------- |