stats: Update to match classic memory changes

1 files changed, 174 insertions, 170 deletions

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index b912f8d81..b27dfcb1b 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.361598                       # Number of seconds simulated
-sim_ticks                                361597758500                       # Number of ticks simulated
-final_tick                               361597758500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.361613                       # Number of seconds simulated
+sim_ticks                                361613361500                       # Number of ticks simulated
+final_tick                               361613361500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1165746                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1165794                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1728825291                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 381188                       # Number of bytes of host memory used
-host_seconds                                   209.16                       # Real time elapsed on the host
+host_inst_rate                                1370596                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1370653                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2032709522                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 385816                       # Number of bytes of host memory used
+host_seconds                                   177.90                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             56256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            942336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               998592                       # Number of bytes read from this memory
@@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total           56256                       # Nu
 system.physmem.num_reads::cpu.inst                879                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14724                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15603                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               155576                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2606034                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2761610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          155576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             155576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              155576                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2606034                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2761610                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.physmem.bw_read::cpu.inst               155569                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2605921                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2761491                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          155569                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             155569                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              155569                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2605921                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2761491                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    361597758500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        723195517                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    361613361500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        723226723                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   243825150                       # Number of instructions committed
@@ -53,7 +53,7 @@ system.cpu.num_mem_refs                     105711441                       # nu
 system.cpu.num_load_insts                    82803521                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               723195516.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               723226722.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29302884                       # Number of branches fetched
@@ -92,25 +92,25 @@ system.cpu.op_class::MemWrite                22907920      9.37%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  244431613                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            935475                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3562.412338                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3562.404243                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           104186699                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            939571                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            110.887521                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle      134409733500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3562.412338                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.869730                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.869730                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle      134415942500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3562.404243                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.869728                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.869728                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1         1416                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         2526                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           46                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           47                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         211192111                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        211192111                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     81327576                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        81327576                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits
@@ -131,16 +131,16 @@ system.cpu.dcache.demand_misses::cpu.data       939567                       # n
 system.cpu.dcache.demand_misses::total         939567                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       939567                       # number of overall misses
 system.cpu.dcache.overall_misses::total        939567                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11614835000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11614835000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1320964000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1320964000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data       101000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total       101000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  12935799000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  12935799000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  12935799000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  12935799000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11614992000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11614992000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1335530000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1335530000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       102000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       102000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  12950522000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  12950522000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  12950522000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  12950522000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     82220433                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     82220433                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     22901951                       # number of WriteReq accesses(hits+misses)
@@ -161,16 +161,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_miss_rate::total     0.008938                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.008938                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.008938                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        25250                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total        25250                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13767.830288                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13767.830288                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        25500                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total        25500                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13783.500272                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13783.500272                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -189,16 +189,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       939567
 system.cpu.dcache.demand_mshr_misses::total       939567                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       939567                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       939567                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10721978000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10721978000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1274254000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1274254000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        97000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total        97000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11996232000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11996232000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11996232000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11996232000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10722135000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10722135000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1288820000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1288820000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        98000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        98000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12010955000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12010955000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12010955000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12010955000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002040                       # mshr miss rate for WriteReq accesses
@@ -209,26 +209,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_mshr_miss_rate::total     0.008938                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.008938                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        24250                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        24250                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        24500                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        24500                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                25                       # number of replacements
-system.cpu.icache.tags.tagsinuse           725.404879                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           725.403723                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           244420617                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               882                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          277120.880952                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   725.404879                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.354202                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.354202                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   725.403723                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.354201                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.354201                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          857                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
@@ -237,7 +237,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4          781
 system.cpu.icache.tags.occ_task_id_percent::1024     0.418457                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         488843880                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        488843880                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst    244420617                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       244420617                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     244420617                       # number of demand (read+write) hits
@@ -250,12 +250,12 @@ system.cpu.icache.demand_misses::cpu.inst          882                       # n
 system.cpu.icache.demand_misses::total            882                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          882                       # number of overall misses
 system.cpu.icache.overall_misses::total           882                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     54543500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     54543500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     54543500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     54543500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     54543500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     54543500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     55422500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     55422500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     55422500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     55422500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     55422500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     55422500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    244421499                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    244421499                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    244421499                       # number of demand (read+write) accesses
@@ -268,12 +268,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000004
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61840.702948                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61840.702948                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 62837.301587                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62837.301587                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -288,48 +288,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          882
 system.cpu.icache.demand_mshr_misses::total          882                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          882                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          882                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     53661500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     53661500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     53661500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     53661500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     53661500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     53661500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     54540500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     54540500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     54540500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     54540500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     54540500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     54540500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         9729.320449                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1813523                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15586                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           116.355896                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10855.563013                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1860349                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            15603                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           119.230212                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8846.376929                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   738.627938                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   144.315582                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.269970                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   738.626846                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.022541                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.004404                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.296915                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15586                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.308744                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.331285                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15603                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1385                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13986                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.475647                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15069916                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15069916                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           64                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15465                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.476166                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15023219                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15023219                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       935266                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       935266                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks           25                       # number of WritebackClean hits
@@ -358,18 +356,18 @@ system.cpu.l2cache.demand_misses::total         15603                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          879                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14724                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15603                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    866736500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    866736500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     52304000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     52304000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      9341500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      9341500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     52304000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    876078000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    928382000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     52304000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    876078000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    928382000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    881303500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    881303500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     53183000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     53183000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      9498500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      9498500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     53183000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    890802000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    943985000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     53183000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    890802000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    943985000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       935266                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       935266                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks           25                       # number of WritebackClean accesses(hits+misses)
@@ -398,18 +396,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.016591                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996599                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015671                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016591                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        59500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        59500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        59500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        59500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        59500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        59500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        60500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        60500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        60500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        60500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        60500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        60500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -428,18 +426,18 @@ system.cpu.l2cache.demand_mshr_misses::total        15603
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          879                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14724                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    721066500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    721066500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43514000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43514000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7771500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7771500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43514000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    728838000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    772352000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43514000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    728838000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    772352000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    735633500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    735633500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     44393000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     44393000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7928500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7928500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     44393000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    743562000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    787955000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     44393000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    743562000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    787955000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311834                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311834                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for ReadCleanReq accesses
@@ -452,25 +450,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.016591
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015671                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016591                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        49500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        49500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        50500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        50500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        50500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        50500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      1875953                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       935500                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        893739                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       935266                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean           25                       # Transaction distribution
@@ -504,7 +502,13 @@ system.cpu.toL2Bus.respLayer0.occupancy       1323000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1409356500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500                       # Cumulative time (in ticks) in various power states
+system.membus.snoop_filter.tot_requests         15603                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               1036                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14567                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14567                       # Transaction distribution