stats: Update stats for syscall emulation Linux kernel changes.

3 files changed, 63 insertions, 63 deletions

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 2ba8ced6e..22dd9c24e 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index f34d81d26..869cdf524 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 12:31:43
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:15:25
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 362481577000 because target called exit()
+Exiting @ tick 362481563000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 5f77178bc..44702e46f 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.362482                       # Number of seconds simulated
-sim_ticks                                362481577000                       # Number of ticks simulated
-final_tick                               362481577000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                362481563000                       # Number of ticks simulated
+final_tick                               362481563000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1217197                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1217247                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1809539933                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 354248                       # Number of bytes of host memory used
-host_seconds                                   200.32                       # Real time elapsed on the host
-sim_insts                                   243825163                       # Number of instructions simulated
-sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1415125                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1415183                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2103788292                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 363728                       # Number of bytes of host memory used
+host_seconds                                   172.30                       # Real time elapsed on the host
+sim_insts                                   243825150                       # Number of instructions simulated
+sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             56256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            942336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               998592                       # Number of bytes read from this memory
@@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst              155197                       # To
 system.physmem.bw_total::cpu.data             2599680                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                2754877                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        724963154                       # number of cpu cycles simulated
+system.cpu.numCycles                        724963126                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   243825163                       # Number of instructions committed
-system.cpu.committedOps                     243835278                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.committedInsts                   243825150                       # Number of instructions committed
+system.cpu.committedOps                     243835265                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             194726494                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
 system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_conditional_control_insts     18619959                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    194726494                       # number of integer instructions
 system.cpu.num_fp_insts                         11630                       # number of float instructions
-system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          215451566                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           456818988                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451553                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     105711442                       # number of memory refs
-system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_mem_refs                     105711441                       # number of memory refs
+system.cpu.num_load_insts                    82803521                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  724963154                       # Number of busy cycles
+system.cpu.num_busy_cycles                  724963126                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     25                       # number of replacements
-system.cpu.icache.tagsinuse                725.564686                       # Cycle average of tags in use
-system.cpu.icache.total_refs                244420630                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                725.564713                       # Cycle average of tags in use
+system.cpu.icache.total_refs                244420617                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               277120.895692                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               277120.880952                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     725.564686                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     725.564713                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.354280                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.354280                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    244420630                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       244420630                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     244420630                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        244420630                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    244420630                       # number of overall hits
-system.cpu.icache.overall_hits::total       244420630                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    244420617                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       244420617                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     244420617                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        244420617                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    244420617                       # number of overall hits
+system.cpu.icache.overall_hits::total       244420617                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          882                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           882                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          882                       # number of demand (read+write) misses
@@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     49333000
 system.cpu.icache.demand_miss_latency::total     49333000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     49333000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     49333000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    244421512                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244421512                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244421512                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244421512                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244421512                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244421512                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    244421499                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244421499                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244421499                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244421499                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244421499                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244421499                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
@@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 935475                       # number of replacements
-system.cpu.dcache.tagsinuse               3563.804804                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               3563.804941                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                104186699                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           134384281000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3563.804804                       # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs                 110.887521                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           134384267000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3563.804941                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.870070                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.870070                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     81327577                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        81327577                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     81327576                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        81327576                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       22855241                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data         3882                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total            3882                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data     104182818                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        104182818                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    104182818                       # number of overall hits
-system.cpu.dcache.overall_hits::total       104182818                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     104182817                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        104182817                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    104182817                       # number of overall hits
+system.cpu.dcache.overall_hits::total       104182817                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       892857                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        892857                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data        46710                       # number of WriteReq misses
@@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data  13778134000
 system.cpu.dcache.demand_miss_latency::total  13778134000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data  13778134000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  13778134000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     82220434                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     82220434                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     82220433                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     82220433                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     22901951                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     22901951                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data         3886                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total         3886                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    105122385                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    105122385                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    105122385                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    105122385                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    105122384                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    105122384                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    105122384                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    105122384                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010859                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.010859                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002040                       # miss rate for WriteReq accesses
@@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              9744.633089                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              9744.633464                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 1813121                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 15586                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                116.330104                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  8861.504688                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    738.799807                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    144.328594                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks  8861.505031                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    738.799835                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    144.328599                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.270432                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.022546                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.004405                       # Average percentage of cache occupancy