stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

1 files changed, 5 insertions, 14 deletions

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 4cc0ff469..c28c5f296 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.361598                       # Nu
 sim_ticks                                361597758500                       # Number of ticks simulated
 final_tick                               361597758500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1193747                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1193796                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1770350920                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 429888                       # Number of bytes of host memory used
-host_seconds                                   204.25                       # Real time elapsed on the host
+host_inst_rate                                1238958                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1239009                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1837400352                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 383872                       # Number of bytes of host memory used
+host_seconds                                   196.80                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -172,8 +172,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       935266                       # number of writebacks
 system.cpu.dcache.writebacks::total            935266                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       892857                       # number of ReadReq MSHR misses
@@ -216,7 +214,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                25                       # number of replacements
 system.cpu.icache.tags.tagsinuse           725.404879                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           244420617                       # Total number of references to valid blocks.
@@ -276,8 +273,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           25                       # number of writebacks
 system.cpu.icache.writebacks::total                25                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          882                       # number of ReadReq MSHR misses
@@ -304,7 +299,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         9729.320449                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1813523                       # Total number of references to valid blocks.
@@ -413,8 +407,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14567                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14567                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          879                       # number of ReadCleanReq MSHR misses
@@ -463,7 +455,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1875953                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       935500                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.