diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
| commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
| tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff /tests/long/se/10.mcf/ref/sparc/linux | |
| parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
| download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz | |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Diffstat (limited to 'tests/long/se/10.mcf/ref/sparc/linux')
| -rw-r--r-- | tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b27dfcb1b..ff7ca3031 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361613 # Nu sim_ticks 361613361500 # Number of ticks simulated final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1370596 # Simulator instruction rate (inst/s) -host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2032709522 # Simulator tick rate (ticks/s) -host_mem_usage 385816 # Number of bytes of host memory used -host_seconds 177.90 # Real time elapsed on the host +host_inst_rate 1844871 # Simulator instruction rate (inst/s) +host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2736100211 # Simulator tick rate (ticks/s) +host_mem_usage 385448 # Number of bytes of host memory used +host_seconds 132.16 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,7 +65,9 @@ system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Cl system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction @@ -87,8 +89,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction |