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authorAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:43 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:43 -0600
commit4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch)
treec6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/10.mcf/ref/sparc/linux
parent542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff)
downloadgem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/10.mcf/ref/sparc/linux')
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini17
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt15
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini50
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt412
6 files changed, 303 insertions, 203 deletions
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 77055bd16..5d8a4468f 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
type=SparcTLB
size=64
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -64,7 +77,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
index 18a19b6d7..019979259 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:20:13
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:49
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index e3ffceab4..fc2e52856 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.122216 # Nu
sim_ticks 122215830000 # Number of ticks simulated
final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3409932 # Simulator instruction rate (inst/s)
-host_tick_rate 1709135687 # Simulator tick rate (ticks/s)
-host_mem_usage 338176 # Number of bytes of host memory used
-host_seconds 71.51 # Real time elapsed on the host
-sim_insts 243835278 # Number of instructions simulated
+host_inst_rate 4048457 # Simulator instruction rate (inst/s)
+host_op_rate 4048623 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2029262264 # Simulator tick rate (ticks/s)
+host_mem_usage 335836 # Number of bytes of host memory used
+host_seconds 60.23 # Real time elapsed on the host
+sim_insts 243825163 # Number of instructions simulated
+sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory
system.physmem.bytes_written 91606089 # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 443 # Nu
system.cpu.numCycles 244431661 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 243835278 # Number of instructions executed
+system.cpu.committedInsts 243825163 # Number of instructions committed
+system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index acd41b2d5..ad77524dc 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -130,20 +129,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index ca44a686d..0301a7a93 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:21:35
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:58:00
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 7dc591cfe..14199b227 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.362431 # Nu
sim_ticks 362430887000 # Number of ticks simulated
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1587659 # Simulator instruction rate (inst/s)
-host_tick_rate 2359857170 # Simulator tick rate (ticks/s)
-host_mem_usage 346888 # Number of bytes of host memory used
-host_seconds 153.58 # Real time elapsed on the host
-sim_insts 243835278 # Number of instructions simulated
+host_inst_rate 1947938 # Simulator instruction rate (inst/s)
+host_op_rate 1948018 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2895487158 # Simulator tick rate (ticks/s)
+host_mem_usage 344700 # Number of bytes of host memory used
+host_seconds 125.17 # Real time elapsed on the host
+sim_insts 243825163 # Number of instructions simulated
+sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1001472 # Number of bytes read from this memory
system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2560 # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 443 # Nu
system.cpu.numCycles 724861774 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 243835278 # Number of instructions executed
+system.cpu.committedInsts 243825163 # Number of instructions committed
+system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs 244420630 # To
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits
-system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 244420630 # number of overall hits
-system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
-system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 882 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 49266000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 49266000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 49266000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55857.142857 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55857.142857 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits
+system.cpu.icache.overall_hits::total 244420630 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
+system.cpu.icache.overall_misses::total 882 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 46620000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 46620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 46620000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
@@ -102,38 +116,59 @@ system.cpu.dcache.total_refs 104186700 # To
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 22855241 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
-system.cpu.dcache.demand_hits 104182818 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 104182818 # number of overall hits
-system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 46710 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
-system.cpu.dcache.demand_misses 939567 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 939567 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 12508482000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 1265712000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency 98000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency 13774194000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 13774194000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate 0.008938 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.008938 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency 24500 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14660.150899 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits
+system.cpu.dcache.overall_hits::total 104182818 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
+system.cpu.dcache.overall_misses::total 939567 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 935237 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 46710 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 939567 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 939567 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 9829911000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 1125582000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency 86000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 10955493000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 10955493000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.002040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.008938 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.008938 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 21500 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks
+system.cpu.dcache.writebacks::total 935237 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 865 # number of replacements
system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
@@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs 1585884 # To
system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 892658 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 935237 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 32147 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 924805 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 924805 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 14567 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 15648 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 15648 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 56212000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 757484000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 813696000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 813696000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 935237 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.311834 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.016639 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.016639 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits
+system.cpu.l2cache.overall_hits::total 924805 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses
+system.cpu.l2cache.overall_misses::total 15648 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 40 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 14567 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 15648 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 15648 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 43240000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 582680000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 625920000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 625920000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311834 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.016639 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.016639 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks
+system.cpu.l2cache.writebacks::total 40 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------