Stats: Updates due to bus changes

This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.

3 files changed, 102 insertions, 102 deletions

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 8e6bba913..2ba8ced6e 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 8432da315..f34d81d26 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:55:42
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 12:31:43
 gem5 executing on zizzer
 command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 362428997000 because target called exit()
+Exiting @ tick 362481577000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 75faf8d15..5f77178bc 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.362429                       # Number of seconds simulated
-sim_ticks                                362428997000                       # Number of ticks simulated
-final_tick                               362428997000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.362482                       # Number of seconds simulated
+sim_ticks                                362481577000                       # Number of ticks simulated
+final_tick                               362481577000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1801112                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1801186                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2677225778                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 354292                       # Number of bytes of host memory used
-host_seconds                                   135.37                       # Real time elapsed on the host
+host_inst_rate                                1217197                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1217247                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1809539933                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354248                       # Number of bytes of host memory used
+host_seconds                                   200.32                       # Real time elapsed on the host
 sim_insts                                   243825163                       # Number of instructions simulated
 sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             56256                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total           56256                       # Nu
 system.physmem.num_reads::cpu.inst                879                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14724                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15603                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               155219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2600057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2755276                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          155219                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             155219                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              155219                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2600057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2755276                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               155197                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2599680                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2754877                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          155197                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             155197                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              155197                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2599680                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2754877                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        724857994                       # number of cpu cycles simulated
+system.cpu.numCycles                        724963154                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   243825163                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                     105711442                       # nu
 system.cpu.num_load_insts                    82803522                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  724857994                       # Number of busy cycles
+system.cpu.num_busy_cycles                  724963154                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     25                       # number of replacements
-system.cpu.icache.tagsinuse                725.567220                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                725.564686                       # Cycle average of tags in use
 system.cpu.icache.total_refs                244420630                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               277120.895692                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     725.567220                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.354281                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.354281                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     725.564686                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.354280                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.354280                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    244420630                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       244420630                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     244420630                       # number of demand (read+write) hits
@@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst          882                       # n
 system.cpu.icache.demand_misses::total            882                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          882                       # number of overall misses
 system.cpu.icache.overall_misses::total           882                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     49266000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     49266000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     49266000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     49266000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     49266000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     49266000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     49333000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     49333000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     49333000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     49333000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     49333000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     49333000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    244421512                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    244421512                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    244421512                       # number of demand (read+write) accesses
@@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000004
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55857.142857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55857.142857                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55933.106576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55933.106576                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          882
 system.cpu.icache.demand_mshr_misses::total          882                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          882                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          882                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46620000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     46620000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     46620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46620000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     46620000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46687000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     46687000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     46687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46687000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     46687000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 935475                       # number of replacements
-system.cpu.dcache.tagsinuse               3563.821484                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3563.804804                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           134373316000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3563.821484                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.870074                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.870074                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle           134384281000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3563.804804                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.870070                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.870070                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     81327577                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        81327577                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits
@@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data       939567                       # n
 system.cpu.dcache.demand_misses::total         939567                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       939567                       # number of overall misses
 system.cpu.dcache.overall_misses::total        939567                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  12506592000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  12506592000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1265712000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1265712000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data        98000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total        98000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  13772304000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  13772304000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  13772304000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  13772304000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12510586000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12510586000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1267548000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1267548000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       101000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       101000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  13778134000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  13778134000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  13778134000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  13778134000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     82220434                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     82220434                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     22901951                       # number of WriteReq accesses(hits+misses)
@@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_miss_rate::total     0.008938                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.008938                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.008938                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        24500                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total        24500                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14658.139334                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14658.139334                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        25250                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total        25250                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14664.344320                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14664.344320                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -217,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       939567
 system.cpu.dcache.demand_mshr_misses::total       939567                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       939567                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       939567                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9828021000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9828021000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1125582000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1125582000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        86000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total        86000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10953603000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10953603000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10953603000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10953603000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9832015000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9832015000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1127418000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1127418000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        89000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        89000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10959433000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10959433000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10959433000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10959433000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002040                       # mshr miss rate for WriteReq accesses
@@ -237,30 +237,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_mshr_miss_rate::total     0.008938                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.008938                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        21500                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        21500                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        22250                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        22250                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              9744.405217                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              9744.633089                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 1813121                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 15586                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                116.330104                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  8861.272475                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    738.802087                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    144.330654                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.270425                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks  8861.504688                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    738.799807                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    144.328594                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.270432                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.022546                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.004405                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.297376                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.297383                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       892700                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         892703                       # number of ReadReq hits