diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/10.mcf/ref/sparc | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/10.mcf/ref/sparc')
4 files changed, 576 insertions, 559 deletions
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index c6db85421..d6f970870 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 8bd59a796..1f1ba7a8d 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38669 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:43:33 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66471 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 361597758500 because target called exit() +Exiting @ tick 361613361500 because exiting with last active thread context diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 33d560709..7f71ad751 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,541 +1,541 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361613 # Number of seconds simulated -sim_ticks 361613361500 # Number of ticks simulated -final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1844871 # Simulator instruction rate (inst/s) -host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2736100211 # Simulator tick rate (ticks/s) -host_mem_usage 385448 # Number of bytes of host memory used -host_seconds 132.16 # Real time elapsed on the host -sim_insts 243825150 # Number of instructions simulated -sim_ops 243835265 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory -system.physmem.bytes_read::total 998592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 443 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 723226723 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825150 # Number of instructions committed -system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses -system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726494 # number of integer instructions -system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written -system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read -system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711441 # number of memory refs -system.cpu.num_load_insts 82803521 # Number of load instructions -system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29302884 # Number of branches fetched -system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction -system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 244431613 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits -system.cpu.dcache.overall_hits::total 104182817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses -system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks -system.cpu.dcache.writebacks::total 935266 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency 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-system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses -system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits -system.cpu.icache.overall_hits::total 244420617 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses -system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 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of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits -system.cpu.l2cache.overall_hits::total 924850 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses -system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) 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# miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1036 # Transaction distribution -system.membus.trans_dist::ReadExReq 14567 # Transaction distribution -system.membus.trans_dist::ReadExResp 14567 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 15603 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.361613 +sim_ticks 361613361500 +final_tick 361613361500 +sim_freq 1000000000000 +host_inst_rate 812212 +host_op_rate 812245 +host_tick_rate 1204578633 +host_mem_usage 395932 +host_seconds 300.20 +sim_insts 243825150 +sim_ops 243835265 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 +system.physmem.bytes_read::cpu.inst 56256 +system.physmem.bytes_read::cpu.data 942336 +system.physmem.bytes_read::total 998592 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12950522000 +system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 +system.cpu.dcache.overall_miss_latency::total 12950522000 +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 +system.cpu.dcache.ReadReq_accesses::total 82220433 +system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 +system.cpu.dcache.WriteReq_accesses::total 22901951 +system.cpu.dcache.SwapReq_accesses::cpu.data 3886 +system.cpu.dcache.SwapReq_accesses::total 3886 +system.cpu.dcache.demand_accesses::cpu.data 105122384 +system.cpu.dcache.demand_accesses::total 105122384 +system.cpu.dcache.overall_accesses::cpu.data 105122384 +system.cpu.dcache.overall_accesses::total 105122384 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 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+system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 15603 +system.membus.reqLayer0.occupancy 15606500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 78015000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- |