stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

    commit 2c1286865fc2542a0586ca4ff40b00765d17b348
    Author: Brandon Potter <Brandon.Potter@amd.com>
    Date:   Wed Mar 1 14:52:23 2017 -0600

        syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 74 insertions, 23 deletions

diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index e54b7db9f..ebb274721 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
 init_param=0
 kernel=
 kernel_addr_check=true
+kvm_vm=Null
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
@@ -65,7 +66,7 @@ SSITSize=1024
 activity=0
 backComSize=5
 branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
 checker=Null
 clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
@@ -139,6 +140,7 @@ socket_id=0
 squashWidth=8
 store_set_clear_period=250000
 switched_out=false
+syscallRetryLatency=10000
 system=system
 tracer=system.cpu.tracer
 trapLatency=13
@@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
@@ -200,6 +202,7 @@ response_latency=2
 sequential_access=false
 size=262144
 system=system
+tag_latency=2
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -212,15 +215,16 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=262144
+tag_latency=2
 
 [system.cpu.dtb]
 type=X86TLB
@@ -313,10 +317,10 @@ pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
-children=opList0 opList1 opList2
+children=opList0 opList1 opList2 opList3 opList4
 count=2
 eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
 
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
@@ -328,11 +332,25 @@ pipelined=true
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
 opClass=FloatDiv
 opLat=12
 pipelined=false
 
-[system.cpu.fuPool.FUList3.opList2]
+[system.cpu.fuPool.FUList3.opList4]
 type=OpDesc
 eventq_index=0
 opClass=FloatSqrt
@@ -341,18 +359,25 @@ pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
 
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList4.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemRead
 opLat=1
 pipelined=true
 
+[system.cpu.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
 [system.cpu.fuPool.FUList5]
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -502,24 +527,31 @@ pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=0
 eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
 
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList6.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu.fuPool.FUList7]
 type=FUDesc
-children=opList0 opList1
+children=opList0 opList1 opList2 opList3
 count=4
 eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
 
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
@@ -535,6 +567,20 @@ opClass=MemWrite
 opLat=1
 pipelined=true
 
+[system.cpu.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
 [system.cpu.fuPool.FUList8]
 type=FUDesc
 children=opList
@@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
@@ -573,6 +619,7 @@ response_latency=2
 sequential_access=false
 size=131072
 system=system
+tag_latency=2
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -585,15 +632,16 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=131072
+tag_latency=2
 
 [system.cpu.interrupts]
 type=X86LocalApic
@@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=20
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -660,6 +708,7 @@ response_latency=20
 sequential_access=false
 size=2097152
 system=system
+tag_latency=20
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -672,15 +721,16 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=20
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=20
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=2097152
+tag_latency=20
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
@@ -716,7 +766,7 @@ type=ExeTracer
 eventq_index=0
 
 [system.cpu.workload]
-type=LiveProcess
+type=Process
 cmd=mcf mcf.in
 cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 drivers=
@@ -725,14 +775,15 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
 output=cout
+pgid=100
 pid=100
-ppid=99
+ppid=0
 simpoint=55300000000
 system=system
 uid=100