diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 2102 |
1 files changed, 1051 insertions, 1051 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 492625dc5..b9b8eb4c6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,1055 +1,1055 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065721 # Number of seconds simulated -sim_ticks 65721494500 # Number of ticks simulated -final_tick 65721494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 191999 # Simulator instruction rate (inst/s) -host_op_rate 338080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79869594 # Simulator tick rate (ticks/s) -host_mem_usage 415448 # Number of bytes of host memory used -host_seconds 822.86 # Real time elapsed on the host -sim_insts 157988547 # Number of instructions simulated -sim_ops 278192464 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory -system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19136 # Number of bytes written to this memory -system.physmem.bytes_written::total 19136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 299 # Number of write requests responded to by this memory -system.physmem.num_writes::total 299 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1046842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28796424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29843265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1046842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1046842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 291168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 291168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 291168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1046842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28796424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30134433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30646 # Number of read requests accepted -system.physmem.writeReqs 299 # Number of write requests accepted -system.physmem.readBursts 30646 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 299 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1952832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue -system.physmem.bytesWritten 17216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1961344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1937 # Per bank write bursts -system.physmem.perBankRdBursts::1 2081 # Per bank write bursts -system.physmem.perBankRdBursts::2 2039 # Per bank write bursts -system.physmem.perBankRdBursts::3 1941 # Per bank write bursts -system.physmem.perBankRdBursts::4 2068 # Per bank write bursts -system.physmem.perBankRdBursts::5 1911 # Per bank write bursts -system.physmem.perBankRdBursts::6 1977 # Per bank write bursts -system.physmem.perBankRdBursts::7 1878 # Per bank write bursts -system.physmem.perBankRdBursts::8 1945 # Per bank write bursts -system.physmem.perBankRdBursts::9 1939 # Per bank write bursts -system.physmem.perBankRdBursts::10 1805 # Per bank write bursts -system.physmem.perBankRdBursts::11 1794 # Per bank write bursts -system.physmem.perBankRdBursts::12 1792 # Per bank write bursts -system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1827 # Per bank write bursts -system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 8 # Per bank write bursts -system.physmem.perBankWrBursts::1 125 # Per bank write bursts -system.physmem.perBankWrBursts::2 25 # Per bank write bursts -system.physmem.perBankWrBursts::3 26 # Per bank write bursts -system.physmem.perBankWrBursts::4 54 # Per bank write bursts -system.physmem.perBankWrBursts::5 8 # Per bank write bursts -system.physmem.perBankWrBursts::6 14 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 6 # Per bank write bursts -system.physmem.perBankWrBursts::10 3 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65721290500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30646 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 299 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2852 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 690.064516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 482.522488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 397.377699 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2852 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 15 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2030.466667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.801531 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7801.447410 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 15 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 15 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.933333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.931540 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.258199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 6.67% 6.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 14 93.33% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 15 # Writes before turning the bus around for reads -system.physmem.totQLat 402617750 # Total ticks spent queuing -system.physmem.totMemAccLat 974736500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13194.96 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31944.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.29 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.51 # Average write queue length when enqueuing -system.physmem.readRowHits 27734 # Number of row buffer hits during reads -system.physmem.writeRowHits 187 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.54 # Row buffer hit rate for writes -system.physmem.avgGap 2123809.68 # Average gap between requests -system.physmem.pageHitRate 90.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11052720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5855685 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 113040480 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1357200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 309163920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 263324610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 16569120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 979073610 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 268447200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 14975920920 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 16943805465 # Total energy per rank (pJ) -system.physmem_0.averagePower 257.812234 # Core power per rank (mW) -system.physmem_0.totalIdleTime 65100637750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 22061500 # Time in different power states -system.physmem_0.memoryStateTime::REF 131194000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62254705500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 699065250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 467433500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 2147034750 # Time in different power states -system.physmem_1.actEnergy 9374820 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4967655 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 104822340 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 372471840.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 249536310 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 19488480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1119740490 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 403290240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14835337125 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17119488570 # Total energy per rank (pJ) -system.physmem_1.averagePower 260.485370 # Core power per rank (mW) -system.physmem_1.totalIdleTime 65120969250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 28589000 # Time in different power states -system.physmem_1.memoryStateTime::REF 158136000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 61616793750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1050209250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 412212500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2455554000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40406290 # Number of BP lookups -system.cpu.branchPred.condPredicted 40406290 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1431845 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26031629 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6025963 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 91921 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26031629 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 20992529 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5039100 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 530263 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131442990 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30464048 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219898668 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40406290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27018492 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99269738 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2979935 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 465 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 7592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 128961 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29660171 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 359072 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 17 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131360995 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.946103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.409063 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65827184 50.11% 50.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4032527 3.07% 53.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3600376 2.74% 55.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6081929 4.63% 60.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7728911 5.88% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5535416 4.21% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3331669 2.54% 73.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2842658 2.16% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32380325 24.65% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131360995 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307405 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.672959 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15255907 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64520496 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40208811 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9885814 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1489967 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 362265652 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1489967 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20796133 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11129664 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23832 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44255424 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53665975 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 352608748 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23342 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 777450 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46732943 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5205031 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 354925639 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934456502 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 575559102 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 21159 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 75712892 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 482 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 483 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64647332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112313472 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38475522 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51426374 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8868395 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343765046 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3883 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 317634440 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 163759 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65576465 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 101836454 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3438 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131360995 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.418027 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.167913 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131360995 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 317634440 # Type of FU issued -system.cpu.iq.rate 2.416519 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4120029 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012971 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 770896978 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 409373525 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 313389776 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 16685 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 31480 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3775 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321713926 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7204 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57497351 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21534087 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66072 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 62227 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7035770 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4204 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141777 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1489967 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8057522 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2987683 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343768929 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 139556 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112313472 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38475522 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1604 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2862 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2991864 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 62227 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 520614 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1090823 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1611437 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 315197484 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100490397 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2436956 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134782236 # number of memory reference insts executed -system.cpu.iew.exec_branches 32089039 # Number of branches executed -system.cpu.iew.exec_stores 34291839 # Number of stores executed -system.cpu.iew.exec_rate 2.397979 # Inst execution rate -system.cpu.iew.wb_sent 314036708 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 313393551 # cumulative count of insts written-back -system.cpu.iew.wb_producers 237399400 # num instructions producing a value -system.cpu.iew.wb_consumers 342887037 # num instructions consuming a value -system.cpu.iew.wb_rate 2.384255 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692355 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 65692241 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1439325 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121896437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.282203 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.051706 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 56939574 46.71% 46.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121896437 # Number of insts commited each cycle -system.cpu.commit.committedInsts 157988547 # Number of instructions committed -system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 122219137 # Number of memory references committed -system.cpu.commit.loads 90779385 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 29309705 # Number of branches committed -system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. -system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 90779371 32.63% 88.70% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 31439738 11.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 14 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23179490 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 442601652 # The number of ROB reads -system.cpu.rob.rob_writes 697313320 # The number of ROB writes -system.cpu.timesIdled 909 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 81995 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 157988547 # Number of Instructions Simulated -system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.831978 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.831978 # CPI: Total CPI of All Threads -system.cpu.ipc 1.201955 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.201955 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 502529726 # number of integer regfile reads -system.cpu.int_regfile_writes 247564665 # number of integer regfile writes -system.cpu.fp_regfile_reads 3566 # number of floating regfile reads -system.cpu.fp_regfile_writes 731 # number of floating regfile writes -system.cpu.cc_regfile_reads 108994485 # number of cc regfile reads -system.cpu.cc_regfile_writes 65428204 # number of cc regfile writes -system.cpu.misc_regfile_reads 201784346 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073509 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.268199 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71482624 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077605 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.406263 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21075173500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992985 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992985 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 504 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150633517 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150633517 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40136683 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40136683 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345941 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345941 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71482624 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71482624 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71482624 # number of overall hits -system.cpu.dcache.overall_hits::total 71482624 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2701521 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2701521 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93811 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93811 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2795332 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2795332 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2795332 # number of overall misses -system.cpu.dcache.overall_misses::total 2795332 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32454671000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3177582491 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35632253491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35632253491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35632253491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35632253491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42838204 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42838204 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74277956 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74277956 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74277956 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74277956 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.063063 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002984 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12747.055982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12747.055982 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 219709 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 682 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43158 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066902 # number of writebacks -system.cpu.dcache.writebacks::total 2066902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 705827 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11900 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 717727 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 717727 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 717727 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 717727 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995694 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81911 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077605 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077605 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077605 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077605 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3020316491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3020316491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27293249991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27293249991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27293249991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27293249991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002605 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002605 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027971 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027971 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.652942 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.652942 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36873.148796 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36873.148796 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 86 # number of replacements -system.cpu.icache.tags.tagsinuse 865.699388 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29658716 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1101 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26937.980018 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 865.699388 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.422705 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.422705 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1015 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.495605 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59321439 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59321439 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29658716 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29658716 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29658716 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29658716 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29658716 # number of overall hits -system.cpu.icache.overall_hits::total 29658716 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1453 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1453 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1453 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1453 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1453 # number of overall misses -system.cpu.icache.overall_misses::total 1453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 154504998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 154504998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 154504998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 154504998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 154504998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 154504998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29660169 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29660169 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29660169 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29660169 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29660169 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29660169 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 106335.167240 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 106335.167240 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 106335.167240 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 106335.167240 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 106335.167240 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 106335.167240 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4008 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 235.764706 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 86 # number of writebacks -system.cpu.icache.writebacks::total 86 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 352 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 352 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 352 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 352 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 352 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1101 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1101 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1101 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1101 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1101 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1101 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 113239998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 113239998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 113239998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 113239998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 113239998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 113239998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102851.950954 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102851.950954 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102851.950954 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 102851.950954 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102851.950954 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 102851.950954 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 680 # number of replacements -system.cpu.l2cache.tags.tagsinuse 21650.115816 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4121613 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30665 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 134.407729 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.138386 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 704.921194 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20942.056236 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000096 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021512 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.639101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.660709 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29985 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 54 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29640 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915070 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33248889 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33248889 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2066902 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2066902 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 86 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 86 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 52946 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 52946 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995088 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1995088 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2048034 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2048060 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2048034 # number of overall hits -system.cpu.l2cache.overall_hits::total 2048060 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1075 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1075 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 575 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 575 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1075 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29571 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30646 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1075 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29571 # number of overall misses -system.cpu.l2cache.overall_misses::total 30646 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2341147500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2341147500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 111300000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 111300000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 88414500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 88414500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 111300000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2429562000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2540862000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 111300000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2429562000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2540862000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066902 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2066902 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 86 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 86 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 81942 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 81942 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1101 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1101 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995663 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1995663 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1101 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2077605 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2078706 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1101 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2077605 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2078706 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353860 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.353860 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014743 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014743 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 299 # number of writebacks -system.cpu.l2cache.writebacks::total 299 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4152301 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 330 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 86 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6988 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6231007 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265324416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 680 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19136 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000170 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.013047 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079386 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4143138500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1652498 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116407500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 30996 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 350 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1650 # Transaction distribution -system.membus.trans_dist::WritebackDirty 299 # Transaction distribution -system.membus.trans_dist::CleanEvict 51 # Transaction distribution -system.membus.trans_dist::ReadExReq 28996 # Transaction distribution -system.membus.trans_dist::ReadExResp 28996 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1650 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61642 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1980480 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30646 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30646 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30646 # Request fanout histogram -system.membus.reqLayer0.occupancy 43591500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161486250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +sim_seconds 0.065721 +sim_ticks 65721494500 +final_tick 65721494500 +sim_freq 1000000000000 +host_inst_rate 83517 +host_op_rate 147060 +host_tick_rate 34742064 +host_mem_usage 427260 +host_seconds 1891.70 +sim_insts 157988547 +sim_ops 278192464 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.physmem.bytes_read::cpu.inst 68800 +system.physmem.bytes_read::cpu.data 1892544 +system.physmem.bytes_read::total 1961344 +system.physmem.bytes_inst_read::cpu.inst 68800 +system.physmem.bytes_inst_read::total 68800 +system.physmem.bytes_written::writebacks 19136 +system.physmem.bytes_written::total 19136 +system.physmem.num_reads::cpu.inst 1075 +system.physmem.num_reads::cpu.data 29571 +system.physmem.num_reads::total 30646 +system.physmem.num_writes::writebacks 299 +system.physmem.num_writes::total 299 +system.physmem.bw_read::cpu.inst 1046842 +system.physmem.bw_read::cpu.data 28796424 +system.physmem.bw_read::total 29843265 +system.physmem.bw_inst_read::cpu.inst 1046842 +system.physmem.bw_inst_read::total 1046842 +system.physmem.bw_write::writebacks 291168 +system.physmem.bw_write::total 291168 +system.physmem.bw_total::writebacks 291168 +system.physmem.bw_total::cpu.inst 1046842 +system.physmem.bw_total::cpu.data 28796424 +system.physmem.bw_total::total 30134433 +system.physmem.readReqs 30646 +system.physmem.writeReqs 299 +system.physmem.readBursts 30646 +system.physmem.writeBursts 299 +system.physmem.bytesReadDRAM 1952832 +system.physmem.bytesReadWrQ 8512 +system.physmem.bytesWritten 17216 +system.physmem.bytesReadSys 1961344 +system.physmem.bytesWrittenSys 19136 +system.physmem.servicedByWrQ 133 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 1937 +system.physmem.perBankRdBursts::1 2081 +system.physmem.perBankRdBursts::2 2039 +system.physmem.perBankRdBursts::3 1941 +system.physmem.perBankRdBursts::4 2068 +system.physmem.perBankRdBursts::5 1911 +system.physmem.perBankRdBursts::6 1977 +system.physmem.perBankRdBursts::7 1878 +system.physmem.perBankRdBursts::8 1945 +system.physmem.perBankRdBursts::9 1939 +system.physmem.perBankRdBursts::10 1805 +system.physmem.perBankRdBursts::11 1794 +system.physmem.perBankRdBursts::12 1792 +system.physmem.perBankRdBursts::13 1800 +system.physmem.perBankRdBursts::14 1827 +system.physmem.perBankRdBursts::15 1779 +system.physmem.perBankWrBursts::0 8 +system.physmem.perBankWrBursts::1 125 +system.physmem.perBankWrBursts::2 25 +system.physmem.perBankWrBursts::3 26 +system.physmem.perBankWrBursts::4 54 +system.physmem.perBankWrBursts::5 8 +system.physmem.perBankWrBursts::6 14 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 6 +system.physmem.perBankWrBursts::10 3 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 65721290500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 30646 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 299 +system.physmem.rdQLenPdf::0 29942 +system.physmem.rdQLenPdf::1 423 +system.physmem.rdQLenPdf::2 106 +system.physmem.rdQLenPdf::3 36 +system.physmem.rdQLenPdf::4 5 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 1 +system.physmem.wrQLenPdf::1 1 +system.physmem.wrQLenPdf::2 1 +system.physmem.wrQLenPdf::3 1 +system.physmem.wrQLenPdf::4 1 +system.physmem.wrQLenPdf::5 1 +system.physmem.wrQLenPdf::6 1 +system.physmem.wrQLenPdf::7 1 +system.physmem.wrQLenPdf::8 1 +system.physmem.wrQLenPdf::9 1 +system.physmem.wrQLenPdf::10 1 +system.physmem.wrQLenPdf::11 1 +system.physmem.wrQLenPdf::12 1 +system.physmem.wrQLenPdf::13 1 +system.physmem.wrQLenPdf::14 1 +system.physmem.wrQLenPdf::15 15 +system.physmem.wrQLenPdf::16 16 +system.physmem.wrQLenPdf::17 16 +system.physmem.wrQLenPdf::18 16 +system.physmem.wrQLenPdf::19 16 +system.physmem.wrQLenPdf::20 16 +system.physmem.wrQLenPdf::21 16 +system.physmem.wrQLenPdf::22 16 +system.physmem.wrQLenPdf::23 16 +system.physmem.wrQLenPdf::24 16 +system.physmem.wrQLenPdf::25 16 +system.physmem.wrQLenPdf::26 16 +system.physmem.wrQLenPdf::27 16 +system.physmem.wrQLenPdf::28 16 +system.physmem.wrQLenPdf::29 16 +system.physmem.wrQLenPdf::30 15 +system.physmem.wrQLenPdf::31 15 +system.physmem.wrQLenPdf::32 15 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 2852 +system.physmem.bytesPerActivate::mean 690.064516 +system.physmem.bytesPerActivate::gmean 482.522488 +system.physmem.bytesPerActivate::stdev 397.377699 +system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% +system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% +system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% +system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% +system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% +system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% +system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% +system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% +system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% +system.physmem.bytesPerActivate::total 2852 +system.physmem.rdPerTurnAround::samples 15 +system.physmem.rdPerTurnAround::mean 2030.466667 +system.physmem.rdPerTurnAround::gmean 23.801531 +system.physmem.rdPerTurnAround::stdev 7801.447410 +system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% +system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% +system.physmem.rdPerTurnAround::total 15 +system.physmem.wrPerTurnAround::samples 15 +system.physmem.wrPerTurnAround::mean 17.933333 +system.physmem.wrPerTurnAround::gmean 17.931540 +system.physmem.wrPerTurnAround::stdev 0.258199 +system.physmem.wrPerTurnAround::17 1 6.67% 6.67% +system.physmem.wrPerTurnAround::18 14 93.33% 100.00% +system.physmem.wrPerTurnAround::total 15 +system.physmem.totQLat 402617750 +system.physmem.totMemAccLat 974736500 +system.physmem.totBusLat 152565000 +system.physmem.avgQLat 13194.96 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 31944.96 +system.physmem.avgRdBW 29.71 +system.physmem.avgWrBW 0.26 +system.physmem.avgRdBWSys 29.84 +system.physmem.avgWrBWSys 0.29 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 0.23 +system.physmem.busUtilRead 0.23 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.00 +system.physmem.avgWrQLen 12.51 +system.physmem.readRowHits 27734 +system.physmem.writeRowHits 187 +system.physmem.readRowHitRate 90.89 +system.physmem.writeRowHitRate 62.54 +system.physmem.avgGap 2123809.68 +system.physmem.pageHitRate 90.62 +system.physmem_0.actEnergy 11052720 +system.physmem_0.preEnergy 5855685 +system.physmem_0.readEnergy 113040480 +system.physmem_0.writeEnergy 1357200 +system.physmem_0.refreshEnergy 309163920.000000 +system.physmem_0.actBackEnergy 263324610 +system.physmem_0.preBackEnergy 16569120 +system.physmem_0.actPowerDownEnergy 979073610 +system.physmem_0.prePowerDownEnergy 268447200 +system.physmem_0.selfRefreshEnergy 14975920920 +system.physmem_0.totalEnergy 16943805465 +system.physmem_0.averagePower 257.812234 +system.physmem_0.totalIdleTime 65100637750 +system.physmem_0.memoryStateTime::IDLE 22061500 +system.physmem_0.memoryStateTime::REF 131194000 +system.physmem_0.memoryStateTime::SREF 62254705500 +system.physmem_0.memoryStateTime::PRE_PDN 699065250 +system.physmem_0.memoryStateTime::ACT 467433500 +system.physmem_0.memoryStateTime::ACT_PDN 2147034750 +system.physmem_1.actEnergy 9374820 +system.physmem_1.preEnergy 4967655 +system.physmem_1.readEnergy 104822340 +system.physmem_1.writeEnergy 46980 +system.physmem_1.refreshEnergy 372471840.000000 +system.physmem_1.actBackEnergy 249536310 +system.physmem_1.preBackEnergy 19488480 +system.physmem_1.actPowerDownEnergy 1119740490 +system.physmem_1.prePowerDownEnergy 403290240 +system.physmem_1.selfRefreshEnergy 14835337125 +system.physmem_1.totalEnergy 17119488570 +system.physmem_1.averagePower 260.485370 +system.physmem_1.totalIdleTime 65120969250 +system.physmem_1.memoryStateTime::IDLE 28589000 +system.physmem_1.memoryStateTime::REF 158136000 +system.physmem_1.memoryStateTime::SREF 61616793750 +system.physmem_1.memoryStateTime::PRE_PDN 1050209250 +system.physmem_1.memoryStateTime::ACT 412212500 +system.physmem_1.memoryStateTime::ACT_PDN 2455554000 +system.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.branchPred.lookups 40406290 +system.cpu.branchPred.condPredicted 40406290 +system.cpu.branchPred.condIncorrect 1431845 +system.cpu.branchPred.BTBLookups 26031629 +system.cpu.branchPred.BTBHits 0 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 0.000000 +system.cpu.branchPred.usedRAS 6025963 +system.cpu.branchPred.RASInCorrect 91921 +system.cpu.branchPred.indirectLookups 26031629 +system.cpu.branchPred.indirectHits 20992529 +system.cpu.branchPred.indirectMisses 5039100 +system.cpu.branchPredindirectMispredicted 530263 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.workload.numSyscalls 444 +system.cpu.pwrStateResidencyTicks::ON 65721494500 +system.cpu.numCycles 131442990 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 30464048 +system.cpu.fetch.Insts 219898668 +system.cpu.fetch.Branches 40406290 +system.cpu.fetch.predictedBranches 27018492 +system.cpu.fetch.Cycles 99269738 +system.cpu.fetch.SquashCycles 2979934 +system.cpu.fetch.TlbCycles 465 +system.cpu.fetch.MiscStallCycles 7592 +system.cpu.fetch.PendingTrapStallCycles 128961 +system.cpu.fetch.PendingQuiesceStallCycles 50 +system.cpu.fetch.IcacheWaitRetryStallCycles 174 +system.cpu.fetch.CacheLines 29660171 +system.cpu.fetch.IcacheSquashes 359072 +system.cpu.fetch.ItlbSquashes 17 +system.cpu.fetch.rateDist::samples 131360995 +system.cpu.fetch.rateDist::mean 2.946103 +system.cpu.fetch.rateDist::stdev 3.409063 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 65827184 50.11% 50.11% +system.cpu.fetch.rateDist::1 4032527 3.07% 53.18% +system.cpu.fetch.rateDist::2 3600376 2.74% 55.92% +system.cpu.fetch.rateDist::3 6081929 4.63% 60.55% +system.cpu.fetch.rateDist::4 7728911 5.88% 66.44% +system.cpu.fetch.rateDist::5 5535416 4.21% 70.65% +system.cpu.fetch.rateDist::6 3331669 2.54% 73.19% +system.cpu.fetch.rateDist::7 2842658 2.16% 75.35% +system.cpu.fetch.rateDist::8 32380325 24.65% 100.00% +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 8 +system.cpu.fetch.rateDist::total 131360995 +system.cpu.fetch.branchRate 0.307405 +system.cpu.fetch.rate 1.672959 +system.cpu.decode.IdleCycles 15255907 +system.cpu.decode.BlockedCycles 64520496 +system.cpu.decode.RunCycles 40208811 +system.cpu.decode.UnblockCycles 9885814 +system.cpu.decode.SquashCycles 1489967 +system.cpu.decode.DecodedInsts 362265652 +system.cpu.rename.SquashCycles 1489967 +system.cpu.rename.IdleCycles 20796133 +system.cpu.rename.BlockCycles 11129664 +system.cpu.rename.serializeStallCycles 23832 +system.cpu.rename.RunCycles 44255424 +system.cpu.rename.UnblockCycles 53665975 +system.cpu.rename.RenamedInsts 352608748 +system.cpu.rename.ROBFullEvents 23342 +system.cpu.rename.IQFullEvents 777450 +system.cpu.rename.LQFullEvents 46732943 +system.cpu.rename.SQFullEvents 5205031 +system.cpu.rename.RenamedOperands 354925639 +system.cpu.rename.RenameLookups 934456502 +system.cpu.rename.int_rename_lookups 575559102 +system.cpu.rename.fp_rename_lookups 21159 +system.cpu.rename.CommittedMaps 279212747 +system.cpu.rename.UndoneMaps 75712892 +system.cpu.rename.serializingInsts 482 +system.cpu.rename.tempSerializingInsts 483 +system.cpu.rename.skidInsts 64647332 +system.cpu.memDep0.insertedLoads 112313472 +system.cpu.memDep0.insertedStores 38475522 +system.cpu.memDep0.conflictingLoads 51426374 +system.cpu.memDep0.conflictingStores 8868395 +system.cpu.iq.iqInstsAdded 343765046 +system.cpu.iq.iqNonSpecInstsAdded 3883 +system.cpu.iq.iqInstsIssued 317634440 +system.cpu.iq.iqSquashedInstsIssued 163759 +system.cpu.iq.iqSquashedInstsExamined 65576464 +system.cpu.iq.iqSquashedOperandsExamined 101836454 +system.cpu.iq.iqSquashedNonSpecRemoved 3438 +system.cpu.iq.issued_per_cycle::samples 131360995 +system.cpu.iq.issued_per_cycle::mean 2.418027 +system.cpu.iq.issued_per_cycle::stdev 2.167913 +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% +system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14% +system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41% +system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41% +system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80% +system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43% +system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23% +system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34% +system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43% +system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00% +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::min_value 0 +system.cpu.iq.issued_per_cycle::max_value 8 +system.cpu.iq.issued_per_cycle::total 131360995 +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% +system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92% +system.cpu.iq.fu_full::IntMult 0 0.00% 8.92% +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92% +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92% +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92% +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92% +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92% +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92% +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92% +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92% +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92% +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92% +system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32% +system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97% +system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97% +system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00% +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% +system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20% +system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20% +system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20% +system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20% +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20% +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20% +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20% +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20% +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20% +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20% +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20% +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20% +system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08% +system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00% +system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00% +system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00% +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::total 317634440 +system.cpu.iq.rate 2.416519 +system.cpu.iq.fu_busy_cnt 4120029 +system.cpu.iq.fu_busy_rate 0.012971 +system.cpu.iq.int_inst_queue_reads 770896978 +system.cpu.iq.int_inst_queue_writes 409373524 +system.cpu.iq.int_inst_queue_wakeup_accesses 313389776 +system.cpu.iq.fp_inst_queue_reads 16685 +system.cpu.iq.fp_inst_queue_writes 31480 +system.cpu.iq.fp_inst_queue_wakeup_accesses 3775 +system.cpu.iq.int_alu_accesses 321713926 +system.cpu.iq.fp_alu_accesses 7204 +system.cpu.iew.lsq.thread0.forwLoads 57497351 +system.cpu.iew.lsq.thread0.invAddrLoads 0 +system.cpu.iew.lsq.thread0.squashedLoads 21534087 +system.cpu.iew.lsq.thread0.ignoredResponses 66072 +system.cpu.iew.lsq.thread0.memOrderViolation 62227 +system.cpu.iew.lsq.thread0.squashedStores 7035770 +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 +system.cpu.iew.lsq.thread0.blockedLoads 0 +system.cpu.iew.lsq.thread0.rescheduledLoads 4204 +system.cpu.iew.lsq.thread0.cacheBlocked 141777 +system.cpu.iew.iewIdleCycles 0 +system.cpu.iew.iewSquashCycles 1489967 +system.cpu.iew.iewBlockCycles 8057522 +system.cpu.iew.iewUnblockCycles 2987683 +system.cpu.iew.iewDispatchedInsts 343768929 +system.cpu.iew.iewDispSquashedInsts 139556 +system.cpu.iew.iewDispLoadInsts 112313472 +system.cpu.iew.iewDispStoreInsts 38475522 +system.cpu.iew.iewDispNonSpecInsts 1604 +system.cpu.iew.iewIQFullEvents 2862 +system.cpu.iew.iewLSQFullEvents 2991864 +system.cpu.iew.memOrderViolationEvents 62227 +system.cpu.iew.predictedTakenIncorrect 520614 +system.cpu.iew.predictedNotTakenIncorrect 1090823 +system.cpu.iew.branchMispredicts 1611437 +system.cpu.iew.iewExecutedInsts 315197484 +system.cpu.iew.iewExecLoadInsts 100490397 +system.cpu.iew.iewExecSquashedInsts 2436956 +system.cpu.iew.exec_swp 0 +system.cpu.iew.exec_nop 0 +system.cpu.iew.exec_refs 134782236 +system.cpu.iew.exec_branches 32089039 +system.cpu.iew.exec_stores 34291839 +system.cpu.iew.exec_rate 2.397979 +system.cpu.iew.wb_sent 314036708 +system.cpu.iew.wb_count 313393551 +system.cpu.iew.wb_producers 237399400 +system.cpu.iew.wb_consumers 342887037 +system.cpu.iew.wb_rate 2.384255 +system.cpu.iew.wb_fanout 0.692355 +system.cpu.commit.commitSquashedInsts 65692241 +system.cpu.commit.commitNonSpecStalls 445 +system.cpu.commit.branchMispredicts 1439325 +system.cpu.commit.committed_per_cycle::samples 121896438 +system.cpu.commit.committed_per_cycle::mean 2.282203 +system.cpu.commit.committed_per_cycle::stdev 3.051706 +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% +system.cpu.commit.committed_per_cycle::0 56939575 46.71% 46.71% +system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21% +system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26% +system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44% +system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17% +system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62% +system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39% +system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98% +system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00% +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% +system.cpu.commit.committed_per_cycle::min_value 0 +system.cpu.commit.committed_per_cycle::max_value 8 +system.cpu.commit.committed_per_cycle::total 121896438 +system.cpu.commit.committedInsts 157988547 +system.cpu.commit.committedOps 278192464 +system.cpu.commit.swp_count 0 +system.cpu.commit.refs 122219137 +system.cpu.commit.loads 90779385 +system.cpu.commit.membars 0 +system.cpu.commit.branches 29309705 +system.cpu.commit.fp_insts 40 +system.cpu.commit.int_insts 278169481 +system.cpu.commit.function_calls 4237596 +system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% +system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% +system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% +system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% +system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% +system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.07% +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 56.07% +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% +system.cpu.commit.op_class_0::MemRead 90779371 32.63% 88.70% +system.cpu.commit.op_class_0::MemWrite 31439738 11.30% 100.00% +system.cpu.commit.op_class_0::FloatMemRead 14 0.00% 100.00% +system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% +system.cpu.commit.op_class_0::total 278192464 +system.cpu.commit.bw_lim_events 23179490 +system.cpu.rob.rob_reads 442601653 +system.cpu.rob.rob_writes 697313319 +system.cpu.timesIdled 909 +system.cpu.idleCycles 81995 +system.cpu.committedInsts 157988547 +system.cpu.committedOps 278192464 +system.cpu.cpi 0.831978 +system.cpu.cpi_total 0.831978 +system.cpu.ipc 1.201955 +system.cpu.ipc_total 1.201955 +system.cpu.int_regfile_reads 502529726 +system.cpu.int_regfile_writes 247564665 +system.cpu.fp_regfile_reads 3566 +system.cpu.fp_regfile_writes 731 +system.cpu.cc_regfile_reads 108994485 +system.cpu.cc_regfile_writes 65428204 +system.cpu.misc_regfile_reads 201784346 +system.cpu.misc_regfile_writes 1 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.dcache.tags.replacements 2073509 +system.cpu.dcache.tags.tagsinuse 4067.268199 +system.cpu.dcache.tags.total_refs 71482624 +system.cpu.dcache.tags.sampled_refs 2077605 +system.cpu.dcache.tags.avg_refs 34.406263 +system.cpu.dcache.tags.warmup_cycle 21075173500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199 +system.cpu.dcache.tags.occ_percent::cpu.data 0.992985 +system.cpu.dcache.tags.occ_percent::total 0.992985 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 504 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 147 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 150633517 +system.cpu.dcache.tags.data_accesses 150633517 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.dcache.ReadReq_hits::cpu.data 40136683 +system.cpu.dcache.ReadReq_hits::total 40136683 +system.cpu.dcache.WriteReq_hits::cpu.data 31345941 +system.cpu.dcache.WriteReq_hits::total 31345941 +system.cpu.dcache.demand_hits::cpu.data 71482624 +system.cpu.dcache.demand_hits::total 71482624 +system.cpu.dcache.overall_hits::cpu.data 71482624 +system.cpu.dcache.overall_hits::total 71482624 +system.cpu.dcache.ReadReq_misses::cpu.data 2701521 +system.cpu.dcache.ReadReq_misses::total 2701521 +system.cpu.dcache.WriteReq_misses::cpu.data 93811 +system.cpu.dcache.WriteReq_misses::total 93811 +system.cpu.dcache.demand_misses::cpu.data 2795332 +system.cpu.dcache.demand_misses::total 2795332 +system.cpu.dcache.overall_misses::cpu.data 2795332 +system.cpu.dcache.overall_misses::total 2795332 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000 +system.cpu.dcache.ReadReq_miss_latency::total 32454671000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491 +system.cpu.dcache.WriteReq_miss_latency::total 3177582491 +system.cpu.dcache.demand_miss_latency::cpu.data 35632253491 +system.cpu.dcache.demand_miss_latency::total 35632253491 +system.cpu.dcache.overall_miss_latency::cpu.data 35632253491 +system.cpu.dcache.overall_miss_latency::total 35632253491 +system.cpu.dcache.ReadReq_accesses::cpu.data 42838204 +system.cpu.dcache.ReadReq_accesses::total 42838204 +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 +system.cpu.dcache.WriteReq_accesses::total 31439752 +system.cpu.dcache.demand_accesses::cpu.data 74277956 +system.cpu.dcache.demand_accesses::total 74277956 +system.cpu.dcache.overall_accesses::cpu.data 74277956 +system.cpu.dcache.overall_accesses::total 74277956 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063 +system.cpu.dcache.ReadReq_miss_rate::total 0.063063 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984 +system.cpu.dcache.WriteReq_miss_rate::total 0.002984 +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 +system.cpu.dcache.demand_miss_rate::total 0.037633 +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 +system.cpu.dcache.overall_miss_rate::total 0.037633 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924 +system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743 +system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982 +system.cpu.dcache.demand_avg_miss_latency::total 12747.055982 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982 +system.cpu.dcache.overall_avg_miss_latency::total 12747.055982 +system.cpu.dcache.blocked_cycles::no_mshrs 219709 +system.cpu.dcache.blocked_cycles::no_targets 682 +system.cpu.dcache.blocked::no_mshrs 43158 +system.cpu.dcache.blocked::no_targets 6 +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806 +system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667 +system.cpu.dcache.writebacks::writebacks 2066902 +system.cpu.dcache.writebacks::total 2066902 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827 +system.cpu.dcache.ReadReq_mshr_hits::total 705827 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900 +system.cpu.dcache.WriteReq_mshr_hits::total 11900 +system.cpu.dcache.demand_mshr_hits::cpu.data 717727 +system.cpu.dcache.demand_mshr_hits::total 717727 +system.cpu.dcache.overall_mshr_hits::cpu.data 717727 +system.cpu.dcache.overall_mshr_hits::total 717727 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694 +system.cpu.dcache.ReadReq_mshr_misses::total 1995694 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911 +system.cpu.dcache.WriteReq_mshr_misses::total 81911 +system.cpu.dcache.demand_mshr_misses::cpu.data 2077605 +system.cpu.dcache.demand_mshr_misses::total 2077605 +system.cpu.dcache.overall_mshr_misses::cpu.data 2077605 +system.cpu.dcache.overall_mshr_misses::total 2077605 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3020316491 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3020316491 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27293249991 +system.cpu.dcache.demand_mshr_miss_latency::total 27293249991 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27293249991 +system.cpu.dcache.overall_mshr_miss_latency::total 27293249991 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046587 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046587 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002605 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002605 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027971 +system.cpu.dcache.demand_mshr_miss_rate::total 0.027971 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027971 +system.cpu.dcache.overall_mshr_miss_rate::total 0.027971 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.652942 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.652942 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36873.148796 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36873.148796 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13136.881164 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13136.881164 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13136.881164 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13136.881164 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.icache.tags.replacements 86 +system.cpu.icache.tags.tagsinuse 865.699388 +system.cpu.icache.tags.total_refs 29658716 +system.cpu.icache.tags.sampled_refs 1101 +system.cpu.icache.tags.avg_refs 26937.980018 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 865.699388 +system.cpu.icache.tags.occ_percent::cpu.inst 0.422705 +system.cpu.icache.tags.occ_percent::total 0.422705 +system.cpu.icache.tags.occ_task_id_blocks::1024 1015 +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 +system.cpu.icache.tags.age_task_id_blocks_1024::3 35 +system.cpu.icache.tags.age_task_id_blocks_1024::4 900 +system.cpu.icache.tags.occ_task_id_percent::1024 0.495605 +system.cpu.icache.tags.tag_accesses 59321439 +system.cpu.icache.tags.data_accesses 59321439 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.icache.ReadReq_hits::cpu.inst 29658716 +system.cpu.icache.ReadReq_hits::total 29658716 +system.cpu.icache.demand_hits::cpu.inst 29658716 +system.cpu.icache.demand_hits::total 29658716 +system.cpu.icache.overall_hits::cpu.inst 29658716 +system.cpu.icache.overall_hits::total 29658716 +system.cpu.icache.ReadReq_misses::cpu.inst 1453 +system.cpu.icache.ReadReq_misses::total 1453 +system.cpu.icache.demand_misses::cpu.inst 1453 +system.cpu.icache.demand_misses::total 1453 +system.cpu.icache.overall_misses::cpu.inst 1453 +system.cpu.icache.overall_misses::total 1453 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 154504998 +system.cpu.icache.ReadReq_miss_latency::total 154504998 +system.cpu.icache.demand_miss_latency::cpu.inst 154504998 +system.cpu.icache.demand_miss_latency::total 154504998 +system.cpu.icache.overall_miss_latency::cpu.inst 154504998 +system.cpu.icache.overall_miss_latency::total 154504998 +system.cpu.icache.ReadReq_accesses::cpu.inst 29660169 +system.cpu.icache.ReadReq_accesses::total 29660169 +system.cpu.icache.demand_accesses::cpu.inst 29660169 +system.cpu.icache.demand_accesses::total 29660169 +system.cpu.icache.overall_accesses::cpu.inst 29660169 +system.cpu.icache.overall_accesses::total 29660169 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 +system.cpu.icache.ReadReq_miss_rate::total 0.000049 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 +system.cpu.icache.demand_miss_rate::total 0.000049 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 +system.cpu.icache.overall_miss_rate::total 0.000049 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 106335.167240 +system.cpu.icache.ReadReq_avg_miss_latency::total 106335.167240 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 106335.167240 +system.cpu.icache.demand_avg_miss_latency::total 106335.167240 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 106335.167240 +system.cpu.icache.overall_avg_miss_latency::total 106335.167240 +system.cpu.icache.blocked_cycles::no_mshrs 4008 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 17 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs 235.764706 +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 86 +system.cpu.icache.writebacks::total 86 +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 352 +system.cpu.icache.ReadReq_mshr_hits::total 352 +system.cpu.icache.demand_mshr_hits::cpu.inst 352 +system.cpu.icache.demand_mshr_hits::total 352 +system.cpu.icache.overall_mshr_hits::cpu.inst 352 +system.cpu.icache.overall_mshr_hits::total 352 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1101 +system.cpu.icache.ReadReq_mshr_misses::total 1101 +system.cpu.icache.demand_mshr_misses::cpu.inst 1101 +system.cpu.icache.demand_mshr_misses::total 1101 +system.cpu.icache.overall_mshr_misses::cpu.inst 1101 +system.cpu.icache.overall_mshr_misses::total 1101 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 113239998 +system.cpu.icache.ReadReq_mshr_miss_latency::total 113239998 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 113239998 +system.cpu.icache.demand_mshr_miss_latency::total 113239998 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 113239998 +system.cpu.icache.overall_mshr_miss_latency::total 113239998 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 +system.cpu.icache.demand_mshr_miss_rate::total 0.000037 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 +system.cpu.icache.overall_mshr_miss_rate::total 0.000037 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102851.950954 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102851.950954 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102851.950954 +system.cpu.icache.demand_avg_mshr_miss_latency::total 102851.950954 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102851.950954 +system.cpu.icache.overall_avg_mshr_miss_latency::total 102851.950954 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.l2cache.tags.replacements 680 +system.cpu.l2cache.tags.tagsinuse 21650.115816 +system.cpu.l2cache.tags.total_refs 4121613 +system.cpu.l2cache.tags.sampled_refs 30665 +system.cpu.l2cache.tags.avg_refs 134.407729 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::writebacks 3.138386 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 704.921194 +system.cpu.l2cache.tags.occ_blocks::cpu.data 20942.056236 +system.cpu.l2cache.tags.occ_percent::writebacks 0.000096 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021512 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.639101 +system.cpu.l2cache.tags.occ_percent::total 0.660709 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29985 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 54 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29640 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915070 +system.cpu.l2cache.tags.tag_accesses 33248889 +system.cpu.l2cache.tags.data_accesses 33248889 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066902 +system.cpu.l2cache.WritebackDirty_hits::total 2066902 +system.cpu.l2cache.WritebackClean_hits::writebacks 86 +system.cpu.l2cache.WritebackClean_hits::total 86 +system.cpu.l2cache.ReadExReq_hits::cpu.data 52946 +system.cpu.l2cache.ReadExReq_hits::total 52946 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 +system.cpu.l2cache.ReadCleanReq_hits::total 26 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995088 +system.cpu.l2cache.ReadSharedReq_hits::total 1995088 +system.cpu.l2cache.demand_hits::cpu.inst 26 +system.cpu.l2cache.demand_hits::cpu.data 2048034 +system.cpu.l2cache.demand_hits::total 2048060 +system.cpu.l2cache.overall_hits::cpu.inst 26 +system.cpu.l2cache.overall_hits::cpu.data 2048034 +system.cpu.l2cache.overall_hits::total 2048060 +system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 +system.cpu.l2cache.ReadExReq_misses::total 28996 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1075 +system.cpu.l2cache.ReadCleanReq_misses::total 1075 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 575 +system.cpu.l2cache.ReadSharedReq_misses::total 575 +system.cpu.l2cache.demand_misses::cpu.inst 1075 +system.cpu.l2cache.demand_misses::cpu.data 29571 +system.cpu.l2cache.demand_misses::total 30646 +system.cpu.l2cache.overall_misses::cpu.inst 1075 +system.cpu.l2cache.overall_misses::cpu.data 29571 +system.cpu.l2cache.overall_misses::total 30646 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2341147500 +system.cpu.l2cache.ReadExReq_miss_latency::total 2341147500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 111300000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 111300000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 88414500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 88414500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 111300000 +system.cpu.l2cache.demand_miss_latency::cpu.data 2429562000 +system.cpu.l2cache.demand_miss_latency::total 2540862000 +system.cpu.l2cache.overall_miss_latency::cpu.inst 111300000 +system.cpu.l2cache.overall_miss_latency::cpu.data 2429562000 +system.cpu.l2cache.overall_miss_latency::total 2540862000 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066902 +system.cpu.l2cache.WritebackDirty_accesses::total 2066902 +system.cpu.l2cache.WritebackClean_accesses::writebacks 86 +system.cpu.l2cache.WritebackClean_accesses::total 86 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81942 +system.cpu.l2cache.ReadExReq_accesses::total 81942 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1101 +system.cpu.l2cache.ReadCleanReq_accesses::total 1101 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995663 +system.cpu.l2cache.ReadSharedReq_accesses::total 1995663 +system.cpu.l2cache.demand_accesses::cpu.inst 1101 +system.cpu.l2cache.demand_accesses::cpu.data 2077605 +system.cpu.l2cache.demand_accesses::total 2078706 +system.cpu.l2cache.overall_accesses::cpu.inst 1101 +system.cpu.l2cache.overall_accesses::cpu.data 2077605 +system.cpu.l2cache.overall_accesses::total 2078706 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353860 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353860 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233 +system.cpu.l2cache.demand_miss_rate::total 0.014743 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233 +system.cpu.l2cache.overall_miss_rate::total 0.014743 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178 +system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178 +system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.writebacks::writebacks 299 +system.cpu.l2cache.writebacks::total 299 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075 +system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 +system.cpu.l2cache.demand_mshr_misses::total 30646 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075 +system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 +system.cpu.l2cache.overall_mshr_misses::total 30646 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000 +system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000 +system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830 +system.cpu.toL2Bus.snoop_filter.tot_requests 4152301 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23 +system.cpu.toL2Bus.snoop_filter.tot_snoops 330 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.toL2Bus.trans_dist::ReadResp 1996764 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201 +system.cpu.toL2Bus.trans_dist::WritebackClean 86 +system.cpu.toL2Bus.trans_dist::CleanEvict 6988 +system.cpu.toL2Bus.trans_dist::ReadExReq 81942 +system.cpu.toL2Bus.trans_dist::ReadExResp 81942 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719 +system.cpu.toL2Bus.pkt_count::total 6231007 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448 +system.cpu.toL2Bus.pkt_size::total 265324416 +system.cpu.toL2Bus.snoops 680 +system.cpu.toL2Bus.snoopTraffic 19136 +system.cpu.toL2Bus.snoop_fanout::samples 2079386 +system.cpu.toL2Bus.snoop_fanout::mean 0.000170 +system.cpu.toL2Bus.snoop_fanout::stdev 0.013047 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98% +system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 2079386 +system.cpu.toL2Bus.reqLayer0.occupancy 4143138500 +system.cpu.toL2Bus.reqLayer0.utilization 6.3 +system.cpu.toL2Bus.respLayer0.occupancy 1652498 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 3116407500 +system.cpu.toL2Bus.respLayer1.utilization 4.7 +system.membus.snoop_filter.tot_requests 30996 +system.membus.snoop_filter.hit_single_requests 350 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.membus.trans_dist::ReadResp 1650 +system.membus.trans_dist::WritebackDirty 299 +system.membus.trans_dist::CleanEvict 51 +system.membus.trans_dist::ReadExReq 28996 +system.membus.trans_dist::ReadExResp 28996 +system.membus.trans_dist::ReadSharedReq 1650 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642 +system.membus.pkt_count::total 61642 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480 +system.membus.pkt_size::total 1980480 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 30646 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 30646 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 30646 +system.membus.reqLayer0.occupancy 43591500 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 161486250 +system.membus.respLayer1.utilization 0.2 ---------- End Simulation Statistics ---------- |