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authorNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
commit9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch)
tree64b85031cb791a21af6059778384d358d992b817 /tests/long/se/10.mcf/ref/x86/linux/o3-timing
parentdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff)
downloadgem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux/o3-timing')
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini39
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt27
3 files changed, 41 insertions, 33 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index e9db1ff8f..c87784f11 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -514,9 +519,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index 83aadb6fc..3f08953e4 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 22:18:55
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:36:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 73afa61c1..860f57b09 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.065983 # Nu
sim_ticks 65982862500 # Number of ticks simulated
final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123083 # Simulator instruction rate (inst/s)
-host_op_rate 216729 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51404636 # Simulator tick rate (ticks/s)
-host_mem_usage 379576 # Number of bytes of host memory used
-host_seconds 1283.60 # Real time elapsed on the host
+host_inst_rate 72483 # Simulator instruction rate (inst/s)
+host_op_rate 127630 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 30271870 # Simulator tick rate (ticks/s)
+host_mem_usage 430980 # Number of bytes of host memory used
+host_seconds 2179.68 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
@@ -192,18 +192,19 @@ system.physmem.writeRowHits 45 # Nu
system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
system.physmem.avgGap 2155034.39 # Average gap between requests
+system.cpu.branchPred.lookups 34537566 # Number of BP lookups
+system.cpu.branchPred.condPredicted 34537566 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 909846 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 24744786 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 24642661 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.587287 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 131965726 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 34537566 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 34537566 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 909846 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 24744786 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 24642661 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed
system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered