diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | 453 |
1 files changed, 233 insertions, 220 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 02993075a..d40f8a71c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365989065500 # Number of ticks simulated -final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 365988859500 # Number of ticks simulated +final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 678113 # Simulator instruction rate (inst/s) -host_op_rate 1194048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1570885616 # Simulator tick rate (ticks/s) -host_mem_usage 451452 # Number of bytes of host memory used -host_seconds 232.98 # Real time elapsed on the host +host_inst_rate 643347 # Simulator instruction rate (inst/s) +host_op_rate 1132831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1490347920 # Simulator tick rate (ticks/s) +host_mem_usage 451472 # Number of bytes of host memory used +host_seconds 245.57 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory -system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory +system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory -system.physmem.bytes_written::total 6400 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory +system.physmem.bytes_written::total 6528 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory -system.physmem.num_writes::total 100 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory +system.physmem.num_writes::total 102 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5113336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5253756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5113336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5271592 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731978131 # number of cpu cycles simulated +system.cpu.numCycles 731977719 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles +system.cpu.num_busy_cycles 731977718.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -100,12 +100,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.488591 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 126079705500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488591 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -132,14 +132,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498474000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25498474000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598457000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598457000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28096931000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28096931000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28096931000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28096931000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -156,14 +156,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.648292 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.648292 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.563647 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.563647 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13594.221389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13594.221389 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -172,8 +172,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks -system.cpu.dcache.writebacks::total 2062484 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks +system.cpu.dcache.writebacks::total 2062482 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses @@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23537754000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23537754000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492348000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492348000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26030102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26030102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26030102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26030102000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -198,22 +198,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12004.648292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12004.648292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23488.563647 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23488.563647 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.632473 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632473 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44233500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44233500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44233500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44233500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44233500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44233500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54744.430693 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54744.430693 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54744.430693 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54744.430693 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -273,117 +273,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43425500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43425500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43425500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43425500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43425500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43425500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 19329.043320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.394677 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 156.453912 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589876 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 2062482 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2062482 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2037588 # 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number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # 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miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1233551000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1233551000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34129500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34129500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9222500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9222500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1242773500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1276903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34129500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1242773500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1276903000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.490660 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.490660 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 313 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.000076 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.008704 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4130121 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4130394 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 313 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1025 # Transaction distribution -system.membus.trans_dist::ReadResp 1025 # Transaction distribution -system.membus.trans_dist::Writeback 100 # Transaction distribution +system.membus.trans_dist::ReadResp 1020 # Transaction distribution +system.membus.trans_dist::Writeback 102 # Transaction distribution +system.membus.trans_dist::CleanEvict 14 # Transaction distribution system.membus.trans_dist::ReadExReq 29024 # Transaction distribution system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30149 # Request fanout histogram +system.membus.snoop_fanout::samples 30160 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30149 # Request fanout histogram -system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30160 # Request fanout histogram +system.membus.reqLayer0.occupancy 30601000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 150253000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |