stats: update stats for insts/ops and master id changes

1 files changed, 233 insertions, 150 deletions

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 59ae818d2..a57ebe258 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds                                  0.370011                       # Nu
 sim_ticks                                370010840000                       # Number of ticks simulated
 final_tick                               370010840000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1163147                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1547047043                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 348152                       # Number of bytes of host memory used
-host_seconds                                   239.17                       # Real time elapsed on the host
-sim_insts                                   278192520                       # Number of instructions simulated
+host_inst_rate                                 912216                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1606265                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2136418129                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 353708                       # Number of bytes of host memory used
+host_seconds                                   173.19                       # Real time elapsed on the host
+sim_insts                                   157988583                       # Number of instructions simulated
+sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     4900800                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  51712                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  1885440                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  444                       # Nu
 system.cpu.numCycles                        740021680                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        278192520                       # Number of instructions executed
+system.cpu.committedInsts                   157988583                       # Number of instructions committed
+system.cpu.committedOps                     278192520                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs                217695401                       # To
 system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               269425.001238                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            666.191948                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.325289                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              217695401                       # number of ReadReq hits
-system.cpu.icache.demand_hits               217695401                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              217695401                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  808                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   808                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  808                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       45248000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        45248000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       45248000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          217696209                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           217696209                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          217696209                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     666.191948                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.325289                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.325289                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    217695401                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       217695401                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     217695401                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        217695401                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    217695401                       # number of overall hits
+system.cpu.icache.overall_hits::total       217695401                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          808                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           808                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          808                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            808                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          808                       # number of overall misses
+system.cpu.icache.overall_misses::total           808                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     45248000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     45248000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     45248000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     45248000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     45248000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     45248000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    217696209                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    217696209                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    217696209                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    217696209                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    217696209                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    217696209                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             808                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              808                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             808                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     42824000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     42824000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     42824000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          808                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          808                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42824000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42824000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42824000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42824000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42824000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42824000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2062733                       # number of replacements
 system.cpu.dcache.tagsinuse               4076.661903                       # Cycle average of tags in use
@@ -102,32 +116,49 @@ system.cpu.dcache.total_refs                120152372                       # To
 system.cpu.dcache.sampled_refs                2066829                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  58.133678                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle           126200130000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4076.661903                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995279                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               88818730                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              31333642                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               120152372                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              120152372                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1960720                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              106109                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2066829                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2066829                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    28849058000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    3268793000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     32117851000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    32117851000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           90779450                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           122219201                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          122219201                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.021599                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.003375                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.016911                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.016911                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 15539.675029                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 15539.675029                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4076.661903                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     88818730                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88818730                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31333642                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31333642                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     120152372                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        120152372                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    120152372                       # number of overall hits
+system.cpu.dcache.overall_hits::total       120152372                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1960720                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1960720                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       106109                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       106109                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2066829                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2066829                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2066829                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2066829                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  28849058000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  28849058000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3268793000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3268793000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  32117851000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32117851000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  32117851000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32117851000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     90779450                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     90779450                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    122219201                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    122219201                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    122219201                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    122219201                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021599                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003375                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016911                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.016911                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1437080                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1960720                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         106109                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2066829                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2066829                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  22966898000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2950464500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  25917362500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  25917362500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.021599                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003375                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.016911                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.016911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      1437080                       # number of writebacks
+system.cpu.dcache.writebacks::total           1437080                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1960720                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1960720                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       106109                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       106109                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2066829                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2066829                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2066829                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2066829                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  22966898000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  22966898000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2950464500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2950464500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25917362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25917362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  25917362500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  25917362500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.021599                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003375                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 49212                       # number of replacements
 system.cpu.l2cache.tagsinuse             18614.603260                       # Cycle average of tags in use
@@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs                 3296079                       # To
 system.cpu.l2cache.sampled_refs                 77127                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 42.735735                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          6551.798271                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12062.804989                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.199945                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.368128                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1927411                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1437080                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               63651                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1991062                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1991062                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               34117                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             42458                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                76575                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               76575                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1774084000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2207845500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3981929500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3981929500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1961528                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1437080                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          106109                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2067637                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2067637                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.017393                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.400136                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.037035                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.037035                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000.385243                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000.385243                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 12062.804989                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    196.794797                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   6355.003474                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.368128                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.006006                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.193939                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.568073                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      1927411                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1927411                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1437080                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1437080                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        63651                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        63651                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      1991062                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1991062                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      1991062                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1991062                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          808                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        33309                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        34117                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        42458                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        42458                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          808                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        75767                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         76575                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          808                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        75767                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        76575                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     42016000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1732068000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1774084000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2207845500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2207845500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     42016000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3939913500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3981929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     42016000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3939913500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3981929500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          808                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1960720                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1961528                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1437080                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1437080                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       106109                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       106109                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          808                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2066829                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2067637                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          808                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2066829                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2067637                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.016988                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.400136                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.036659                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.036659                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   29460                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          34117                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        42458                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           76575                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          76575                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1364680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1698320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   3063000000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   3063000000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017393                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.400136                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.037035                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.037035                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        29460                       # number of writebacks
+system.cpu.l2cache.writebacks::total            29460                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        33309                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        34117                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        42458                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        42458                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          808                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        75767                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        76575                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        75767                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        76575                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     32320000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1332360000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1364680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1698320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1698320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     32320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3030680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3063000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     32320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3030680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3063000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.016988                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.400136                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.036659                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.036659                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------