diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | 1074 |
1 files changed, 537 insertions, 537 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 957a0aa1f..275d179a2 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,541 +1,541 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366229 # Number of seconds simulated -sim_ticks 366229314500 # Number of ticks simulated -final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1002365 # Simulator instruction rate (inst/s) -host_op_rate 1765004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2323557450 # Simulator tick rate (ticks/s) -host_mem_usage 412036 # Number of bytes of host memory used -host_seconds 157.62 # Real time elapsed on the host -sim_insts 157988548 # Number of instructions simulated -sim_ops 278192465 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory -system.physmem.bytes_read::total 1922944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory -system.physmem.bytes_written::total 6656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30046 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732458629 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_func_calls 8475189 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278169482 # number of integer instructions -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read -system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read -system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written -system.cpu.num_mem_refs 122219137 # number of memory refs -system.cpu.num_load_insts 90779385 # Number of load instructions -system.cpu.num_store_insts 31439752 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29309705 # Number of branches fetched -system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction -system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 278192465 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits -system.cpu.dcache.overall_hits::total 120152370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses -system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25500310500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2830649000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28330959500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28330959500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28330959500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28330959500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13707.452092 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13707.452092 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks -system.cpu.dcache.writebacks::total 2062482 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26264130500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26264130500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.626582 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.626582 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses -system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits -system.cpu.icache.overall_hits::total 217695356 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses -system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50660000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50660000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50660000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50660000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50660000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62698.019802 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62698.019802 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24 # number of writebacks -system.cpu.icache.writebacks::total 24 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49852000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49852000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49852000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 315 # number of replacements -system.cpu.l2cache.tags.tagsinuse 21080.806353 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4100347 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30047 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 136.464439 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.624695 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000019 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.626347 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.643335 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29732 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33073199 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33073199 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1960501 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2037586 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037591 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2037586 # number of overall hits -system.cpu.l2cache.overall_hits::total 2037591 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 219 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 219 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29243 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30046 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29243 # number of overall misses -system.cpu.l2cache.overall_misses::total 30046 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1755983000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48585000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1769232500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1817817500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 48585000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1769232500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1817817500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014532 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014532 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks -system.cpu.l2cache.writebacks::total 104 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29243 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29243 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30046 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 315 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6656 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2067952 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2067952 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 30164 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 118 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1022 # Transaction distribution -system.membus.trans_dist::WritebackDirty 104 # Transaction distribution -system.membus.trans_dist::CleanEvict 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 29024 # Transaction distribution -system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1022 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60210 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929600 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30046 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30046 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30046 # Request fanout histogram -system.membus.reqLayer0.occupancy 30614500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150230000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.366229 +sim_ticks 366229314500 +final_tick 366229314500 +sim_freq 1000000000000 +host_inst_rate 440271 +host_op_rate 775247 +host_tick_rate 1020581695 +host_mem_usage 422392 +host_seconds 358.84 +sim_insts 157988548 +sim_ops 278192465 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.physmem.bytes_read::cpu.inst 51392 +system.physmem.bytes_read::cpu.data 1871552 +system.physmem.bytes_read::total 1922944 +system.physmem.bytes_inst_read::cpu.inst 51392 +system.physmem.bytes_inst_read::total 51392 +system.physmem.bytes_written::writebacks 6656 +system.physmem.bytes_written::total 6656 +system.physmem.num_reads::cpu.inst 803 +system.physmem.num_reads::cpu.data 29243 +system.physmem.num_reads::total 30046 +system.physmem.num_writes::writebacks 104 +system.physmem.num_writes::total 104 +system.physmem.bw_read::cpu.inst 140327 +system.physmem.bw_read::cpu.data 5110328 +system.physmem.bw_read::total 5250656 +system.physmem.bw_inst_read::cpu.inst 140327 +system.physmem.bw_inst_read::total 140327 +system.physmem.bw_write::writebacks 18174 +system.physmem.bw_write::total 18174 +system.physmem.bw_total::writebacks 18174 +system.physmem.bw_total::cpu.inst 140327 +system.physmem.bw_total::cpu.data 5110328 +system.physmem.bw_total::total 5268830 +system.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.workload.numSyscalls 444 +system.cpu.pwrStateResidencyTicks::ON 366229314500 +system.cpu.numCycles 732458629 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 157988548 +system.cpu.committedOps 278192465 +system.cpu.num_int_alu_accesses 278169482 +system.cpu.num_fp_alu_accesses 40 +system.cpu.num_func_calls 8475189 +system.cpu.num_conditional_control_insts 18628007 +system.cpu.num_int_insts 278169482 +system.cpu.num_fp_insts 40 +system.cpu.num_int_register_reads 635379407 +system.cpu.num_int_register_writes 217447860 +system.cpu.num_fp_register_reads 40 +system.cpu.num_fp_register_writes 26 +system.cpu.num_cc_register_reads 104140596 +system.cpu.num_cc_register_writes 61764861 +system.cpu.num_mem_refs 122219137 +system.cpu.num_load_insts 90779385 +system.cpu.num_store_insts 31439752 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 732458629 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 29309705 +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% +system.cpu.op_class::IntMult 10938 0.00% 56.07% +system.cpu.op_class::IntDiv 329 0.00% 56.07% +system.cpu.op_class::FloatAdd 12 0.00% 56.07% +system.cpu.op_class::FloatCmp 0 0.00% 56.07% +system.cpu.op_class::FloatCvt 0 0.00% 56.07% +system.cpu.op_class::FloatMult 0 0.00% 56.07% +system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% +system.cpu.op_class::FloatDiv 0 0.00% 56.07% +system.cpu.op_class::FloatMisc 0 0.00% 56.07% +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% +system.cpu.op_class::SimdAdd 0 0.00% 56.07% +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% +system.cpu.op_class::SimdAlu 0 0.00% 56.07% +system.cpu.op_class::SimdCmp 0 0.00% 56.07% +system.cpu.op_class::SimdCvt 0 0.00% 56.07% +system.cpu.op_class::SimdMisc 0 0.00% 56.07% +system.cpu.op_class::SimdMult 0 0.00% 56.07% +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% +system.cpu.op_class::SimdShift 0 0.00% 56.07% +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% +system.cpu.op_class::MemRead 90779371 32.63% 88.70% +system.cpu.op_class::MemWrite 31439738 11.30% 100.00% +system.cpu.op_class::FloatMemRead 14 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 278192465 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.dcache.tags.replacements 2062733 +system.cpu.dcache.tags.tagsinuse 4076.272883 +system.cpu.dcache.tags.total_refs 120152370 +system.cpu.dcache.tags.sampled_refs 2066829 +system.cpu.dcache.tags.avg_refs 58.133677 +system.cpu.dcache.tags.warmup_cycle 126128435500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 +system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 +system.cpu.dcache.tags.occ_percent::total 0.995184 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 246505227 +system.cpu.dcache.tags.data_accesses 246505227 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.dcache.ReadReq_hits::cpu.data 88818727 +system.cpu.dcache.ReadReq_hits::total 88818727 +system.cpu.dcache.WriteReq_hits::cpu.data 31333643 +system.cpu.dcache.WriteReq_hits::total 31333643 +system.cpu.dcache.demand_hits::cpu.data 120152370 +system.cpu.dcache.demand_hits::total 120152370 +system.cpu.dcache.overall_hits::cpu.data 120152370 +system.cpu.dcache.overall_hits::total 120152370 +system.cpu.dcache.ReadReq_misses::cpu.data 1960720 +system.cpu.dcache.ReadReq_misses::total 1960720 +system.cpu.dcache.WriteReq_misses::cpu.data 106109 +system.cpu.dcache.WriteReq_misses::total 106109 +system.cpu.dcache.demand_misses::cpu.data 2066829 +system.cpu.dcache.demand_misses::total 2066829 +system.cpu.dcache.overall_misses::cpu.data 2066829 +system.cpu.dcache.overall_misses::total 2066829 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 +system.cpu.dcache.ReadReq_miss_latency::total 25500310500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 +system.cpu.dcache.WriteReq_miss_latency::total 2830649000 +system.cpu.dcache.demand_miss_latency::cpu.data 28330959500 +system.cpu.dcache.demand_miss_latency::total 28330959500 +system.cpu.dcache.overall_miss_latency::cpu.data 28330959500 +system.cpu.dcache.overall_miss_latency::total 28330959500 +system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 +system.cpu.dcache.ReadReq_accesses::total 90779447 +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 +system.cpu.dcache.WriteReq_accesses::total 31439752 +system.cpu.dcache.demand_accesses::cpu.data 122219199 +system.cpu.dcache.demand_accesses::total 122219199 +system.cpu.dcache.overall_accesses::cpu.data 122219199 +system.cpu.dcache.overall_accesses::total 122219199 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 +system.cpu.dcache.ReadReq_miss_rate::total 0.021599 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 +system.cpu.dcache.WriteReq_miss_rate::total 0.003375 +system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 +system.cpu.dcache.demand_miss_rate::total 0.016911 +system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 +system.cpu.dcache.overall_miss_rate::total 0.016911 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938 +system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 +system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 +system.cpu.dcache.demand_avg_miss_latency::total 13707.452092 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 +system.cpu.dcache.overall_avg_miss_latency::total 13707.452092 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 2062482 +system.cpu.dcache.writebacks::total 2062482 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 +system.cpu.dcache.ReadReq_mshr_misses::total 1960720 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 +system.cpu.dcache.WriteReq_mshr_misses::total 106109 +system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 +system.cpu.dcache.demand_mshr_misses::total 2066829 +system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 +system.cpu.dcache.overall_mshr_misses::total 2066829 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500 +system.cpu.dcache.demand_mshr_miss_latency::total 26264130500 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500 +system.cpu.dcache.overall_mshr_miss_latency::total 26264130500 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 +system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 +system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.icache.tags.replacements 24 +system.cpu.icache.tags.tagsinuse 665.626582 +system.cpu.icache.tags.total_refs 217695357 +system.cpu.icache.tags.sampled_refs 808 +system.cpu.icache.tags.avg_refs 269424.946782 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 665.626582 +system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 +system.cpu.icache.tags.occ_percent::total 0.325013 +system.cpu.icache.tags.occ_task_id_blocks::1024 784 +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 +system.cpu.icache.tags.age_task_id_blocks_1024::3 23 +system.cpu.icache.tags.age_task_id_blocks_1024::4 715 +system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 +system.cpu.icache.tags.tag_accesses 435393138 +system.cpu.icache.tags.data_accesses 435393138 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.icache.ReadReq_hits::cpu.inst 217695357 +system.cpu.icache.ReadReq_hits::total 217695357 +system.cpu.icache.demand_hits::cpu.inst 217695357 +system.cpu.icache.demand_hits::total 217695357 +system.cpu.icache.overall_hits::cpu.inst 217695357 +system.cpu.icache.overall_hits::total 217695357 +system.cpu.icache.ReadReq_misses::cpu.inst 808 +system.cpu.icache.ReadReq_misses::total 808 +system.cpu.icache.demand_misses::cpu.inst 808 +system.cpu.icache.demand_misses::total 808 +system.cpu.icache.overall_misses::cpu.inst 808 +system.cpu.icache.overall_misses::total 808 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000 +system.cpu.icache.ReadReq_miss_latency::total 50660000 +system.cpu.icache.demand_miss_latency::cpu.inst 50660000 +system.cpu.icache.demand_miss_latency::total 50660000 +system.cpu.icache.overall_miss_latency::cpu.inst 50660000 +system.cpu.icache.overall_miss_latency::total 50660000 +system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 +system.cpu.icache.ReadReq_accesses::total 217696165 +system.cpu.icache.demand_accesses::cpu.inst 217696165 +system.cpu.icache.demand_accesses::total 217696165 +system.cpu.icache.overall_accesses::cpu.inst 217696165 +system.cpu.icache.overall_accesses::total 217696165 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 +system.cpu.icache.ReadReq_miss_rate::total 0.000004 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 +system.cpu.icache.demand_miss_rate::total 0.000004 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 +system.cpu.icache.overall_miss_rate::total 0.000004 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802 +system.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 +system.cpu.icache.demand_avg_miss_latency::total 62698.019802 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 +system.cpu.icache.overall_avg_miss_latency::total 62698.019802 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 24 +system.cpu.icache.writebacks::total 24 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 +system.cpu.icache.ReadReq_mshr_misses::total 808 +system.cpu.icache.demand_mshr_misses::cpu.inst 808 +system.cpu.icache.demand_mshr_misses::total 808 +system.cpu.icache.overall_mshr_misses::cpu.inst 808 +system.cpu.icache.overall_mshr_misses::total 808 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000 +system.cpu.icache.ReadReq_mshr_miss_latency::total 49852000 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000 +system.cpu.icache.demand_mshr_miss_latency::total 49852000 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000 +system.cpu.icache.overall_mshr_miss_latency::total 49852000 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802 +system.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802 +system.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.l2cache.tags.replacements 315 +system.cpu.l2cache.tags.tagsinuse 21080.806353 +system.cpu.l2cache.tags.total_refs 4100347 +system.cpu.l2cache.tags.sampled_refs 30047 +system.cpu.l2cache.tags.avg_refs 136.464439 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::writebacks 0.624695 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540 +system.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118 +system.cpu.l2cache.tags.occ_percent::writebacks 0.000019 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.626347 +system.cpu.l2cache.tags.occ_percent::total 0.643335 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29732 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 +system.cpu.l2cache.tags.tag_accesses 33073199 +system.cpu.l2cache.tags.data_accesses 33073199 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 +system.cpu.l2cache.WritebackDirty_hits::total 2062482 +system.cpu.l2cache.WritebackClean_hits::writebacks 24 +system.cpu.l2cache.WritebackClean_hits::total 24 +system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 +system.cpu.l2cache.ReadExReq_hits::total 77085 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 +system.cpu.l2cache.ReadCleanReq_hits::total 5 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501 +system.cpu.l2cache.ReadSharedReq_hits::total 1960501 +system.cpu.l2cache.demand_hits::cpu.inst 5 +system.cpu.l2cache.demand_hits::cpu.data 2037586 +system.cpu.l2cache.demand_hits::total 2037591 +system.cpu.l2cache.overall_hits::cpu.inst 5 +system.cpu.l2cache.overall_hits::cpu.data 2037586 +system.cpu.l2cache.overall_hits::total 2037591 +system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 +system.cpu.l2cache.ReadExReq_misses::total 29024 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 +system.cpu.l2cache.ReadCleanReq_misses::total 803 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 219 +system.cpu.l2cache.ReadSharedReq_misses::total 219 +system.cpu.l2cache.demand_misses::cpu.inst 803 +system.cpu.l2cache.demand_misses::cpu.data 29243 +system.cpu.l2cache.demand_misses::total 30046 +system.cpu.l2cache.overall_misses::cpu.inst 803 +system.cpu.l2cache.overall_misses::cpu.data 29243 +system.cpu.l2cache.overall_misses::total 30046 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000 +system.cpu.l2cache.ReadExReq_miss_latency::total 1755983000 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 48585000 +system.cpu.l2cache.demand_miss_latency::cpu.data 1769232500 +system.cpu.l2cache.demand_miss_latency::total 1817817500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 48585000 +system.cpu.l2cache.overall_miss_latency::cpu.data 1769232500 +system.cpu.l2cache.overall_miss_latency::total 1817817500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 +system.cpu.l2cache.WritebackDirty_accesses::total 2062482 +system.cpu.l2cache.WritebackClean_accesses::writebacks 24 +system.cpu.l2cache.WritebackClean_accesses::total 24 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 +system.cpu.l2cache.ReadExReq_accesses::total 106109 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 +system.cpu.l2cache.ReadCleanReq_accesses::total 808 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 +system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 +system.cpu.l2cache.demand_accesses::cpu.inst 808 +system.cpu.l2cache.demand_accesses::cpu.data 2066829 +system.cpu.l2cache.demand_accesses::total 2067637 +system.cpu.l2cache.overall_accesses::cpu.inst 808 +system.cpu.l2cache.overall_accesses::cpu.data 2066829 +system.cpu.l2cache.overall_accesses::total 2067637 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 +system.cpu.l2cache.demand_miss_rate::total 0.014532 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 +system.cpu.l2cache.overall_miss_rate::total 0.014532 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 +system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 +system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.writebacks::writebacks 104 +system.cpu.l2cache.writebacks::total 104 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 +system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 +system.cpu.l2cache.demand_mshr_misses::cpu.data 29243 +system.cpu.l2cache.demand_mshr_misses::total 30046 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 +system.cpu.l2cache.overall_mshr_misses::cpu.data 29243 +system.cpu.l2cache.overall_mshr_misses::total 30046 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 +system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 +system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 +system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 197 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.cpu.toL2Bus.trans_dist::ReadResp 1961528 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 +system.cpu.toL2Bus.trans_dist::WritebackClean 24 +system.cpu.toL2Bus.trans_dist::CleanEvict 462 +system.cpu.toL2Bus.trans_dist::ReadExReq 106109 +system.cpu.toL2Bus.trans_dist::ReadExResp 106109 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 +system.cpu.toL2Bus.pkt_count::total 6198031 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 +system.cpu.toL2Bus.pkt_size::total 264329152 +system.cpu.toL2Bus.snoops 315 +system.cpu.toL2Bus.snoopTraffic 6656 +system.cpu.toL2Bus.snoop_fanout::samples 2067952 +system.cpu.toL2Bus.snoop_fanout::mean 0.000095 +system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% +system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 2067952 +system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 +system.cpu.toL2Bus.reqLayer0.utilization 1.1 +system.cpu.toL2Bus.respLayer0.occupancy 1212000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 3100243500 +system.cpu.toL2Bus.respLayer1.utilization 0.8 +system.membus.snoop_filter.tot_requests 30164 +system.membus.snoop_filter.hit_single_requests 118 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.membus.trans_dist::ReadResp 1022 +system.membus.trans_dist::WritebackDirty 104 +system.membus.trans_dist::CleanEvict 14 +system.membus.trans_dist::ReadExReq 29024 +system.membus.trans_dist::ReadExResp 29024 +system.membus.trans_dist::ReadSharedReq 1022 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 +system.membus.pkt_count::total 60210 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 +system.membus.pkt_size::total 1929600 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 30046 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 30046 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 30046 +system.membus.reqLayer0.occupancy 30614500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 150230000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- |