summaryrefslogtreecommitdiff
path: root/tests/long/se/10.mcf/ref/x86/linux/simple-timing
diff options
context:
space:
mode:
authorSteve Reinhardt <steve.reinhardt@amd.com>2013-10-16 10:44:12 -0400
committerSteve Reinhardt <steve.reinhardt@amd.com>2013-10-16 10:44:12 -0400
commit10e64501206b72901c266855fde2909523b875e0 (patch)
treedf5db553cf78ff00467b4ca87614a5721439b2ec /tests/long/se/10.mcf/ref/x86/linux/simple-timing
parentb10ff075b102b2a2e4abf5d22735b919a8fda1a9 (diff)
downloadgem5-10e64501206b72901c266855fde2909523b875e0.tar.xz
test: update stats
Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux/simple-timing')
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt20
2 files changed, 13 insertions, 13 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 2c70ca6cf..033910815 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 22 2013 06:21:20
-gem5 started Sep 22 2013 06:32:00
+gem5 compiled Oct 16 2013 01:35:57
+gem5 started Oct 16 2013 01:48:06
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 2b38a25ba..fa71cbd3c 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
sim_ticks 365989065000 # Number of ticks simulated
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 324809 # Simulator instruction rate (inst/s)
-host_op_rate 571936 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 752437231 # Simulator tick rate (ticks/s)
-host_mem_usage 382748 # Number of bytes of host memory used
-host_seconds 486.40 # Real time elapsed on the host
+host_inst_rate 746941 # Simulator instruction rate (inst/s)
+host_op_rate 1315244 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1730329772 # Simulator tick rate (ticks/s)
+host_mem_usage 386536 # Number of bytes of host memory used
+host_seconds 211.51 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
@@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
+system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 8475189 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278186175 # number of integer instructions
+system.cpu.num_int_insts 278169482 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read
-system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written
+system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
+system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions