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authorSteve Reinhardt <steve.reinhardt@amd.com>2016-03-17 10:30:58 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2016-03-17 10:30:58 -0700
commit4fc69db8f89049a881a5f4aa68545840818b124c (patch)
tree7388f5b2755f6f4937b7ce9b8ba889f0d48bc403 /tests/long/se/10.mcf/ref/x86/linux
parentdbad391a9b4e861fd3d660069ed448db85144e17 (diff)
downloadgem5-4fc69db8f89049a881a5f4aa68545840818b124c.tar.xz
stats: update stats for mmap changes
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux')
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt360
2 files changed, 183 insertions, 183 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index 4c5d4c468..072ce04c3 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 15 2016 19:39:16
-gem5 started Mar 15 2016 19:40:29
-gem5 executing on dinar2c11, pid 3692
+gem5 compiled Mar 16 2016 15:38:19
+gem5 started Mar 16 2016 15:38:47
+gem5 executing on dinar2c11, pid 14352
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 19e7a4fbe..63290598f 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -4,46 +4,46 @@ sim_seconds 0.061602 # Nu
sim_ticks 61602281500 # Number of ticks simulated
final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59652 # Simulator instruction rate (inst/s)
-host_op_rate 105038 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23259273 # Simulator tick rate (ticks/s)
-host_mem_usage 445096 # Number of bytes of host memory used
-host_seconds 2648.50 # Real time elapsed on the host
+host_inst_rate 60207 # Simulator instruction rate (inst/s)
+host_op_rate 106015 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 23475786 # Simulator tick rate (ticks/s)
+host_mem_usage 445092 # Number of bytes of host memory used
+host_seconds 2624.08 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1946944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory
system.physmem.bytes_written::total 12160 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30421 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory
system.physmem.num_writes::total 190 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 30569257 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 31606102 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 30568218 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 31605063 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 30569257 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 31803497 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30422 # Number of read requests accepted
+system.physmem.bw_total::cpu.data 30568218 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 31802458 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 30421 # Number of read requests accepted
system.physmem.writeReqs 190 # Number of write requests accepted
-system.physmem.readBursts 30422 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 30421 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1941504 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 1941440 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue
system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 1947008 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 1946944 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
@@ -57,7 +57,7 @@ system.physmem.perBankRdBursts::5 1901 # Pe
system.physmem.perBankRdBursts::6 1952 # Per bank write bursts
system.physmem.perBankRdBursts::7 1864 # Per bank write bursts
system.physmem.perBankRdBursts::8 1938 # Per bank write bursts
-system.physmem.perBankRdBursts::9 1932 # Per bank write bursts
+system.physmem.perBankRdBursts::9 1931 # Per bank write bursts
system.physmem.perBankRdBursts::10 1804 # Per bank write bursts
system.physmem.perBankRdBursts::11 1794 # Per bank write bursts
system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
@@ -89,7 +89,7 @@ system.physmem.readPktSize::2 0 # Re
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 30422 # Read request sizes (log2)
+system.physmem.readPktSize::6 30421 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -98,7 +98,7 @@ system.physmem.writePktSize::4 0 # Wr
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 190 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
@@ -194,11 +194,11 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 716.489526 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 515.486965 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 387.954881 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 364 13.38% 13.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 231 8.49% 21.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 716.466005 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 515.355667 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 387.992511 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 365 13.41% 13.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 230 8.45% 21.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation
@@ -208,8 +208,8 @@ system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # B
system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 3363.777778 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 10055.709980 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 3363.666667 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 10055.376646 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes
@@ -221,11 +221,11 @@ system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Wr
system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads
system.physmem.totQLat 133021500 # Total ticks spent queuing
-system.physmem.totMemAccLat 701821500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 151680000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 4384.94 # Average queueing delay per DRAM burst
+system.physmem.totMemAccLat 701802750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 151675000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 4385.08 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23134.94 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 23135.08 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s
@@ -236,11 +236,11 @@ system.physmem.busUtilRead 0.25 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing
-system.physmem.readRowHits 27659 # Number of row buffer hits during reads
+system.physmem.readRowHits 27658 # Number of row buffer hits during reads
system.physmem.writeRowHits 106 # Number of row buffer hits during writes
system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes
-system.physmem.avgGap 2012351.25 # Average gap between requests
+system.physmem.avgGap 2012416.99 # Average gap between requests
system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ)
@@ -258,13 +258,13 @@ system.physmem_0.memoryStateTime::ACT 2211196750 # Ti
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy 114199800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 41481574230 # Total energy per rank (pJ)
-system.physmem_1.averagePower 673.432024 # Core power per rank (mW)
+system.physmem_1.totalEnergy 41481566430 # Total energy per rank (pJ)
+system.physmem_1.averagePower 673.431898 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states
system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
@@ -350,7 +350,7 @@ system.cpu.iq.iqNonSpecInstsAdded 2340 # Nu
system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 63882730 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 63882734 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle
@@ -443,7 +443,7 @@ system.cpu.iq.fu_busy_cnt 3969927 # FU
system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 304282659 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses 304282658 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses
@@ -483,8 +483,8 @@ system.cpu.iew.exec_refs 131430384 # nu
system.cpu.iew.exec_branches 31401849 # Number of branches executed
system.cpu.iew.exec_stores 33679798 # Number of stores executed
system.cpu.iew.exec_rate 2.476830 # Inst execution rate
-system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back
+system.cpu.iew.wb_sent 304565843 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 304282791 # cumulative count of insts written-back
system.cpu.iew.wb_producers 230213909 # num instructions producing a value
system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value
system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle
@@ -573,22 +573,22 @@ system.cpu.cc_regfile_reads 107533030 # nu
system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes
system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 2072313 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4068.012890 # Cycle average of tags in use
+system.cpu.dcache.tags.replacements 2072312 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4068.008256 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2076409 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 32.783059 # Average number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2076408 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 32.783074 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012890 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.993167 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.993167 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 4068.008256 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.993166 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.993166 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 143788645 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 143788645 # Number of data accesses
+system.cpu.dcache.tags.tag_accesses 143788642 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 143788642 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits
@@ -597,30 +597,30 @@ system.cpu.dcache.demand_hits::cpu.data 68071037 # nu
system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits
system.cpu.dcache.overall_hits::total 68071037 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2691154 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2691154 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data 2691153 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2691153 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2785081 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2785081 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2785081 # number of overall misses
-system.cpu.dcache.overall_misses::total 2785081 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304267000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 32304267000 # number of ReadReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 2785080 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2785080 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2785080 # number of overall misses
+system.cpu.dcache.overall_misses::total 2785080 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304195500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 32304195500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35260881994 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35260881994 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35260881994 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35260881994 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 39416366 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 39416366 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 35260810494 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 35260810494 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 35260810494 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 35260810494 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 39416365 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 39416365 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 70856118 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 70856118 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 70856118 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 70856118 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 70856117 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 70856117 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 70856117 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 70856117 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses
@@ -629,14 +629,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306
system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.871573 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.871573 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 12660.630694 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked
@@ -655,22 +655,22 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 708671
system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses
@@ -679,14 +679,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305
system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 53 # number of replacements
system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use
@@ -783,27 +783,27 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426
system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 493 # number of replacements
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id
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system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits
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system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses)
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@@ -902,117 +902,117 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856602000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1922339000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856543000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 1922280000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000214 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000213 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66769.953052 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66769.953052 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 4149788 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072369 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1995353 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 6015 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 6014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994339 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225133 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6227214 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225130 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 6227211 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152576 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 265220864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 493 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 2077917 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 2077916 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2077592 99.98% 99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2077591 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2077917 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4141549000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 2077916 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4141548000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3114612500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 1424 # Transaction distribution
+system.membus.trans_dist::ReadResp 1423 # Transaction distribution
system.membus.trans_dist::WritebackDirty 190 # Transaction distribution
system.membus.trans_dist::CleanEvict 24 # Transaction distribution
system.membus.trans_dist::ReadExReq 28998 # Transaction distribution
system.membus.trans_dist::ReadExResp 28998 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1424 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61058 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61058 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 61058 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1959168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 1423 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61056 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61056 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 61056 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1959104 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 30636 # Request fanout histogram
+system.membus.snoop_fanout::samples 30635 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 30636 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 30635 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 30636 # Request fanout histogram
-system.membus.reqLayer0.occupancy 42770500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 30635 # Request fanout histogram
+system.membus.reqLayer0.occupancy 42769000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 160321750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 160316500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------