diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/10.mcf/ref | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/10.mcf/ref')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 601 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1550 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 274 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1407 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | 453 |
5 files changed, 2164 insertions, 2121 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index df256055e..1f83c039b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061296 # Number of seconds simulated -sim_ticks 61295518500 # Number of ticks simulated -final_tick 61295518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061280 # Number of seconds simulated +sim_ticks 61279840500 # Number of ticks simulated +final_tick 61279840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265745 # Simulator instruction rate (inst/s) -host_op_rate 267069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 179784475 # Simulator tick rate (ticks/s) -host_mem_usage 446692 # Number of bytes of host memory used -host_seconds 340.94 # Real time elapsed on the host +host_inst_rate 263178 # Simulator instruction rate (inst/s) +host_op_rate 264489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 178002192 # Simulator tick rate (ticks/s) +host_mem_usage 447788 # Number of bytes of host memory used +host_seconds 344.26 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15453006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16261156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15453006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16261156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15456959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16265316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15456959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16265316 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61295424000 # Total gap between requests +system.physmem.totGap 61279747000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 651.693517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 447.533847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.021267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 238 15.59% 15.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 181 11.85% 27.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 84 5.50% 32.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.45% 37.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 4.65% 42.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 87 5.70% 47.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 52 3.41% 51.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 56 3.67% 54.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 690 45.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation -system.physmem.totQLat 75432750 # Total ticks spent queuing -system.physmem.totMemAccLat 367445250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 650.032658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 444.829113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 399.661041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 243 15.87% 15.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 12.15% 28.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 73 4.77% 32.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 4.25% 37.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 75 4.90% 41.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 100 6.53% 48.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.81% 51.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 51 3.33% 54.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 695 45.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation +system.physmem.totQLat 71795500 # Total ticks spent queuing +system.physmem.totMemAccLat 363808000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4843.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4609.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23593.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23359.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14042 # Number of row buffer hits during reads +system.physmem.readRowHits 14039 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3935753.44 # Average gap between requests -system.physmem.pageHitRate 90.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 3934746.82 # Average gap between requests +system.physmem.pageHitRate 90.14 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6259680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3415500 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2494246185 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34588236750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41159350290 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.511167 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57530940500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2046720000 # Time in different power states +system.physmem_0.refreshEnergy 4002367200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2491685460 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34581139500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41148640140 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.507037 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57518843500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2046200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1716061500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1713017750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2575259145 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34517172750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41161458375 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.545560 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57412676250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2046720000 # Time in different power states +system.physmem_1.refreshEnergy 4002367200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2548940535 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34530915750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41147955240 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.495861 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57435989500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2046200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1834237500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1796249000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20766617 # Number of BP lookups -system.cpu.branchPred.condPredicted 17069689 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20766613 # Number of BP lookups +system.cpu.branchPred.condPredicted 17069686 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8958723 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8857106 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8958713 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8857097 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.865720 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62714 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.865730 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,67 +377,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122591037 # number of cpu cycles simulated +system.cpu.numCycles 122559681 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2197459 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2197712 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.353059 # CPI: cycles per instruction -system.cpu.ipc 0.739066 # IPC: instructions per cycle -system.cpu.tickCycles 109335027 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13256010 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.352713 # CPI: cycles per instruction +system.cpu.ipc 0.739255 # IPC: instructions per cycle +system.cpu.tickCycles 109336366 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13223315 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946108 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.919530 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267744 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3616.962336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267632 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644321 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20526719250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.919530 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.883037 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883037 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.644203 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20520732500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.962336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 254 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2248 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463926 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463926 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660805 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660805 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463928 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463928 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598652 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598652 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660698 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660698 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259462 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259462 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259970 # number of overall hits -system.cpu.dcache.overall_hits::total 26259970 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914937 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914937 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74176 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74176 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26259350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259858 # number of overall hits +system.cpu.dcache.overall_hits::total 26259858 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914943 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74283 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74283 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 989113 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989113 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989117 # number of overall misses -system.cpu.dcache.overall_misses::total 989117 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11917910744 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11917910744 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566961500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2566961500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14484872244 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14484872244 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14484872244 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14484872244 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513594 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513594 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 989226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989230 # number of overall misses +system.cpu.dcache.overall_misses::total 989230 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918923000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918923000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2541568000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2541568000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14460491000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14460491000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14460491000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14460491000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513595 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248575 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248575 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27249087 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27249087 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015666 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015666 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 27248576 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248576 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27249088 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27249088 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036300 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036300 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.935932 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.935932 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34606.361896 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34606.361896 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.304790 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14644.304790 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.245569 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14644.245569 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.036304 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036304 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036303 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.956871 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.956871 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34214.665536 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34214.665536 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14617.985172 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14617.985172 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.926064 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14617.926064 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,14 +478,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks system.cpu.dcache.writebacks::total 943289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11503 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11503 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27409 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27409 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38912 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38912 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38912 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38912 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11509 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11509 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950201 system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412555256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412555256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464079000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464079000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876634256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11876634256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11876789756 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11876789756 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865211000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865211000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480610000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480610000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345821000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12345821000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345977500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12345977500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses @@ -516,69 +516,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11525.529542 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11525.529542 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31305.813929 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31305.813929 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.075728 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.075728 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.199915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.199915 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.568626 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.568626 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31659.289670 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31659.289670 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.852039 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.852039 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.975719 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.975719 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 690.424253 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27792420 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.428077 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27792848 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34653.890274 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34654.423940 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.424253 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337121 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337121 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.428077 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337123 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337123 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55587246 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55587246 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27792420 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27792420 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27792420 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27792420 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27792420 # number of overall hits -system.cpu.icache.overall_hits::total 27792420 # number of overall hits +system.cpu.icache.tags.tag_accesses 55588102 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55588102 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27792848 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27792848 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27792848 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27792848 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27792848 # number of overall hits +system.cpu.icache.overall_hits::total 27792848 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60382998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60382998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60382998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60382998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60382998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60382998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27793222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27793222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27793222 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27793222 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27793222 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27793222 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59599500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59599500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59599500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59599500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59599500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59599500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27793650 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27793650 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27793650 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27793650 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27793650 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27793650 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75290.521197 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75290.521197 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75290.521197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75290.521197 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74313.591022 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74313.591022 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74313.591022 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74313.591022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74313.591022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74313.591022 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58841002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58841002 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58841002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58841002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58841002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58841002 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58797500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 58797500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58797500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 58797500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58797500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 58797500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73367.832918 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73367.832918 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73313.591022 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73313.591022 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73313.591022 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73313.591022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73313.591022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73313.591022 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.234608 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831338 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10246.423743 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1834010 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.717940 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.889696 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.355364 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.450791 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.428453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9356.530979 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.454442 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.438322 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285539 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020583 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312660 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312696 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -632,78 +632,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15216684 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15216684 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903175 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903201 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 15238060 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15238060 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 943289 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 943289 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903175 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 903175 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 935398 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 935424 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 935398 # number of overall hits system.cpu.l2cache.overall_hits::total 935424 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 776 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 79311250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073550250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1073550250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1095095500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1152861500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1095095500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1152861500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903437 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066648000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1066648000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57320500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57320500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21756000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21756000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57320500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1088404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1145724500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57320500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1088404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1145724500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 943289 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943289 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903437 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 903437 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 950204 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 950204 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967581 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74440.721649 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82233.778626 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76407.755299 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73813.961084 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73813.961084 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73986.747529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73986.747529 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73339.383938 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73339.383938 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73866.623711 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73866.623711 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83038.167939 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83038.167939 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73866.623711 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73511.009050 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73528.719035 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73866.623711 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73511.009050 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73528.719035 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -712,93 +718,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49433000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 940013000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 989446000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49433000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940013000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 989446000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61922.803618 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70100.585938 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63955.339806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61313.686056 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61313.686056 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63339.383938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63339.383938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63866.925065 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63866.925065 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73457.031250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73457.031250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63866.925065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63514.391892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63531.912161 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63866.925065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63514.391892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63531.912161 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2672 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843697 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845301 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903437 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846366 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2847973 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1894295 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1897118 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1894295 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1897118 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1894295 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1890436500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1897118 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891848000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1372498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428685244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1425308994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1030 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) @@ -814,9 +827,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21690500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21740500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82133750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82134000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index cb0d7cfc4..37d15d84b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058203 # Number of seconds simulated -sim_ticks 58203290500 # Number of ticks simulated -final_tick 58203290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058174 # Number of seconds simulated +sim_ticks 58174017500 # Number of ticks simulated +final_tick 58174017500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131910 # Simulator instruction rate (inst/s) -host_op_rate 132567 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84750962 # Simulator tick rate (ticks/s) -host_mem_usage 445160 # Number of bytes of host memory used -host_seconds 686.76 # Real time elapsed on the host +host_inst_rate 129950 # Simulator instruction rate (inst/s) +host_op_rate 130597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83449704 # Simulator tick rate (ticks/s) +host_mem_usage 446256 # Number of bytes of host memory used +host_seconds 697.11 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 930624 # Number of bytes read from this memory -system.physmem.bytes_read::total 1023424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 25536 # Number of bytes written to this memory -system.physmem.bytes_written::total 25536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14541 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15991 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 399 # Number of write requests responded to by this memory -system.physmem.num_writes::total 399 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 765318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15989199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17583611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 765318 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 765318 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 438738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 438738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 438738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 765318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15989199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18022349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15991 # Number of read requests accepted -system.physmem.writeReqs 399 # Number of write requests accepted -system.physmem.readBursts 15991 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1010944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue -system.physmem.bytesWritten 24064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1023424 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 25536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1015 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 49984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 930560 # Number of bytes read from this memory +system.physmem.bytes_read::total 1025024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 26560 # Number of bytes written to this memory +system.physmem.bytes_written::total 26560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14540 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16016 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 415 # Number of write requests responded to by this memory +system.physmem.num_writes::total 415 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 764603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 859215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15996145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17619962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 764603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 764603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 456561 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 456561 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 456561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 764603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 859215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15996145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18076524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16016 # Number of read requests accepted +system.physmem.writeReqs 415 # Number of write requests accepted +system.physmem.readBursts 16016 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 415 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1011776 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 13248 # Total number of bytes read from write queue +system.physmem.bytesWritten 25088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1025024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 26560 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 207 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1014 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 963 # Per bank write bursts -system.physmem.perBankRdBursts::3 1023 # Per bank write bursts +system.physmem.perBankRdBursts::2 957 # Per bank write bursts +system.physmem.perBankRdBursts::3 1028 # Per bank write bursts system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1139 # Per bank write bursts -system.physmem.perBankRdBursts::6 1118 # Per bank write bursts -system.physmem.perBankRdBursts::7 1101 # Per bank write bursts -system.physmem.perBankRdBursts::8 1044 # Per bank write bursts +system.physmem.perBankRdBursts::5 1144 # Per bank write bursts +system.physmem.perBankRdBursts::6 1126 # Per bank write bursts +system.physmem.perBankRdBursts::7 1093 # Per bank write bursts +system.physmem.perBankRdBursts::8 1040 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 939 # Per bank write bursts -system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 905 # Per bank write bursts -system.physmem.perBankRdBursts::13 898 # Per bank write bursts -system.physmem.perBankRdBursts::14 928 # Per bank write bursts -system.physmem.perBankRdBursts::15 921 # Per bank write bursts -system.physmem.perBankWrBursts::0 32 # Per bank write bursts +system.physmem.perBankRdBursts::10 938 # Per bank write bursts +system.physmem.perBankRdBursts::11 903 # Per bank write bursts +system.physmem.perBankRdBursts::12 912 # Per bank write bursts +system.physmem.perBankRdBursts::13 888 # Per bank write bursts +system.physmem.perBankRdBursts::14 938 # Per bank write bursts +system.physmem.perBankRdBursts::15 925 # Per bank write bursts +system.physmem.perBankWrBursts::0 43 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 16 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 9 # Per bank write bursts -system.physmem.perBankWrBursts::5 45 # Per bank write bursts -system.physmem.perBankWrBursts::6 72 # Per bank write bursts -system.physmem.perBankWrBursts::7 35 # Per bank write bursts -system.physmem.perBankWrBursts::8 36 # Per bank write bursts +system.physmem.perBankWrBursts::2 7 # Per bank write bursts +system.physmem.perBankWrBursts::3 6 # Per bank write bursts +system.physmem.perBankWrBursts::4 10 # Per bank write bursts +system.physmem.perBankWrBursts::5 44 # Per bank write bursts +system.physmem.perBankWrBursts::6 74 # Per bank write bursts +system.physmem.perBankWrBursts::7 25 # Per bank write bursts +system.physmem.perBankWrBursts::8 45 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 13 # Per bank write bursts -system.physmem.perBankWrBursts::11 2 # Per bank write bursts -system.physmem.perBankWrBursts::12 5 # Per bank write bursts -system.physmem.perBankWrBursts::13 37 # Per bank write bursts -system.physmem.perBankWrBursts::14 47 # Per bank write bursts -system.physmem.perBankWrBursts::15 27 # Per bank write bursts +system.physmem.perBankWrBursts::10 10 # Per bank write bursts +system.physmem.perBankWrBursts::11 5 # Per bank write bursts +system.physmem.perBankWrBursts::12 11 # Per bank write bursts +system.physmem.perBankWrBursts::13 32 # Per bank write bursts +system.physmem.perBankWrBursts::14 48 # Per bank write bursts +system.physmem.perBankWrBursts::15 32 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58203132500 # Total gap between requests +system.physmem.totGap 58173860500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15991 # Read request sizes (log2) +system.physmem.readPktSize::6 16016 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 399 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 415 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,94 +197,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 542.975328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 308.892213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 434.261771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 566 29.71% 29.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 241 12.65% 42.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 4.88% 47.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 55 2.89% 50.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 58 3.04% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 46 2.41% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 56 2.94% 58.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 43 2.26% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 747 39.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1905 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 21 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 751.047619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 33.268614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3285.704681 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 20 95.24% 95.24% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 4.76% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 21 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 21 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.904762 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.888741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.768424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 9.52% 9.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18 85.71% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 4.76% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 21 # Writes before turning the bus around for reads -system.physmem.totQLat 171453784 # Total ticks spent queuing -system.physmem.totMemAccLat 467628784 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10854.25 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.107772 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 304.077638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 432.159932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 590 30.57% 30.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 221 11.45% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 5.03% 47.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 3.58% 50.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 3.68% 54.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 49 2.54% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 2.64% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 42 2.18% 61.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 740 38.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1930 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 717.636364 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 31.597036 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3209.686449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 21 95.45% 95.45% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 4.55% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 22 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.818182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.808292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.588490 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 9.09% 9.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20 90.91% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 22 # Writes before turning the bus around for reads +system.physmem.totQLat 169690298 # Total ticks spent queuing +system.physmem.totMemAccLat 466109048 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79045000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10733.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29604.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29483.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14158 # Number of row buffer hits during reads -system.physmem.writeRowHits 107 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 27.02 # Row buffer hit rate for writes -system.physmem.avgGap 3551136.82 # Average gap between requests -system.physmem.pageHitRate 88.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7854840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4285875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1354320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2465906355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32758411500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39103960890 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.860748 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54486158959 # Time in different power states -system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states +system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing +system.physmem.avgWrQLen 17.30 # Average write queue length when enqueuing +system.physmem.readRowHits 14150 # Number of row buffer hits during reads +system.physmem.writeRowHits 110 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.83 # Row buffer hit rate for writes +system.physmem.avgGap 3540494.22 # Average gap between requests +system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7832160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4273500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64506000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1289520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2476215945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32730681000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39084249885 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.881619 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54439969881 # Time in different power states +system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1772833541 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1788917619 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6546960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3572250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58468800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1082160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2423272635 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32795809500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39090238305 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.624974 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54548877915 # Time in different power states -system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states +system.physmem_1.actEnergy 6667920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3638250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58507800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1146960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2448182205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32755263750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39072858645 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.685955 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54482617084 # Time in different power states +system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1710114585 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1747288416 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28259243 # Number of BP lookups -system.cpu.branchPred.condPredicted 23281231 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11853879 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11785418 # Number of BTB hits +system.cpu.branchPred.lookups 28257086 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279263 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837830 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842064 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784394 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.422459 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75772 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.513007 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -403,128 +402,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116406582 # number of cpu cycles simulated +system.cpu.numCycles 116348036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748963 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134993544 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28259243 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11861190 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114762985 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679231 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 807 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32304048 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 578 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116353304 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165458 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 748817 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134985012 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860154 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114705506 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679063 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1007 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 831 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32301197 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116295692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58781536 50.52% 50.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13944543 11.98% 62.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9221339 7.93% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34405886 29.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58725363 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13942075 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230802 7.94% 70.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34397452 29.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116353304 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242763 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.159673 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8844047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64088450 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33032847 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9560591 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827369 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101287 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12347 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114434695 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1995559 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827369 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15306268 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49839660 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109196 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35408210 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14862601 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110902627 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1415209 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11132813 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1143128 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1515839 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 570040 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129962079 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483289738 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119478423 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 422 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116295692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242867 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.160183 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839821 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64036145 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034290 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558144 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827292 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101248 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114428571 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996975 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827292 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15280810 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49891272 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109349 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35424705 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14762264 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110897410 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415598 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11131669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144033 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1526935 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 476507 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129954934 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483266147 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119472382 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22649160 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22642015 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21571738 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26814245 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5349583 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 611820 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 348925 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109694682 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101389793 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1073874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18661898 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41702987 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116353304 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988581 # Number of insts issued each cycle +system.cpu.rename.skidInsts 21506426 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812625 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349337 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 517439 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253975 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109689181 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101387653 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074699 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18656398 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41685630 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116295692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871809 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989320 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54657362 46.98% 46.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31448211 27.03% 74.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 21997386 18.91% 92.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7054887 6.06% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1195141 1.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54655211 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31361654 26.97% 73.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008607 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7072409 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197497 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 314 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116353304 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116295692 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9796132 48.71% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9605412 47.76% 96.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 708293 3.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9793566 48.69% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9616917 47.81% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 703878 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71985396 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71983899 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10709 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -546,90 +545,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 53 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24344165 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049339 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343332 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049532 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101389793 # Type of FU issued -system.cpu.iq.rate 0.870997 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20109899 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198342 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340316208 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128365476 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99625945 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 608 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121499455 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 237 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 282715 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101387653 # Type of FU issued +system.cpu.iq.rate 0.871417 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20114424 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340259668 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128354519 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99625011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 453 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121501841 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 290489 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4338334 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1512 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1293 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336714 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1340 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604493 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7563 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130432 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7566 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827369 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8116840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 661308 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109715594 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827292 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8117300 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684188 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109710095 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26814245 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5349583 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178503 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 319361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1293 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436568 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412973 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849541 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100128175 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23807340 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1261618 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26812625 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349337 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178987 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342189 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1340 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436578 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412874 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849452 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100126762 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806670 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1260891 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12666 # number of nop insts executed -system.cpu.iew.exec_refs 28725211 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624854 # Number of branches executed -system.cpu.iew.exec_stores 4917871 # Number of stores executed -system.cpu.iew.exec_rate 0.860159 # Inst execution rate -system.cpu.iew.wb_sent 99711063 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99626058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59706030 # num instructions producing a value -system.cpu.iew.wb_consumers 95562635 # num instructions consuming a value +system.cpu.iew.exec_nop 12667 # number of nop insts executed +system.cpu.iew.exec_refs 28724538 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624131 # Number of branches executed +system.cpu.iew.exec_stores 4917868 # Number of stores executed +system.cpu.iew.exec_rate 0.860580 # Inst execution rate +system.cpu.iew.wb_sent 99709725 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99625125 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59703453 # num instructions producing a value +system.cpu.iew.wb_consumers 95545682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.855846 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624784 # average fanout of values written-back +system.cpu.iew.wb_rate 0.856268 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624868 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17389920 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17384546 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113660326 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801103 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737104 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825591 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113603530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801504 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.738080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77212273 67.93% 67.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18641375 16.40% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7152706 6.29% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3462873 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1652643 1.45% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 524647 0.46% 95.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 723706 0.64% 96.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178634 0.16% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4111469 3.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77180399 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18615023 16.39% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7150693 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3466326 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1641860 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 544762 0.48% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 180030 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120085 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113660326 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113603530 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -675,78 +674,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4111469 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217986682 # The number of ROB reads -system.cpu.rob.rob_writes 219580711 # The number of ROB writes -system.cpu.timesIdled 588 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53278 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120085 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217915896 # The number of ROB reads +system.cpu.rob.rob_writes 219569120 # The number of ROB writes +system.cpu.timesIdled 587 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52344 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284986 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284986 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778219 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778219 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108112805 # number of integer regfile reads -system.cpu.int_regfile_writes 58701882 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 369068913 # number of cc regfile reads -system.cpu.cc_regfile_writes 58692415 # number of cc regfile writes -system.cpu.misc_regfile_reads 28415527 # number of misc regfile reads +system.cpu.cpi 1.284339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284339 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778610 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778610 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108111439 # number of integer regfile reads +system.cpu.int_regfile_writes 58700930 # number of integer regfile writes +system.cpu.fp_regfile_reads 59 # number of floating regfile reads +system.cpu.fp_regfile_writes 95 # number of floating regfile writes +system.cpu.cc_regfile_reads 369063438 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693153 # number of cc regfile writes +system.cpu.misc_regfile_reads 28414947 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5469565 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.787779 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18297385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470077 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.344996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35255000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.787779 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999586 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999586 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5470195 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.789215 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18252015 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470707 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336317 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35049500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.789215 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999588 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999588 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61924887 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61924887 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13934133 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13934133 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4354955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4354955 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61908703 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61908703 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13889937 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13889937 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353797 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353797 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18289088 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18289088 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18289610 # number of overall hits -system.cpu.dcache.overall_hits::total 18289610 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9549988 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9549988 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 380026 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 380026 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18243734 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18243734 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18244256 # number of overall hits +system.cpu.dcache.overall_hits::total 18244256 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585777 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585777 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381184 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381184 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9930014 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9930014 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9930021 # number of overall misses -system.cpu.dcache.overall_misses::total 9930021 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88444420972 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88444420972 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962617493 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3962617493 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92407038465 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92407038465 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92407038465 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92407038465 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23484121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23484121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9966961 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9966961 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9966968 # number of overall misses +system.cpu.dcache.overall_misses::total 9966968 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88717689000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88717689000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3954782792 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3954782792 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92672471792 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92672471792 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92672471792 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92672471792 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23475714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23475714 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -755,302 +754,298 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28219102 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28219102 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28219631 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28219631 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080259 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28210695 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28210695 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28211224 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28211224 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408327 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080504 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.351890 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.351890 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.351883 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.351883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.207550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.207550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10427.227329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10427.227329 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.831640 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9305.831640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.825080 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9305.825080 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 306116 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 36058 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 120736 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535416 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15.828797 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.353304 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353304 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353298 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353298 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.138003 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.138003 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10374.996831 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10374.996831 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9297.966731 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9297.966731 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9297.960201 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9297.960201 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 330068 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 99317 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121445 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12837 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.736777 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5437967 # number of writebacks -system.cpu.dcache.writebacks::total 5437967 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4312992 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4312992 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146947 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 146947 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5436552 # number of writebacks +system.cpu.dcache.writebacks::total 5436552 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337556 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337556 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158702 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158702 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4459939 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4459939 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4459939 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4459939 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5236996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233079 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 233079 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496258 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496258 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496258 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496258 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248221 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248221 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222482 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222482 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470075 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470075 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470079 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470079 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40520727758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40520727758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2294964437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2294964437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42815692195 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42815692195 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42815905195 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42815905195 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049225 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 5470703 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470703 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470707 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470707 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43246268500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43246268500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2278267197 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2278267197 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45524535697 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45524535697 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45524750197 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45524750197 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223560 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223560 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193843 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193843 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193839 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193839 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7737.399028 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7737.399028 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9846.294334 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9846.294334 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53250 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53250 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7827.258711 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7827.258711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7827.291927 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7827.291927 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.176719 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.176719 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10240.231556 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10240.231556 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8321.514748 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8321.514748 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8321.547873 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8321.547873 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 449 # number of replacements -system.cpu.icache.tags.tagsinuse 428.262881 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32302878 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35575.856828 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 451 # number of replacements +system.cpu.icache.tags.tagsinuse 428.509106 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32300030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35494.538462 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.262881 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836451 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836451 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 428.509106 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836932 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836932 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64608978 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64608978 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32302878 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32302878 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32302878 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32302878 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32302878 # number of overall hits -system.cpu.icache.overall_hits::total 32302878 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1157 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1157 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1157 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1157 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1157 # number of overall misses -system.cpu.icache.overall_misses::total 1157 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62067238 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62067238 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62067238 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62067238 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62067238 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62067238 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32304035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32304035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32304035 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32304035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32304035 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32304035 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64603278 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64603278 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32300030 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32300030 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32300030 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32300030 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32300030 # number of overall hits +system.cpu.icache.overall_hits::total 32300030 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61388483 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61388483 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61388483 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61388483 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61388483 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61388483 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32301184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32301184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32301184 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32301184 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32301184 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32301184 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53644.976664 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53644.976664 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53644.976664 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53644.976664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53644.976664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53644.976664 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18268 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 226 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53196.259099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53196.259099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53196.259099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53196.259099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53196.259099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53196.259099 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19635 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 227 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 80.831858 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.497797 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49773732 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49773732 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49773732 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49773732 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49773732 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49773732 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50524487 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50524487 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50524487 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50524487 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50524487 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50524487 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54816.885463 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54816.885463 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54816.885463 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54816.885463 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54816.885463 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54816.885463 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55521.414286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55521.414286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55521.414286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55521.414286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55521.414286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55521.414286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4492873 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.736831 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 262 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 23 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 972 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1056 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13076 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015991 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.926392 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 175272106 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 175272106 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 5436552 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 5436552 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 226009 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 226009 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 213 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 213 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243702 # 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number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25379758 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25379758 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41955257 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48552508 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 90507765 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41955257 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48552508 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 829862007 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 920369772 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 415 # number of writebacks +system.cpu.l2cache.writebacks::total 415 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 169 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 169 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 46 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 46 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 217 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20231 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 20231 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 340 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 340 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 695 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 695 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 441 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 441 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 781 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 781 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 21707 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 860658985 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 860658985 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26049500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26049500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43944500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43944500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25180500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25180500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43944500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51230000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 95174500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43944500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51230000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 860658985 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 955833485 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001454 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001454 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000138 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000265 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000138 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001501 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001501 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.763736 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000270 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.003962 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60280.541667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55837.951807 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58621.068407 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41027.438918 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74866.542773 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74866.542773 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60280.541667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64393.246684 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62419.148276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60280.541667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64393.246684 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41027.438918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42458.355492 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.003967 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 42541.593841 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76616.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76616.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63229.496403 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63229.496403 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 57098.639456 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 57098.639456 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63229.496403 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65595.390525 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64481.368564 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63229.496403 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65595.390525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44033.421707 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5237776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5237776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5437967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22114 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 233209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 233209 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1816 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16378127 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16379943 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698114944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 698173056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 22116 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10931068 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.002023 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044933 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 5245099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5436967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 31344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22118 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244189 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408706 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16410965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698064576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 698122816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 22698 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10964961 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.002070 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045451 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10908954 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 22114 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10942263 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 22698 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10931068 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10892444998 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1495005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10964961 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10907683500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1366996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8205165681 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206064991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 15652 # Transaction distribution -system.membus.trans_dist::ReadResp 15652 # Transaction distribution -system.membus.trans_dist::Writeback 399 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 339 # Transaction distribution -system.membus.trans_dist::ReadExResp 339 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32385 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32385 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1048960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1048960 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 15676 # Transaction distribution +system.membus.trans_dist::Writeback 415 # Transaction distribution +system.membus.trans_dist::CleanEvict 117 # Transaction distribution +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 15676 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32564 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1051584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1051584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16392 # Request fanout histogram +system.membus.snoop_fanout::samples 16548 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16392 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16548 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16392 # Request fanout histogram -system.membus.reqLayer0.occupancy 27168735 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16548 # Request fanout histogram +system.membus.reqLayer0.occupancy 27912645 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 83645045 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 83778508 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b81c12b39..86fbc3533 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488530500 # Number of ticks simulated -final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 361488535500 # Number of ticks simulated +final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1163469 # Simulator instruction rate (inst/s) -host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1724927568 # Simulator tick rate (ticks/s) -host_mem_usage 425840 # Number of bytes of host memory used -host_seconds 209.57 # Real time elapsed on the host +host_inst_rate 1224088 # Simulator instruction rate (inst/s) +host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1814798992 # Simulator tick rate (ticks/s) +host_mem_usage 426288 # Number of bytes of host memory used +host_seconds 199.19 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data 2606821 # To system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977061 # number of cpu cycles simulated +system.cpu.numCycles 722977071 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles +system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -206,24 +206,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id @@ -246,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48389500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48389500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48389500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48389500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48389500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48389500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -264,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54863.378685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54863.378685 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -284,34 +284,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47507500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47507500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47507500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47507500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47507500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47507500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy @@ -323,78 +323,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits system.cpu.l2cache.overall_hits::total 924850 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 46150500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 46150500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8242500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8242500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46150500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 819160500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46150500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::total 819160500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,84 +409,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 619097500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 619097500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 37360500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 37360500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6672500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6672500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37360500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 625770000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 663130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37360500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 625770000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 663130500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1875719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1875719 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1875719 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1036 # Transaction distribution system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) @@ -496,9 +508,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15606000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 78018000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1d5681a17..6f4514f73 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062108 # Number of seconds simulated -sim_ticks 62108139000 # Number of ticks simulated -final_tick 62108139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062104 # Number of seconds simulated +sim_ticks 62103992500 # Number of ticks simulated +final_tick 62103992500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114338 # Simulator instruction rate (inst/s) -host_op_rate 201331 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44948395 # Simulator tick rate (ticks/s) -host_mem_usage 455560 # Number of bytes of host memory used -host_seconds 1381.77 # Real time elapsed on the host +host_inst_rate 108853 # Simulator instruction rate (inst/s) +host_op_rate 191673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42789284 # Simulator tick rate (ticks/s) +host_mem_usage 455804 # Number of bytes of host memory used +host_seconds 1451.39 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1886080 # Number of bytes read from this memory -system.physmem.bytes_read::total 1951040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 13952 # Number of bytes written to this memory -system.physmem.bytes_written::total 13952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29470 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30485 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 218 # Number of write requests responded to by this memory -system.physmem.num_writes::total 218 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1045918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30367679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31413596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1045918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1045918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 224640 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 224640 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 224640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1045918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30367679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31638237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30485 # Number of read requests accepted -system.physmem.writeReqs 218 # Number of write requests accepted -system.physmem.readBursts 30485 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 218 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 12736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1951040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 13952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883648 # Number of bytes read from this memory +system.physmem.bytes_read::total 1948480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 11776 # Number of bytes written to this memory +system.physmem.bytes_written::total 11776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29432 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 184 # Number of write requests responded to by this memory +system.physmem.num_writes::total 184 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1043926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30330546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31374472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 189617 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 189617 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 189617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30330546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31564090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30446 # Number of read requests accepted +system.physmem.writeReqs 184 # Number of write requests accepted +system.physmem.readBursts 30446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 184 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1943488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue +system.physmem.bytesWritten 10368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1948544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11776 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1926 # Per bank write bursts -system.physmem.perBankRdBursts::1 2065 # Per bank write bursts -system.physmem.perBankRdBursts::2 2030 # Per bank write bursts -system.physmem.perBankRdBursts::3 1931 # Per bank write bursts -system.physmem.perBankRdBursts::4 2028 # Per bank write bursts -system.physmem.perBankRdBursts::5 1903 # Per bank write bursts -system.physmem.perBankRdBursts::6 1964 # Per bank write bursts -system.physmem.perBankRdBursts::7 1862 # Per bank write bursts +system.physmem.perBankRdBursts::0 1927 # Per bank write bursts +system.physmem.perBankRdBursts::1 2069 # Per bank write bursts +system.physmem.perBankRdBursts::2 2026 # Per bank write bursts +system.physmem.perBankRdBursts::3 1929 # Per bank write bursts +system.physmem.perBankRdBursts::4 2026 # Per bank write bursts +system.physmem.perBankRdBursts::5 1901 # Per bank write bursts +system.physmem.perBankRdBursts::6 1959 # Per bank write bursts +system.physmem.perBankRdBursts::7 1865 # Per bank write bursts system.physmem.perBankRdBursts::8 1938 # Per bank write bursts -system.physmem.perBankRdBursts::9 1938 # Per bank write bursts -system.physmem.perBankRdBursts::10 1804 # Per bank write bursts -system.physmem.perBankRdBursts::11 1795 # Per bank write bursts +system.physmem.perBankRdBursts::9 1937 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts +system.physmem.perBankRdBursts::11 1796 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts system.physmem.perBankRdBursts::14 1819 # Per bank write bursts -system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 14 # Per bank write bursts -system.physmem.perBankWrBursts::1 89 # Per bank write bursts -system.physmem.perBankWrBursts::2 33 # Per bank write bursts -system.physmem.perBankWrBursts::3 21 # Per bank write bursts -system.physmem.perBankWrBursts::4 13 # Per bank write bursts -system.physmem.perBankWrBursts::5 7 # Per bank write bursts +system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankWrBursts::0 25 # Per bank write bursts +system.physmem.perBankWrBursts::1 94 # Per bank write bursts +system.physmem.perBankWrBursts::2 8 # Per bank write bursts +system.physmem.perBankWrBursts::3 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 7 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts system.physmem.perBankWrBursts::6 13 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 6 # Per bank write bursts +system.physmem.perBankWrBursts::9 5 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts @@ -82,25 +82,25 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62107943500 # Total gap between requests +system.physmem.totGap 62103972000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30485 # Read request sizes (log2) +system.physmem.readPktSize::6 30446 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 218 # Write request sizes (log2) +system.physmem.writePktSize::6 184 # Write request sizes (log2) system.physmem.rdQLenPdf::0 29885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,225 +193,221 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2733 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 715.170143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 514.587482 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 389.057467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 358 13.10% 13.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 248 9.07% 22.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 120 4.39% 26.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 119 4.35% 30.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 123 4.50% 35.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 99 3.62% 39.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 98 3.59% 42.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 77 2.82% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1491 54.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2733 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 11 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2756.545455 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.211839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 9104.288367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 10 90.91% 90.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 9.09% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 11 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 11 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.090909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.068275 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.943880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 9.09% 9.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 8 72.73% 81.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 9.09% 90.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 9.09% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 11 # Writes before turning the bus around for reads -system.physmem.totQLat 137229500 # Total ticks spent queuing -system.physmem.totMemAccLat 706742000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4517.99 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2720 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 718.117647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 516.851204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 389.329010 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 349 12.83% 12.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 252 9.26% 22.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 126 4.63% 26.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 106 3.90% 30.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 106 3.90% 34.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 118 4.34% 38.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 88 3.24% 42.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 74 2.72% 44.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1501 55.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2720 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3367.333333 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 25.147360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10062.626521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 9 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads +system.physmem.totQLat 131808750 # Total ticks spent queuing +system.physmem.totMemAccLat 701190000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4340.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23267.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.22 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23090.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 31.38 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.79 # Average write queue length when enqueuing -system.physmem.readRowHits 27693 # Number of row buffer hits during reads -system.physmem.writeRowHits 139 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes -system.physmem.avgGap 2022862.38 # Average gap between requests -system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10893960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5944125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1134000 # Energy for write commands per rank (pJ) +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 13.82 # Average write queue length when enqueuing +system.physmem.readRowHits 27697 # Number of row buffer hits during reads +system.physmem.writeRowHits 108 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.70 # Row buffer hit rate for writes +system.physmem.avgGap 2027553.77 # Average gap between requests +system.physmem.pageHitRate 91.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 10848600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5919375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122421000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 997920 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2882954835 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34733126250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41812553730 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.273290 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57766447750 # Time in different power states +system.physmem_0.actBackEnergy 2874471525 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34740567750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41811500730 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.256335 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57777967000 # Time in different power states system.physmem_0.memoryStateTime::REF 2073760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2264083750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2251676750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9699480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5292375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114270000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114371400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3028786200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34605195750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41819570205 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.386420 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57553191500 # Time in different power states +system.physmem_1.actBackEnergy 3081237030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34559194500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41826144555 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.492132 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57475856750 # Time in different power states system.physmem_1.memoryStateTime::REF 2073760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2477594500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2554341750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37389273 # Number of BP lookups -system.cpu.branchPred.condPredicted 37389273 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 796060 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21398380 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21281300 # Number of BTB hits +system.cpu.branchPred.lookups 37407153 # Number of BP lookups +system.cpu.branchPred.condPredicted 37407153 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 797525 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 21397569 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21291133 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.452856 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5538224 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5409 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.502579 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5522199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5378 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 124216279 # number of cpu cycles simulated +system.cpu.numCycles 124207986 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28231712 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 201414270 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37389273 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26819524 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 95072949 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1663625 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 802 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13794 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 27828273 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 190340 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 124151097 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.859474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.368729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28243826 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 201531916 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37407153 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26813332 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 95053081 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1666271 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 14570 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.CacheLines 27854872 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 208775 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 124145503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.860655 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.369153 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 63239379 50.94% 50.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3665567 2.95% 53.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3524262 2.84% 56.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5966051 4.81% 61.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7629037 6.14% 67.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5460577 4.40% 72.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3340077 2.69% 74.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2074079 1.67% 76.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29252068 23.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 63227150 50.93% 50.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3664165 2.95% 53.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3505505 2.82% 56.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5966108 4.81% 61.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7642313 6.16% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5450974 4.39% 72.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3347715 2.70% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2079081 1.67% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29262492 23.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 124151097 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.301001 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.621480 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13268959 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63731322 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 36520631 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9798373 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 831812 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 334996047 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 831812 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18591577 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8853243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16711 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40784813 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55072941 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328614087 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2150 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 765426 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48317500 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4996682 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 330544508 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 872885571 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537662987 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 823 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 124145503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.301165 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.622536 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13298609 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63688691 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 36532978 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9792090 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 833135 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 335053232 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 833135 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18606460 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8830273 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16174 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 40807487 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55051974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328692220 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2265 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 765831 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48323645 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4961410 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 330669691 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 873156420 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537756143 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 567 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51331761 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 491 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 491 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66256508 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106310670 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36525048 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49788623 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8449867 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 325445308 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307970327 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51339 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 47254612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68858955 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1323 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 124151097 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.480609 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.128122 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 51456944 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 481 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 66169497 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106330183 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36531613 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49817317 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8395275 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 325507363 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2500 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 308019505 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 50533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 47317399 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68952386 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2055 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 124145503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.481117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.143684 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30600533 24.65% 24.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19593175 15.78% 40.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16755552 13.50% 53.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17045170 13.73% 67.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15962727 12.86% 80.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12649852 10.19% 90.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5781799 4.66% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4158736 3.35% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1603553 1.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30872061 24.87% 24.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19525697 15.73% 40.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16787256 13.52% 54.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17357634 13.98% 68.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14846406 11.96% 80.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12689504 10.22% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6302474 5.08% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3917362 3.16% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1847109 1.49% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 124151097 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 124145503 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 316480 7.51% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3709774 87.98% 95.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 190338 4.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 329941 8.31% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3456308 87.04% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 184474 4.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 175386232 56.95% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11196 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 347 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 45 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 175410718 56.95% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11212 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 340 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued @@ -437,84 +433,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98505322 31.99% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34033845 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98529790 31.99% 88.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34034069 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307970327 # Type of FU issued -system.cpu.iq.rate 2.479307 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4216592 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013692 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 744358969 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 372741153 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 305973250 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 713 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1268 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 215 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 312153240 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 339 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58265174 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 308019505 # Type of FU issued +system.cpu.iq.rate 2.479869 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3970723 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 744205245 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 372866875 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 306008038 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 524 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 864 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 311956642 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 248 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 58273942 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15531285 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58585 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41983 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5085296 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15550798 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41716 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5091861 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3668 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 124310 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3678 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 142532 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 831812 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5699246 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3054980 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 325447076 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 123578 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106310670 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36525048 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2754 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3058247 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41983 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 401587 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 444043 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 845630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 306900581 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98149248 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1069746 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 833135 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5706209 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3030570 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 325509863 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125935 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106330183 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36531613 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 471 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2800 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3033928 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41716 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 402612 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445047 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847659 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 306958421 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98183223 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1061084 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131968833 # number of memory reference insts executed -system.cpu.iew.exec_branches 31535132 # Number of branches executed -system.cpu.iew.exec_stores 33819585 # Number of stores executed -system.cpu.iew.exec_rate 2.470695 # Inst execution rate -system.cpu.iew.wb_sent 306301702 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 305973465 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231572201 # num instructions producing a value -system.cpu.iew.wb_consumers 336082865 # num instructions consuming a value +system.cpu.iew.exec_refs 132003276 # number of memory reference insts executed +system.cpu.iew.exec_branches 31537655 # Number of branches executed +system.cpu.iew.exec_stores 33820053 # Number of stores executed +system.cpu.iew.exec_rate 2.471326 # Inst execution rate +system.cpu.iew.wb_sent 306335531 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 306008206 # cumulative count of insts written-back +system.cpu.iew.wb_producers 231609196 # num instructions producing a value +system.cpu.iew.wb_consumers 336109097 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.463232 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689033 # average fanout of values written-back +system.cpu.iew.wb_rate 2.463676 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.689089 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 47355755 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 47420049 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 796864 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117707358 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.363425 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.086682 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 798401 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117693042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.363712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.086908 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 53343112 45.32% 45.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15934290 13.54% 58.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11043478 9.38% 68.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8763951 7.45% 75.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880549 1.60% 77.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1728612 1.47% 78.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 852753 0.72% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 687313 0.58% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23473300 19.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 53351319 45.33% 45.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15952359 13.55% 58.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10962553 9.31% 68.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8763534 7.45% 75.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1923790 1.63% 77.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1729278 1.47% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 853123 0.72% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 692579 0.59% 80.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23464507 19.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117707358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117693042 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -560,324 +556,330 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23473300 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 419782277 # The number of ROB reads -system.cpu.rob.rob_writes 657549499 # The number of ROB writes -system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23464507 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 419841048 # The number of ROB reads +system.cpu.rob.rob_writes 657686557 # The number of ROB writes +system.cpu.timesIdled 566 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 62483 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.786236 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.786236 # CPI: Total CPI of All Threads -system.cpu.ipc 1.271883 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.271883 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 493639930 # number of integer regfile reads -system.cpu.int_regfile_writes 240886983 # number of integer regfile writes -system.cpu.fp_regfile_reads 187 # number of floating regfile reads -system.cpu.fp_regfile_writes 111 # number of floating regfile writes -system.cpu.cc_regfile_reads 107695799 # number of cc regfile reads -system.cpu.cc_regfile_writes 64567771 # number of cc regfile writes -system.cpu.misc_regfile_reads 196286158 # number of misc regfile reads +system.cpu.cpi 0.786183 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.786183 # CPI: Total CPI of All Threads +system.cpu.ipc 1.271968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.271968 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 493729388 # number of integer regfile reads +system.cpu.int_regfile_writes 240917610 # number of integer regfile writes +system.cpu.fp_regfile_reads 146 # number of floating regfile reads +system.cpu.fp_regfile_writes 96 # number of floating regfile writes +system.cpu.cc_regfile_reads 107705980 # number of cc regfile reads +system.cpu.cc_regfile_writes 64576396 # number of cc regfile writes +system.cpu.misc_regfile_reads 196329384 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072438 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.873358 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68418587 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076534 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.948455 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19755616250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.873358 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993133 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993133 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072430 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.090496 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68424035 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076526 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.951206 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19739908500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.090496 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993186 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993186 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 606 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3373 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144472022 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144472022 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37072750 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37072750 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345837 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345837 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68418587 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68418587 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68418587 # number of overall hits -system.cpu.dcache.overall_hits::total 68418587 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2685242 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2685242 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93915 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93915 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2779157 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2779157 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2779157 # number of overall misses -system.cpu.dcache.overall_misses::total 2779157 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32132974500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32132974500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2979596244 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2979596244 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35112570744 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35112570744 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35112570744 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35112570744 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39757992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39757992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 144493228 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 144493228 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37078222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37078222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345813 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345813 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68424035 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68424035 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68424035 # number of overall hits +system.cpu.dcache.overall_hits::total 68424035 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2690377 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2690377 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93939 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93939 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2784316 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2784316 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2784316 # number of overall misses +system.cpu.dcache.overall_misses::total 2784316 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32316565000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32316565000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2955969494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2955969494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35272534494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35272534494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35272534494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35272534494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39768599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39768599 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71197744 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71197744 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71197744 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71197744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067540 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067540 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039034 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039034 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039034 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039034 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11966.509722 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11966.509722 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31726.521259 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31726.521259 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12634.252309 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12634.252309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12634.252309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12634.252309 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 199012 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 71208351 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 71208351 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 71208351 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 71208351 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067651 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067651 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039101 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039101 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039101 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039101 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12011.909483 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12011.909483 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31466.903991 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31466.903991 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12668.294293 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12668.294293 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221313 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39951 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43094 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.981402 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135587 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066723 # number of writebacks -system.cpu.dcache.writebacks::total 2066723 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690734 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 690734 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11889 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11889 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 702623 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 702623 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 702623 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 702623 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82026 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82026 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076534 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076534 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076534 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076534 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23036962750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23036962750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2767409747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2767409747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25804372497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25804372497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25804372497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25804372497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029166 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029166 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029166 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029166 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11550.198219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11550.198219 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33738.201875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33738.201875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12426.655425 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12426.655425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12426.655425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12426.655425 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2066711 # number of writebacks +system.cpu.dcache.writebacks::total 2066711 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 695911 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 695911 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11877 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11877 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 707788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 707788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 707788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 707788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994466 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994466 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82062 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24203306500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24203306500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2798613994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2798613994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27001920494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27001920494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27001920494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27001920494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12135.231435 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12135.231435 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34103.653262 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34103.653262 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 61 # number of replacements -system.cpu.icache.tags.tagsinuse 828.295860 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27826925 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 64 # number of replacements +system.cpu.icache.tags.tagsinuse 833.320748 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27853507 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1032 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26964.074612 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 26989.832364 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 828.295860 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.404441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.404441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 971 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 833.320748 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.406895 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.406895 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 968 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55657578 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55657578 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27826925 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27826925 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27826925 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27826925 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27826925 # number of overall hits -system.cpu.icache.overall_hits::total 27826925 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses -system.cpu.icache.overall_misses::total 1348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 101838000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 101838000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 101838000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 101838000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 101838000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 101838000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27828273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27828273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27828273 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27828273 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27828273 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27828273 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75547.477745 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75547.477745 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75547.477745 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75547.477745 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75547.477745 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75547.477745 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.472656 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55710776 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55710776 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27853507 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27853507 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27853507 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27853507 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27853507 # number of overall hits +system.cpu.icache.overall_hits::total 27853507 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1365 # number of overall misses +system.cpu.icache.overall_misses::total 1365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98783500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98783500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98783500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98783500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98783500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98783500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27854872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27854872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27854872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27854872 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27854872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27854872 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000049 # 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number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.714286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 316 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 316 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 316 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 316 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 316 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 333 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 333 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 333 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 333 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 333 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1032 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1032 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1032 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1032 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1032 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1032 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79628000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 79628000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79628000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 79628000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79628000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 79628000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78148000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78148000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78148000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78148000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78148000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78148000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77158.914729 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77158.914729 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77158.914729 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77158.914729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77158.914729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77158.914729 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.806202 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.806202 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.806202 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.806202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.806202 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 683.118816 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 253.452964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.602576 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007735 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.631158 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29933 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 776 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1394 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994436 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1994436 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076534 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077566 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076528 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077560 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076534 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077566 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983527 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000234 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000743 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353411 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.353411 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983527 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014192 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014673 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983527 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014192 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014673 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77250.492611 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74201.820128 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76289.811066 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73376.202462 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73376.202462 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77250.492611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73389.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73517.844842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77250.492611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73389.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73517.844842 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 2076528 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077560 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353213 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353213 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.981589 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.981589 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000219 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000219 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014174 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014655 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014174 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014655 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73022.899710 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73022.899710 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75414.116486 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75414.116486 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76271.167048 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76271.167048 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75414.116486 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.127646 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73149.083623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75414.116486 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.127646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73149.083623 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,107 +888,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 218 # number of writebacks -system.cpu.l2cache.writebacks::total 218 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1015 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1482 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29003 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29003 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1015 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29470 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1015 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29470 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30485 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65734750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28861750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94596500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1765566500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1765566500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65734750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1794428250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1860163000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65734750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1794428250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1860163000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000234 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000743 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014673 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983527 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014192 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014673 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64763.300493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61802.462527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63830.296896 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60875.306003 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60875.306003 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64763.300493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60889.998303 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61018.960144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64763.300493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60889.998303 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61018.960144 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 184 # number of writebacks +system.cpu.l2cache.writebacks::total 184 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1013 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1013 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29433 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30446 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827412000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827412000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66264500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66264500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28980500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28980500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66264500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856392500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1922657000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66264500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856392500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922657000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353213 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353213 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.981589 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000219 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000219 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014174 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014655 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014174 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014655 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63022.899710 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63022.899710 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65414.116486 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65414.116486 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66316.933638 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66316.933638 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65414.116486 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63071.807155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63149.740524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65414.116486 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63071.807155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63149.740524 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1995500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066723 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82066 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2064 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221855 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 1995466 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6085 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82092 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82092 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994436 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225475 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6227603 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265168448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265234496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4144289 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265167168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265233216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 495 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4150549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.000119 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4144289 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4150054 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 495 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4144289 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4138867500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4150549 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4141738000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1740500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1548000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121586499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3114789000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1482 # Transaction distribution -system.membus.trans_dist::ReadResp 1482 # Transaction distribution -system.membus.trans_dist::Writeback 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 29003 # Transaction distribution -system.membus.trans_dist::ReadExResp 29003 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61188 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1964992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1964992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1964992 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1448 # Transaction distribution +system.membus.trans_dist::Writeback 184 # Transaction distribution +system.membus.trans_dist::CleanEvict 34 # Transaction distribution +system.membus.trans_dist::ReadExReq 28996 # Transaction distribution +system.membus.trans_dist::ReadExResp 28996 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1450 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61108 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1960192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1960192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1960192 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30703 # Request fanout histogram +system.membus.snoop_fanout::samples 30664 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30703 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30703 # Request fanout histogram -system.membus.reqLayer0.occupancy 42842500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30664 # Request fanout histogram +system.membus.reqLayer0.occupancy 42854000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160650000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 160427250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 02993075a..d40f8a71c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365989065500 # Number of ticks simulated -final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 365988859500 # Number of ticks simulated +final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 678113 # Simulator instruction rate (inst/s) -host_op_rate 1194048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1570885616 # Simulator tick rate (ticks/s) -host_mem_usage 451452 # Number of bytes of host memory used -host_seconds 232.98 # Real time elapsed on the host +host_inst_rate 643347 # Simulator instruction rate (inst/s) +host_op_rate 1132831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1490347920 # Simulator tick rate (ticks/s) +host_mem_usage 451472 # Number of bytes of host memory used +host_seconds 245.57 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory -system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory +system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory -system.physmem.bytes_written::total 6400 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory +system.physmem.bytes_written::total 6528 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory -system.physmem.num_writes::total 100 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory +system.physmem.num_writes::total 102 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5113336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5253756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5113336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5271592 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731978131 # number of cpu cycles simulated +system.cpu.numCycles 731977719 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles +system.cpu.num_busy_cycles 731977718.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -100,12 +100,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.488591 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 126079705500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488591 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -132,14 +132,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498474000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25498474000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598457000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598457000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28096931000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28096931000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28096931000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28096931000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -156,14 +156,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.648292 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.648292 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.563647 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.563647 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13594.221389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13594.221389 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -172,8 +172,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks -system.cpu.dcache.writebacks::total 2062484 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks +system.cpu.dcache.writebacks::total 2062482 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses @@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23537754000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23537754000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492348000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492348000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26030102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26030102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26030102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26030102000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -198,22 +198,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12004.648292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12004.648292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23488.563647 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23488.563647 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.632473 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632473 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44233500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44233500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44233500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44233500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44233500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44233500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54744.430693 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54744.430693 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54744.430693 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54744.430693 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -273,117 +273,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43425500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43425500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43425500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43425500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43425500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43425500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53744.430693 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53744.430693 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 318 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 19329.043320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.394677 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 156.453912 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589876 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1242773500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1276903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34129500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1242773500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1276903000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.490660 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.490660 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 313 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.000076 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.008704 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4130121 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4130394 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 313 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1025 # Transaction distribution -system.membus.trans_dist::ReadResp 1025 # Transaction distribution -system.membus.trans_dist::Writeback 100 # Transaction distribution +system.membus.trans_dist::ReadResp 1020 # Transaction distribution +system.membus.trans_dist::Writeback 102 # Transaction distribution +system.membus.trans_dist::CleanEvict 14 # Transaction distribution system.membus.trans_dist::ReadExReq 29024 # Transaction distribution system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30149 # Request fanout histogram +system.membus.snoop_fanout::samples 30160 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30149 # Request fanout histogram -system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30160 # Request fanout histogram +system.membus.reqLayer0.occupancy 30601000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 150253000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |