diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-22 20:22:29 -0700 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-22 20:22:29 -0700 |
commit | 0cf36d94095aedef3c51447243c5a3cc14dd5d56 (patch) | |
tree | c0ed9e35fbbc5512f7fedf2947d4ae2702214f8e /tests/long/se/10.mcf/ref | |
parent | a70a83155bfe4c3877894c29f9dea720beb40f9c (diff) | |
download | gem5-0cf36d94095aedef3c51447243c5a3cc14dd5d56.tar.xz |
stats: update for previous changeset
Very small differences in IQ-specific O3 stats.
Diffstat (limited to 'tests/long/se/10.mcf/ref')
8 files changed, 60 insertions, 49 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 3203f61e7..698e8108f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -135,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=BiModeBP BTBEntries=2048 BTBTagSize=18 RASSize=16 @@ -145,11 +146,7 @@ eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 numThreads=1 -predType=bi-mode [system.cpu.dcache] type=BaseCache @@ -192,6 +189,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -209,7 +207,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -501,7 +498,7 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 is_top_level=true max_miss_count=0 @@ -568,6 +565,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -585,7 +583,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -669,13 +666,16 @@ size=1048576 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -691,9 +691,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false max_stack_size=67108864 output=cout @@ -724,11 +724,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -759,7 +762,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr index 1a4f96712..e9c9539d6 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr @@ -1 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index f37d93ec9..eaa0003ec 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:33:12 +gem5 compiled Apr 22 2015 10:58:25 +gem5 started Apr 22 2015 11:34:28 gem5 executing on phenom command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x666d940 + 0: system.cpu.isa: ISA system set to: 0 0x299b730 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -24,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 26894328500 because target called exit() +Exiting @ tick 58202727500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0eb73f5eb..7cd5a5ef6 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.058203 # Nu sim_ticks 58202727500 # Number of ticks simulated final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129726 # Simulator instruction rate (inst/s) -host_op_rate 130372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83346935 # Simulator tick rate (ticks/s) -host_mem_usage 443628 # Number of bytes of host memory used -host_seconds 698.32 # Real time elapsed on the host +host_inst_rate 129301 # Simulator instruction rate (inst/s) +host_op_rate 129945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83074382 # Simulator tick rate (ticks/s) +host_mem_usage 373768 # Number of bytes of host memory used +host_seconds 700.61 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -468,7 +468,7 @@ system.cpu.iq.iqInstsAdded 109694902 # Nu system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 18662119 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle @@ -561,10 +561,10 @@ system.cpu.iq.rate 0.871007 # In system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_writes 128365920 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 614 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 75b239bd4..80f56aa0a 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -139,7 +140,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -153,7 +154,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -620,8 +620,11 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 @@ -642,9 +645,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false max_stack_size=67108864 output=cout @@ -675,11 +678,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master @@ -710,7 +716,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr index 1a4f96712..e9c9539d6 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr @@ -1 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index b2e148902..d8c79ae54 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,11 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:13:07 -gem5 started Jun 21 2014 16:50:55 +gem5 compiled Apr 22 2015 08:10:29 +gem5 started Apr 22 2015 09:28:24 gem5 executing on phenom command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,12 +17,12 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 -info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 simplex iterations : 2663 +info: Increasing stack size by one page. flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 64361067000 because target called exit() +Exiting @ tick 62113055500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 3dba3eae0..22fd463ff 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.062113 # Nu sim_ticks 62113055500 # Number of ticks simulated final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113198 # Simulator instruction rate (inst/s) -host_op_rate 199324 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44503726 # Simulator tick rate (ticks/s) -host_mem_usage 454072 # Number of bytes of host memory used -host_seconds 1395.68 # Real time elapsed on the host +host_inst_rate 109820 # Simulator instruction rate (inst/s) +host_op_rate 193376 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43175715 # Simulator tick rate (ticks/s) +host_mem_usage 386160 # Number of bytes of host memory used +host_seconds 1438.61 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -349,7 +349,7 @@ system.cpu.iq.iqInstsAdded 325477303 # Nu system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 46683880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 47286965 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle @@ -442,10 +442,10 @@ system.cpu.iq.rate 2.479264 # In system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 372203676 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_writes 372806758 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 722 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses |