diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/se/10.mcf/ref | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/se/10.mcf/ref')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 778 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1517 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1536 |
3 files changed, 1939 insertions, 1892 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 5d753bb44..baaf2995a 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061241 # Number of seconds simulated -sim_ticks 61241011500 # Number of ticks simulated -final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061235 # Number of seconds simulated +sim_ticks 61234797500 # Number of ticks simulated +final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253883 # Simulator instruction rate (inst/s) -host_op_rate 255147 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171606317 # Simulator tick rate (ticks/s) -host_mem_usage 452068 # Number of bytes of host memory used -host_seconds 356.87 # Real time elapsed on the host +host_inst_rate 274685 # Simulator instruction rate (inst/s) +host_op_rate 276053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 185648704 # Simulator tick rate (ticks/s) +host_mem_usage 404860 # Number of bytes of host memory used +host_seconds 329.84 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory -system.physmem.bytes_read::total 996736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 996672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15466760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16275629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15466760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16275629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15574 # Number of read requests accepted +system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 807907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15468329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16276236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 807907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 807907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 807907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15468329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16276236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15573 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15573 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 996672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side +system.physmem.bytesReadSys 996672 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -44,7 +44,7 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 993 # Per bank write bursts system.physmem.perBankRdBursts::1 890 # Per bank write bursts system.physmem.perBankRdBursts::2 949 # Per bank write bursts -system.physmem.perBankRdBursts::3 1028 # Per bank write bursts +system.physmem.perBankRdBursts::3 1027 # Per bank write bursts system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1113 # Per bank write bursts system.physmem.perBankRdBursts::6 1087 # Per bank write bursts @@ -55,8 +55,8 @@ system.physmem.perBankRdBursts::10 938 # Pe system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts system.physmem.perBankRdBursts::13 867 # Per bank write bursts -system.physmem.perBankRdBursts::14 877 # Per bank write bursts -system.physmem.perBankRdBursts::15 905 # Per bank write bursts +system.physmem.perBankRdBursts::14 876 # Per bank write bursts +system.physmem.perBankRdBursts::15 906 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61240917000 # Total gap between requests +system.physmem.totGap 61234703000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15574 # Read request sizes (log2) +system.physmem.readPktSize::6 15573 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1543 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 644.935839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 438.870546 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.302511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 247 16.01% 16.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 187 12.12% 28.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 6.03% 34.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.41% 38.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.47% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 87 5.64% 48.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation -system.physmem.totQLat 73240250 # Total ticks spent queuing -system.physmem.totMemAccLat 365252750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.73 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 648.213681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 443.714701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.012846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 241 15.70% 15.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 12.12% 27.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88 5.73% 33.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 4.76% 38.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.63% 42.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 84 5.47% 48.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.35% 50.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 51 3.32% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1535 # Bytes accessed per row activation +system.physmem.totQLat 72594750 # Total ticks spent queuing +system.physmem.totMemAccLat 364588500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4661.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.73 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23411.58 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s @@ -216,49 +216,53 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14026 # Number of row buffer hits during reads +system.physmem.readRowHits 14028 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3932253.56 # Average gap between requests -system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 3932107.04 # Average gap between requests +system.physmem.pageHitRate 90.08 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63679200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2491483680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34557957750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41122783920 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.511714 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57480384250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states +system.physmem_0.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2519893620 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34528365000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41120963895 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.567381 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57430990750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2044640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1713932750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1755713000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2555148690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34502111250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41122878405 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.513257 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57387653250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states +system.physmem_1.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2548962765 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.499745 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1806576750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20752188 # Number of BP lookups -system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 757746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8939036 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8856390 # Number of BTB hits +system.cpu.branchPred.lookups 20750031 # Number of BP lookups +system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.075448 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 61984 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,67 +381,102 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122482023 # number of cpu cycles simulated +system.cpu.numCycles 122469595 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2176623 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.351856 # CPI: cycles per instruction -system.cpu.ipc 0.739724 # IPC: instructions per cycle -system.cpu.tickCycles 109255161 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13226862 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.351719 # CPI: cycles per instruction +system.cpu.ipc 0.739799 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction +system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction +system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 91054081 # Class of committed instruction +system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946097 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.872758 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.883026 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883026 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55455001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21594211 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21594211 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660690 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660690 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26254901 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26254901 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26255409 # number of overall hits -system.cpu.dcache.overall_hits::total 26255409 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26254404 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26254404 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26254912 # number of overall hits +system.cpu.dcache.overall_hits::total 26254912 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74291 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74291 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74289 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74289 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 989217 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses -system.cpu.dcache.overall_misses::total 989221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919046000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11919046000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542633500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2542633500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14461679500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14461679500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14461679500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14461679500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 989215 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989215 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989219 # number of overall misses +system.cpu.dcache.overall_misses::total 989219 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919140000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2539899500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2539899500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14459039500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14459039500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14459039500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14459039500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22508638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22508638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -446,28 +485,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27244118 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27244118 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27244630 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27244630 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040647 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040647 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015690 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015690 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 27243619 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27243619 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27244131 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27244131 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015689 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015689 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036310 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036310 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.333358 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.333358 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.323390 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.323390 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.319624 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14619.319624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.260509 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14619.260509 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14616.680398 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,107 +517,108 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks system.cpu.dcache.writebacks::total 943278 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11501 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11501 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27526 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27526 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39027 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39027 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39027 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39027 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903425 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903425 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46765 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46765 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903426 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903426 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865349000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865349000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481625500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481625500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480423500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346974500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12346974500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347131000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12347131000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345929500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12345929500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346086000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12346086000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040137 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.841188 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.841188 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.358602 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.358602 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034878 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034878 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034877 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.216420 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.216420 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.340097 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.340097 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27770468 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34626.518703 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.439811 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55543342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55543342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27770468 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27770468 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27770468 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27770468 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27770468 # number of overall hits -system.cpu.icache.overall_hits::total 27770468 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59898000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59898000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59898000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59898000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59898000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59898000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27771270 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27771270 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27771270 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27771270 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27771270 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27771270 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits +system.cpu.icache.overall_hits::total 27766889 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses +system.cpu.icache.overall_misses::total 801 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60228000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60228000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60228000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60228000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60228000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60228000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27767690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27767690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27767690 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27767690 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27767690 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27767690 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74685.785536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74685.785536 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75191.011236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75191.011236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75191.011236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75191.011236 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -589,63 +629,63 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 5 # number of writebacks system.cpu.icache.writebacks::total 5 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59096000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59096000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59096000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59096000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59096000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59096000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59427000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59427000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59427000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59427000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59427000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59427000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.556296 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655409 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.453494 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285496 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020572 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.312643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15556 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15237898 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32221 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32221 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903166 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 903166 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903167 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 903167 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 935387 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 935413 # number of demand (read+write) hits @@ -654,68 +694,68 @@ system.cpu.l2cache.overall_hits::cpu.data 935387 # n system.cpu.l2cache.overall_hits::total 935413 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 776 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 776 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 262 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 262 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 776 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses +system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses -system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067670500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1067670500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1089567500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1147164500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1089567500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1147164500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 15581 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066480500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1066480500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57929500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57929500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22043500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22043500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1088524000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1146453500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57929500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1088524000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1146453500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46765 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903428 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 903428 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903429 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 903429 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 950193 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950995 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 950994 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 950193 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 950995 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311002 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.311002 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967581 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.overall_accesses::total 950994 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967541 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967541 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967541 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967541 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.687844 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.687844 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73621.133359 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73621.133359 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73327.867162 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73327.867162 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74747.741935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74747.741935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84135.496183 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84135.496183 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73580.225916 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -736,54 +776,54 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 6 system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 774 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 774 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15573 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922230500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922230500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941176500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 990886500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941176500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 990886500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.overall_mshr_misses::total 15573 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 921040500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 921040500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50052500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50052500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19092500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19092500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50052500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 940133000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990185500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50052500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940133000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990185500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016375 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.687844 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.687844 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016375 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. @@ -793,56 +833,56 @@ system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Tr system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2848092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2848090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121233792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 950995 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 950994 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 950829 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950828 99.98% 99.98% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 950995 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891831500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1030 # Transaction distribution +system.membus.trans_dist::ReadResp 1029 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15574 # Request fanout histogram +system.membus.snoop_fanout::samples 15573 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 15573 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21739000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 15573 # Request fanout histogram +system.membus.reqLayer0.occupancy 21737000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82131250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82128750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 00e478cc7..fd8ec81c4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058179 # Number of seconds simulated -sim_ticks 58178990500 # Number of ticks simulated -final_tick 58178990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058199 # Number of seconds simulated +sim_ticks 58199030500 # Number of ticks simulated +final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60429 # Simulator instruction rate (inst/s) -host_op_rate 60730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38808737 # Simulator tick rate (ticks/s) -host_mem_usage 520460 # Number of bytes of host memory used -host_seconds 1499.12 # Real time elapsed on the host +host_inst_rate 158181 # Simulator instruction rate (inst/s) +host_op_rate 158969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101622775 # Simulator tick rate (ticks/s) +host_mem_usage 491528 # Number of bytes of host memory used +host_seconds 572.70 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 57344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 923968 # Number of bytes read from this memory -system.physmem.bytes_read::total 1026176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10880 # Number of bytes written to this memory -system.physmem.bytes_written::total 10880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 701 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14437 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16034 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 170 # Number of write requests responded to by this memory -system.physmem.num_writes::total 170 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 771137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 985648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15881472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17638257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 771137 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 771137 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 771137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 985648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15881472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17825266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16035 # Number of read requests accepted -system.physmem.writeReqs 170 # Number of write requests accepted -system.physmem.readBursts 16035 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 170 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1017600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue -system.physmem.bytesWritten 9088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1026240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory +system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory +system.physmem.bytes_written::total 11200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory +system.physmem.num_writes::total 175 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16517 # Number of read requests accepted +system.physmem.writeReqs 175 # Number of write requests accepted +system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1166 # Per bank write bursts -system.physmem.perBankRdBursts::1 919 # Per bank write bursts +system.physmem.perBankRdBursts::1 920 # Per bank write bursts system.physmem.perBankRdBursts::2 953 # Per bank write bursts -system.physmem.perBankRdBursts::3 1033 # Per bank write bursts -system.physmem.perBankRdBursts::4 1062 # Per bank write bursts -system.physmem.perBankRdBursts::5 1116 # Per bank write bursts -system.physmem.perBankRdBursts::6 1091 # Per bank write bursts +system.physmem.perBankRdBursts::3 1031 # Per bank write bursts +system.physmem.perBankRdBursts::4 1061 # Per bank write bursts +system.physmem.perBankRdBursts::5 1122 # Per bank write bursts +system.physmem.perBankRdBursts::6 1094 # Per bank write bursts system.physmem.perBankRdBursts::7 1089 # Per bank write bursts -system.physmem.perBankRdBursts::8 1024 # Per bank write bursts +system.physmem.perBankRdBursts::8 1025 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 937 # Per bank write bursts +system.physmem.perBankRdBursts::10 933 # Per bank write bursts system.physmem.perBankRdBursts::11 900 # Per bank write bursts -system.physmem.perBankRdBursts::12 906 # Per bank write bursts -system.physmem.perBankRdBursts::13 899 # Per bank write bursts -system.physmem.perBankRdBursts::14 910 # Per bank write bursts -system.physmem.perBankRdBursts::15 933 # Per bank write bursts -system.physmem.perBankWrBursts::0 7 # Per bank write bursts +system.physmem.perBankRdBursts::12 903 # Per bank write bursts +system.physmem.perBankRdBursts::13 900 # Per bank write bursts +system.physmem.perBankRdBursts::14 1411 # Per bank write bursts +system.physmem.perBankRdBursts::15 910 # Per bank write bursts +system.physmem.perBankWrBursts::0 2 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 12 # Per bank write bursts -system.physmem.perBankWrBursts::3 4 # Per bank write bursts +system.physmem.perBankWrBursts::2 6 # Per bank write bursts +system.physmem.perBankWrBursts::3 1 # Per bank write bursts system.physmem.perBankWrBursts::4 3 # Per bank write bursts -system.physmem.perBankWrBursts::5 12 # Per bank write bursts -system.physmem.perBankWrBursts::6 37 # Per bank write bursts -system.physmem.perBankWrBursts::7 2 # Per bank write bursts +system.physmem.perBankWrBursts::5 16 # Per bank write bursts +system.physmem.perBankWrBursts::6 40 # Per bank write bursts +system.physmem.perBankWrBursts::7 7 # Per bank write bursts system.physmem.perBankWrBursts::8 2 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 6 # Per bank write bursts -system.physmem.perBankWrBursts::11 4 # Per bank write bursts -system.physmem.perBankWrBursts::12 7 # Per bank write bursts -system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 33 # Per bank write bursts -system.physmem.perBankWrBursts::15 1 # Per bank write bursts +system.physmem.perBankWrBursts::10 2 # Per bank write bursts +system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::12 2 # Per bank write bursts +system.physmem.perBankWrBursts::13 17 # Per bank write bursts +system.physmem.perBankWrBursts::14 37 # Per bank write bursts +system.physmem.perBankWrBursts::15 7 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58178982000 # Total gap between requests +system.physmem.totGap 58199022000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16035 # Read request sizes (log2) +system.physmem.readPktSize::6 16517 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 170 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 291 # What read queue length does an incoming req see +system.physmem.writePktSize::6 175 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -148,8 +148,8 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see @@ -157,9 +157,9 @@ system.physmem.wrQLenPdf::20 9 # Wh system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see @@ -197,93 +197,95 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1792 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 572.928571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 339.689561 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 430.205419 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 476 26.56% 26.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 210 11.72% 38.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 97 5.41% 43.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 3.52% 47.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 46 2.57% 49.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 3.18% 52.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 50 2.79% 55.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 48 2.68% 58.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 745 41.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1980.250000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 75.328493 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 5451.280656 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.750000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.736929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.707107 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 7 87.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads -system.physmem.totQLat 173529353 # Total ticks spent queuing -system.physmem.totMemAccLat 471654353 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10913.11 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4999.69 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29661.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.totQLat 175730624 # Total ticks spent queuing +system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.26 # Average write queue length when enqueuing -system.physmem.readRowHits 14205 # Number of row buffer hits during reads -system.physmem.writeRowHits 45 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 27.11 # Row buffer hit rate for writes -system.physmem.avgGap 3590187.10 # Average gap between requests -system.physmem.pageHitRate 88.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7794360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4252875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 65746200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 498960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2649738195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32583140250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39111131160 # Total energy per rank (pJ) -system.physmem_0.averagePower 672.253743 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54193285294 # Time in different power states -system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing +system.physmem.readRowHits 14651 # Number of row buffer hits during reads +system.physmem.writeRowHits 51 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes +system.physmem.avgGap 3486641.62 # Average gap between requests +system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ) +system.physmem_0.averagePower 672.381118 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states +system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2043128456 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5753160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3139125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58273800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 421200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2342596545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32852562750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39062706900 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.421412 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54644034494 # Time in different power states -system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states +system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.780705 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states +system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1592379256 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257760 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279733 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837848 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842330 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784674 # Number of BTB hits +system.cpu.branchPred.lookups 28233538 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513136 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75804 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -402,83 +404,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116357982 # number of cpu cycles simulated +system.cpu.numCycles 116398062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748703 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134988401 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257760 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860478 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114715121 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679113 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32302514 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 574 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116305190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165894 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319044 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58733287 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13942631 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230901 7.94% 70.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398371 29.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116305190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242852 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160113 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839704 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64044923 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33035218 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558027 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827318 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101316 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114430969 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996281 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827318 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15281065 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49888125 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109559 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35425090 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14774033 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110899108 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1414941 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11132282 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1143663 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1527047 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 487517 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129956871 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483273963 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119474159 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483153288 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22643952 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4359 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21508074 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812702 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5350076 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 518927 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 253927 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109691489 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8248 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101389067 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1075877 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18658707 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41691247 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116305190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871750 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989327 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41667299 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54664640 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31360805 26.96% 73.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22009670 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7071691 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1198071 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -486,44 +488,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116305190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9787073 48.68% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614641 47.82% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 704123 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71985140 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10711 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -551,82 +553,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343416 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049618 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101389067 # Type of FU issued -system.cpu.iq.rate 0.871355 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20105900 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198304 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340264641 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128359131 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99626279 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued +system.cpu.iq.rate 0.870864 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121494727 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 289423 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4336791 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1514 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1348 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 605232 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7566 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130606 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827318 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8114310 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 683997 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109712406 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812702 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5350076 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4360 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178818 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342272 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1348 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436595 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849476 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100127969 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806710 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1261098 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12669 # number of nop insts executed -system.cpu.iew.exec_refs 28724643 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624882 # Number of branches executed -system.cpu.iew.exec_stores 4917933 # Number of stores executed -system.cpu.iew.exec_rate 0.860517 # Inst execution rate -system.cpu.iew.wb_sent 99711034 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99626392 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59704097 # num instructions producing a value -system.cpu.iew.wb_consumers 95546076 # num instructions consuming a value -system.cpu.iew.wb_rate 0.856206 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624872 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17384953 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 12822 # number of nop insts executed +system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621209 # Number of branches executed +system.cpu.iew.exec_stores 4915850 # Number of stores executed +system.cpu.iew.exec_rate 0.860065 # Inst execution rate +system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59691637 # num instructions producing a value +system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value +system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825610 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113612998 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737923 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77188479 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18612991 16.38% 84.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7152574 6.30% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3468909 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644585 1.45% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541952 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704226 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178939 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120343 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113612998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -672,78 +674,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120343 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217925513 # The number of ROB reads -system.cpu.rob.rob_writes 219569964 # The number of ROB writes -system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 52792 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217947492 # The number of ROB reads +system.cpu.rob.rob_writes 219521309 # The number of ROB writes +system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284449 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284449 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778544 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778544 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108112154 # number of integer regfile reads -system.cpu.int_regfile_writes 58701199 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 369067542 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693892 # number of cc regfile writes -system.cpu.misc_regfile_reads 28415154 # number of misc regfile reads +system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108097873 # number of integer regfile reads +system.cpu.int_regfile_writes 58692304 # number of integer regfile writes +system.cpu.fp_regfile_reads 59 # number of floating regfile reads +system.cpu.fp_regfile_writes 96 # number of floating regfile writes +system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes +system.cpu.misc_regfile_reads 28410228 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470195 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.784912 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18253010 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470707 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336499 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35707500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.784912 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999580 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5470634 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61911209 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61911209 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13890997 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13890997 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353726 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353726 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18244723 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18244723 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18245245 # number of overall hits -system.cpu.dcache.overall_hits::total 18245245 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585970 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585970 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381255 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381255 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits +system.cpu.dcache.overall_hits::total 18241600 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9967225 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9967225 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9967232 # number of overall misses -system.cpu.dcache.overall_misses::total 9967232 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88736242500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88736242500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002302858 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4002302858 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92738545358 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92738545358 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92738545358 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92738545358 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23476967 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23476967 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses +system.cpu.dcache.overall_misses::total 9968505 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -752,309 +754,309 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28211948 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28211948 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28212477 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28212477 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408314 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408314 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080519 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353298 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353298 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353292 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353292 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.887149 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.887149 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10497.705887 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10497.705887 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.349541 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9304.349541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.343007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9304.343007 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 330007 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 109189 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121421 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12842 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717874 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.502492 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5470195 # number of writebacks -system.cpu.dcache.writebacks::total 5470195 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337753 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337753 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158766 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158766 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks +system.cpu.dcache.writebacks::total 5470634 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496519 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496519 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496519 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496519 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248217 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248217 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222489 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222489 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470706 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470706 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470710 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470710 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43257355500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43257355500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285854739 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285854739 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45543210239 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45543210239 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45543424739 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45543424739 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223547 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223547 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193911 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.295526 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.295526 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.012374 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.012374 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.923737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.923737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.956859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.956859 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 452 # number of replacements -system.cpu.icache.tags.tagsinuse 428.759642 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32301343 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 911 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35457.017563 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 447 # number of replacements +system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.759642 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.837421 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.837421 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64605911 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64605911 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32301343 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32301343 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32301343 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32301343 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32301343 # number of overall hits -system.cpu.icache.overall_hits::total 32301343 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1157 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1157 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1157 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1157 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1157 # number of overall misses -system.cpu.icache.overall_misses::total 1157 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61697981 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61697981 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61697981 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61697981 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61697981 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61697981 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32302500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32302500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32302500 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32302500 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32302500 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32302500 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53325.826275 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53325.826275 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53325.826275 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53325.826275 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18986 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 108 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits +system.cpu.icache.overall_hits::total 32273898 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses +system.cpu.icache.overall_misses::total 1145 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.382222 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 452 # number of writebacks -system.cpu.icache.writebacks::total 452 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 912 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 912 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50324485 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50324485 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50324485 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50324485 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50324485 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50324485 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 447 # number of writebacks +system.cpu.icache.writebacks::total 447 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55180.356360 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55180.356360 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4981576 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5296807 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 274066 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14075593 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 236 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11228.158132 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5318864 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14906 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 356.827050 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 248 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11064.722538 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 163.435594 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.675337 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009975 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.685312 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 176 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14494 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 160 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3697 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9309 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 890 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010742 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884644 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180495153 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180495153 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 5450602 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5450602 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 17129 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 17129 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226024 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226024 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 209 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 209 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243596 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243596 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 209 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469620 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469829 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 209 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469620 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469829 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits +system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 703 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 703 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 588 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 588 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 703 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1087 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1790 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 703 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1087 # number of overall misses -system.cpu.l2cache.overall_misses::total 1790 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 60500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41219500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41219500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48001500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 48001500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 40148500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 40148500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48001500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 81368000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 129369500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 48001500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 81368000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 129369500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 5450602 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 5450602 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 17129 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 17129 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 500 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 500 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 695 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 695 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1065 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1065 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1565 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2260 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1565 # number of overall misses +system.cpu.l2cache.overall_misses::total 2260 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 59500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 59500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41259500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41259500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47414000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47414000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71274500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71274500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47414000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112534000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 159948000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47414000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112534000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 159948000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5451171 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5451171 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 17033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17033 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 226523 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 226523 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 912 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 912 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244184 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 5244184 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 912 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5470707 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5471619 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 912 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5470707 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5471619 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244627 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 5244627 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 5471146 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5471146 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002203 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002203 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.770833 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.770833 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.770833 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000199 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000327 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.770833 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000199 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82604.208417 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82604.208417 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68280.938834 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68280.938834 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68279.761905 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68279.761905 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68280.938834 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74855.565777 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72273.463687 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68280.938834 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74855.565777 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72273.463687 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002207 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002207 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.767956 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.767956 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000203 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000203 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767956 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000286 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.000413 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767956 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000286 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000413 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82519 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82519 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1063,158 +1065,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 170 # number of writebacks -system.cpu.l2cache.writebacks::total 170 # number of writebacks +system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks +system.cpu.l2cache.writebacks::total 175 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 196 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 191 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316176 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 316176 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 196 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316084 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 316084 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 702 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 702 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 556 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 556 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 702 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 897 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1599 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 702 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 897 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316176 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 317775 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 851895298 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 851895298 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32684500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32684500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43736000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43736000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35150000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35150000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43736000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67834500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 111570500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43736000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67834500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 851895298 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 963465798 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1028 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1028 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1370 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2064 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1370 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316084 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 318148 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852614747 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 41500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 41500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32745000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32745000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43196500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43196500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63614500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63614500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96359500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139556000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96359500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 992170747 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.769737 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000106 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000106 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000292 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058077 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.370534 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95848.973607 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95848.973607 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62301.994302 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62301.994302 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63219.424460 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63219.424460 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69775.171982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3031.911881 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 10942269 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470664 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2916 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 303004 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302696 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 308 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5245095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5450772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 20045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318050 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244184 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2275 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16411619 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16413894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 87232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700217984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700305216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 319547 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5791165 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.224033 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 319939 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485231 94.72% 94.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305626 5.28% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 308 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5791165 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10941781515 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1367498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206066491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15694 # Transaction distribution -system.membus.trans_dist::WritebackDirty 170 # Transaction distribution -system.membus.trans_dist::CleanEvict 58 # Transaction distribution +system.membus.trans_dist::ReadResp 16175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 175 # Transaction distribution +system.membus.trans_dist::CleanEvict 63 # Transaction distribution system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 340 # Transaction distribution -system.membus.trans_dist::ReadExResp 340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15695 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32301 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1037056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1037056 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 341 # Transaction distribution +system.membus.trans_dist::ReadExResp 341 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16267 # Request fanout histogram +system.membus.snoop_fanout::samples 16759 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16267 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16267 # Request fanout histogram -system.membus.reqLayer0.occupancy 26872796 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16759 # Request fanout histogram +system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 83907066 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 63290598f..d813cd17b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061602 # Number of seconds simulated -sim_ticks 61602281500 # Number of ticks simulated -final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065987 # Number of seconds simulated +sim_ticks 65986743500 # Number of ticks simulated +final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60207 # Simulator instruction rate (inst/s) -host_op_rate 106015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23475786 # Simulator tick rate (ticks/s) -host_mem_usage 445092 # Number of bytes of host memory used -host_seconds 2624.08 # Real time elapsed on the host +host_inst_rate 126294 # Simulator instruction rate (inst/s) +host_op_rate 222383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52748930 # Simulator tick rate (ticks/s) +host_mem_usage 414760 # Number of bytes of host memory used +host_seconds 1250.96 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory -system.physmem.bytes_written::total 12160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30421 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory -system.physmem.num_writes::total 190 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30568218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31605063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30568218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31802458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30421 # Number of read requests accepted -system.physmem.writeReqs 190 # Number of write requests accepted -system.physmem.readBursts 30421 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1941440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue -system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1946944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory +system.physmem.bytes_written::total 17920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30622 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory +system.physmem.num_writes::total 280 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30622 # Number of read requests accepted +system.physmem.writeReqs 280 # Number of write requests accepted +system.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue +system.physmem.bytesWritten 16064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1928 # Per bank write bursts -system.physmem.perBankRdBursts::1 2059 # Per bank write bursts -system.physmem.perBankRdBursts::2 2023 # Per bank write bursts -system.physmem.perBankRdBursts::3 1928 # Per bank write bursts -system.physmem.perBankRdBursts::4 2025 # Per bank write bursts -system.physmem.perBankRdBursts::5 1901 # Per bank write bursts -system.physmem.perBankRdBursts::6 1952 # Per bank write bursts -system.physmem.perBankRdBursts::7 1864 # Per bank write bursts -system.physmem.perBankRdBursts::8 1938 # Per bank write bursts -system.physmem.perBankRdBursts::9 1931 # Per bank write bursts -system.physmem.perBankRdBursts::10 1804 # Per bank write bursts +system.physmem.perBankRdBursts::0 1932 # Per bank write bursts +system.physmem.perBankRdBursts::1 2084 # Per bank write bursts +system.physmem.perBankRdBursts::2 2041 # Per bank write bursts +system.physmem.perBankRdBursts::3 1935 # Per bank write bursts +system.physmem.perBankRdBursts::4 2086 # Per bank write bursts +system.physmem.perBankRdBursts::5 1909 # Per bank write bursts +system.physmem.perBankRdBursts::6 1974 # Per bank write bursts +system.physmem.perBankRdBursts::7 1865 # Per bank write bursts +system.physmem.perBankRdBursts::8 1948 # Per bank write bursts +system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::10 1806 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts -system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1818 # Per bank write bursts -system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankRdBursts::13 1799 # Per bank write bursts +system.physmem.perBankRdBursts::14 1828 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts system.physmem.perBankWrBursts::0 10 # Per bank write bursts -system.physmem.perBankWrBursts::1 78 # Per bank write bursts -system.physmem.perBankWrBursts::2 7 # Per bank write bursts -system.physmem.perBankWrBursts::3 28 # Per bank write bursts -system.physmem.perBankWrBursts::4 6 # Per bank write bursts -system.physmem.perBankWrBursts::5 7 # Per bank write bursts +system.physmem.perBankWrBursts::1 107 # Per bank write bursts +system.physmem.perBankWrBursts::2 30 # Per bank write bursts +system.physmem.perBankWrBursts::3 12 # Per bank write bursts +system.physmem.perBankWrBursts::4 60 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts system.physmem.perBankWrBursts::6 16 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts @@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61602096500 # Total gap between requests +system.physmem.totGap 65986546500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30421 # Read request sizes (log2) +system.physmem.readPktSize::6 30622 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 190 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,322 +193,331 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 716.466005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 515.355667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.992511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 365 13.41% 13.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 230 8.45% 21.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 132 4.85% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 112 4.12% 43.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3363.666667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10055.376646 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.777778 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.765969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.666667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 133021500 # Total ticks spent queuing -system.physmem.totMemAccLat 701802750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151675000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4385.08 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads +system.physmem.totQLat 136557750 # Total ticks spent queuing +system.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23135.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.25 # Data bus utilization in percentage -system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing -system.physmem.readRowHits 27658 # Number of row buffer hits during reads -system.physmem.writeRowHits 106 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes -system.physmem.avgGap 2012416.99 # Average gap between requests -system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 121984200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 984960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2835924705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34470717000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41469713850 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.239327 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57330547250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing +system.physmem.readRowHits 27745 # Number of row buffer hits during reads +system.physmem.writeRowHits 178 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes +system.physmem.avgGap 2135348.73 # Average gap between requests +system.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.125124 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2211196750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114199800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41481566430 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.431898 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states +system.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.182663 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2480893250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 36908905 # Number of BP lookups -system.cpu.branchPred.condPredicted 36908905 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21094596 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21013333 # Number of BTB hits +system.cpu.branchPred.lookups 40828848 # Number of BP lookups +system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5443330 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4414 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 123204564 # number of cpu cycles simulated +system.cpu.numCycles 131973488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27815555 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 199030250 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36908905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26456663 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94541896 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1553195 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5275 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 27443897 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 182895 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 123139703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.847279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.366421 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62945303 51.12% 51.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3649645 2.96% 54.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3480674 2.83% 56.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5913881 4.80% 61.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7544216 6.13% 67.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5413971 4.40% 72.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3251108 2.64% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2020095 1.64% 76.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28920810 23.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123139703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299574 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.615445 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12941515 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63708297 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 35887575 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9825719 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 776597 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 331225446 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 776597 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18253426 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8529207 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40202725 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55360957 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 325142954 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 778303 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48626694 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4947433 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 327068188 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 863737810 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532004029 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40712149 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44736331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47855441 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 492 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 63882734 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 501 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30259811 24.57% 24.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19566759 15.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16687041 13.55% 54.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17331203 14.07% 68.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14759381 11.99% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12567446 10.21% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6273248 5.09% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3904177 3.17% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1790637 1.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123139703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 338800 8.53% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 197610 4.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174121950 56.88% 56.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 306103027 # Type of FU issued -system.cpu.iq.rate 2.484510 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3969927 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304282658 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310039433 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58196288 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 319025181 # Type of FU issued +system.cpu.iq.rate 2.417343 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4729640 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141544 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 776597 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5329160 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3100599 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322303732 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1101 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 414776 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 786455 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 305156727 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97750586 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 946300 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131430384 # number of memory reference insts executed -system.cpu.iew.exec_branches 31401849 # Number of branches executed -system.cpu.iew.exec_stores 33679798 # Number of stores executed -system.cpu.iew.exec_rate 2.476830 # Inst execution rate -system.cpu.iew.wb_sent 304565843 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304282791 # cumulative count of insts written-back -system.cpu.iew.wb_producers 230213909 # num instructions producing a value -system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value -system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 135188403 # number of memory reference insts executed +system.cpu.iew.exec_branches 32185799 # Number of branches executed +system.cpu.iew.exec_stores 34371814 # Number of stores executed +system.cpu.iew.exec_rate 2.398114 # Inst execution rate +system.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 314642345 # cumulative count of insts written-back +system.cpu.iew.wb_producers 238446717 # num instructions producing a value +system.cpu.iew.wb_consumers 344411432 # num instructions consuming a value +system.cpu.iew.wb_rate 2.384133 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117118936 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.375299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.092759 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52925822 45.19% 45.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15815600 13.50% 58.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10978628 9.37% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8749337 7.47% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1860126 1.59% 77.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1720772 1.47% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865935 0.74% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 690105 0.59% 79.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23512611 20.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117118936 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,340 +563,337 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23512611 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 416008479 # The number of ROB reads -system.cpu.rob.rob_writes 650833820 # The number of ROB writes -system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64861 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 445462066 # The number of ROB reads +system.cpu.rob.rob_writes 702797421 # The number of ROB writes +system.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.779832 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.779832 # CPI: Total CPI of All Threads -system.cpu.ipc 1.282327 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.282327 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 491477136 # number of integer regfile reads -system.cpu.int_regfile_writes 239432261 # number of integer regfile writes -system.cpu.fp_regfile_reads 110 # number of floating regfile reads -system.cpu.fp_regfile_writes 84 # number of floating regfile writes -system.cpu.cc_regfile_reads 107533030 # number of cc regfile reads -system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes -system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads +system.cpu.cpi 0.835336 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads +system.cpu.ipc 1.197123 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 504041942 # number of integer regfile reads +system.cpu.int_regfile_writes 248656420 # number of integer regfile writes +system.cpu.fp_regfile_reads 4180 # number of floating regfile reads +system.cpu.fp_regfile_writes 782 # number of floating regfile writes +system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads +system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes +system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072312 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.008256 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076408 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.783074 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.008256 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993166 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993166 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2073508 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 143788642 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 143788642 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345825 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68071037 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits -system.cpu.dcache.overall_hits::total 68071037 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2691153 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2691153 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2785080 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2785080 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2785080 # number of overall misses -system.cpu.dcache.overall_misses::total 2785080 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304195500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32304195500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35260810494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35260810494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35260810494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35260810494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39416365 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39416365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits +system.cpu.dcache.overall_hits::total 71894591 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses +system.cpu.dcache.overall_misses::total 2787704 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 70856117 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 70856117 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 70856117 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 70856117 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12660.609567 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12660.609567 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124387 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks -system.cpu.dcache.writebacks::total 2066601 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks +system.cpu.dcache.writebacks::total 2066969 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 708671 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994365 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994365 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076409 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076409 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076409 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076409 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995319995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26995319995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995319995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26995319995 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 710100 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 710100 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995754 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995754 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81850 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81850 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077604 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27017191493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002603 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002603 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027819 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 53 # number of replacements -system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27442574 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27090.398815 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 93 # number of replacements +system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 825.039758 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.402851 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.402851 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 54888808 # Number of tag accesses -system.cpu.icache.tags.data_accesses 54888808 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27442574 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27442574 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27442574 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27442574 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27442574 # number of overall hits -system.cpu.icache.overall_hits::total 27442574 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1323 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1323 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1323 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses -system.cpu.icache.overall_misses::total 1323 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 97204000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 97204000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 97204000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 97204000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 97204000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 97204000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27443897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27443897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27443897 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27443897 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27443897 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27443897 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits +system.cpu.icache.overall_hits::total 29996478 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses +system.cpu.icache.overall_misses::total 1445 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 106088999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 106088999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 106088999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 106088999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29997923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29997923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29997923 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29997923 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29997923 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29997923 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73472.411187 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73472.411187 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73472.411187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73472.411187 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73417.992388 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73417.992388 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73417.992388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73417.992388 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 53 # number of writebacks -system.cpu.icache.writebacks::total 53 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1014 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77418000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 77418000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77418000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 77418000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77418000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 77418000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 93 # number of writebacks +system.cpu.icache.writebacks::total 93 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 332 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 332 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 332 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1113 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1113 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1113 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1113 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1113 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1113 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 84684499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 84684499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 84684499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 84684499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 84684499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 84684499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 493 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20711.322176 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4035102 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30410 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.689970 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 650 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 244.920687 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007474 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.632059 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29917 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27622 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.912994 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33310456 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33310456 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 53 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53071 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53071 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1993914 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1993914 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046985 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2047001 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046985 # number of overall hits -system.cpu.l2cache.overall_hits::total 2047001 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 425 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 425 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29423 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30421 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29423 # number of overall misses -system.cpu.l2cache.overall_misses::total 30421 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118138000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2118138000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75717000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 75717000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32635000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32635000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 75717000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2150773000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2226490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 75717000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2150773000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2226490000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 53 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82069 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1014 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1014 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994339 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1994339 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076408 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077422 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076408 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077422 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353337 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.353337 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.984221 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.984221 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000213 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000213 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984221 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76788.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76788.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73189.244272 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73189.244272 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 275.118635 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.598769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.008396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.628858 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29972 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 833 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 52906 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 52906 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995161 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1995161 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2048067 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2048095 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2048067 # number of overall hits +system.cpu.l2cache.overall_hits::total 2048095 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 28982 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28982 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1085 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1085 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 555 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 555 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29537 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30622 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1085 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29537 # number of overall misses +system.cpu.l2cache.overall_misses::total 30622 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2117059500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2117059500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 82707500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 82707500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43407000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 43407000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 82707500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2160466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2243174000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 82707500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2160466500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2243174000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066969 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2066969 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81888 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81888 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1113 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1113 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995716 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1995716 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1113 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2077604 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2078717 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1113 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2077604 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078717 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353922 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353922 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974843 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974843 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000278 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000278 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.974843 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014217 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014731 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.974843 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014217 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014731 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73047.391484 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73047.391484 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76228.110599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76228.110599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78210.810811 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78210.810811 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73253.673829 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73253.673829 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -896,123 +902,121 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 190 # number of writebacks -system.cpu.l2cache.writebacks::total 190 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 998 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 425 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 425 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29423 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30421 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29423 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30421 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828158000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828158000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65737000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65737000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28385000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28385000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856543000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1922280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856543000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1922280000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000213 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks +system.cpu.l2cache.writebacks::total 280 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29537 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30622 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1085 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29537 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30622 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 71857500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 71857500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 37857000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 37857000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71857500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1865096500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1936954000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71857500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1865096500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1936954000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4149788 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072369 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1995353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994339 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6227211 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265220864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 493 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2077916 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 650 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2077591 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2077916 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4141548000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3114612500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1423 # Transaction distribution -system.membus.trans_dist::WritebackDirty 190 # Transaction distribution -system.membus.trans_dist::CleanEvict 24 # Transaction distribution -system.membus.trans_dist::ReadExReq 28998 # Transaction distribution -system.membus.trans_dist::ReadExResp 28998 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1423 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61056 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1959104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1640 # Transaction distribution +system.membus.trans_dist::WritebackDirty 280 # Transaction distribution +system.membus.trans_dist::CleanEvict 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 28982 # Transaction distribution +system.membus.trans_dist::ReadExResp 28982 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30635 # Request fanout histogram +system.membus.snoop_fanout::samples 30947 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30635 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30635 # Request fanout histogram -system.membus.reqLayer0.occupancy 42769000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30947 # Request fanout histogram +system.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160316500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |