diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/se/10.mcf/ref | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/se/10.mcf/ref')
9 files changed, 1261 insertions, 1029 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index effbf44c1..d00c8cdc7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061144 # Nu sim_ticks 61144411500 # Number of ticks simulated final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253751 # Simulator instruction rate (inst/s) -host_op_rate 255015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171247115 # Simulator tick rate (ticks/s) -host_mem_usage 451144 # Number of bytes of host memory used -host_seconds 357.05 # Real time elapsed on the host +host_inst_rate 269135 # Simulator instruction rate (inst/s) +host_op_rate 270476 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181629122 # Simulator tick rate (ticks/s) +host_mem_usage 440052 # Number of bytes of host memory used +host_seconds 336.64 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # By system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation -system.physmem.totQLat 71444000 # Total ticks spent queuing -system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 71490500 # Total ticks spent queuing +system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s @@ -223,24 +223,32 @@ system.physmem.memoryStateTime::REF 2041520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 16301343 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1030 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 996736 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15574 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15574 # Request fanout histogram +system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 20748985 # Number of BP lookups -system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20748984 # Number of BP lookups +system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits @@ -342,15 +350,15 @@ system.cpu.discardedOps 2027782 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.349724 # CPI: cycles per instruction system.cpu.ipc 0.740892 # IPC: instructions per cycle -system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id @@ -358,44 +366,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 42 system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27773576 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27773576 # number of overall hits -system.cpu.icache.overall_hits::total 27773576 # number of overall hits +system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits +system.cpu.icache.overall_hits::total 27773574 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.icache.overall_misses::total 803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55308998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55308998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68877.955168 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68877.955168 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,26 +418,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803 system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53368002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53368002 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53368002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53368002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53368002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53368002 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1982677223 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution @@ -438,25 +445,39 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121229632 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1371998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428578994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10264.635484 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976615 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy @@ -487,14 +508,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 15582 # system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71727250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71727250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959621000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 959621000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1031348250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1031348250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1031348250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1031348250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses) @@ -513,14 +534,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,14 +564,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574 system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772683000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772683000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831048000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 831048000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831048000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 831048000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses @@ -559,14 +580,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 946045 # number of replacements system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use @@ -606,12 +627,12 @@ system.cpu.dcache.overall_misses::cpu.inst 988793 # system.cpu.dcache.overall_misses::total 988793 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342585500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2342585500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14252071994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14252071994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14252071994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14252071994 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) @@ -634,12 +655,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14413.605268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14413.605268 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -668,12 +689,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334905750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334905750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293231006 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11293231006 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293231006 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11293231006 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses @@ -684,12 +705,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index dd39737d4..c9174d583 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,110 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026367 # Number of seconds simulated -sim_ticks 26367385000 # Number of ticks simulated -final_tick 26367385000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057713 # Number of seconds simulated +sim_ticks 57712782000 # Number of ticks simulated +final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125019 # Simulator instruction rate (inst/s) -host_op_rate 125641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36388385 # Simulator tick rate (ticks/s) -host_mem_usage 387112 # Number of bytes of host memory used -host_seconds 724.61 # Real time elapsed on the host +host_inst_rate 133015 # Simulator instruction rate (inst/s) +host_op_rate 133677 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84740771 # Simulator tick rate (ticks/s) +host_mem_usage 440040 # Number of bytes of host memory used +host_seconds 681.05 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory -system.physmem.bytes_read::total 992448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44608 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 697 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1691787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35947440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37639227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1691787 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1691787 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1691787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35947440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37639227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15507 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15507 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 992448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 989 # Per bank write bursts -system.physmem.perBankRdBursts::1 884 # Per bank write bursts -system.physmem.perBankRdBursts::2 939 # Per bank write bursts -system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1047 # Per bank write bursts -system.physmem.perBankRdBursts::5 1105 # Per bank write bursts -system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1078 # Per bank write bursts -system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 961 # Per bank write bursts -system.physmem.perBankRdBursts::10 931 # Per bank write bursts -system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 906 # Per bank write bursts -system.physmem.perBankRdBursts::13 864 # Per bank write bursts -system.physmem.perBankRdBursts::14 875 # Per bank write bursts -system.physmem.perBankRdBursts::15 896 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory +system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory +system.physmem.bytes_written::total 73600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory +system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 17490 # Number of read requests accepted +system.physmem.writeReqs 1150 # Number of write requests accepted +system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1094 # Per bank write bursts +system.physmem.perBankRdBursts::1 953 # Per bank write bursts +system.physmem.perBankRdBursts::2 1083 # Per bank write bursts +system.physmem.perBankRdBursts::3 1113 # Per bank write bursts +system.physmem.perBankRdBursts::4 1125 # Per bank write bursts +system.physmem.perBankRdBursts::5 1235 # Per bank write bursts +system.physmem.perBankRdBursts::6 1314 # Per bank write bursts +system.physmem.perBankRdBursts::7 1243 # Per bank write bursts +system.physmem.perBankRdBursts::8 1060 # Per bank write bursts +system.physmem.perBankRdBursts::9 962 # Per bank write bursts +system.physmem.perBankRdBursts::10 1021 # Per bank write bursts +system.physmem.perBankRdBursts::11 923 # Per bank write bursts +system.physmem.perBankRdBursts::12 921 # Per bank write bursts +system.physmem.perBankRdBursts::13 987 # Per bank write bursts +system.physmem.perBankRdBursts::14 1105 # Per bank write bursts +system.physmem.perBankRdBursts::15 1049 # Per bank write bursts +system.physmem.perBankWrBursts::0 72 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 62 # Per bank write bursts +system.physmem.perBankWrBursts::3 19 # Per bank write bursts +system.physmem.perBankWrBursts::4 14 # Per bank write bursts +system.physmem.perBankWrBursts::5 111 # Per bank write bursts +system.physmem.perBankWrBursts::6 193 # Per bank write bursts +system.physmem.perBankWrBursts::7 122 # Per bank write bursts +system.physmem.perBankWrBursts::8 49 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 68 # Per bank write bursts +system.physmem.perBankWrBursts::11 20 # Per bank write bursts +system.physmem.perBankWrBursts::12 15 # Per bank write bursts +system.physmem.perBankWrBursts::13 94 # Per bank write bursts +system.physmem.perBankWrBursts::14 168 # Per bank write bursts +system.physmem.perBankWrBursts::15 110 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26367229500 # Total gap between requests +system.physmem.totGap 57712604500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15507 # Read request sizes (log2) +system.physmem.readPktSize::6 17490 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 9831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1150 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -122,39 +133,39 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -186,74 +197,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 734.553002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 545.014262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 382.702300 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 137 10.16% 10.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 142 10.53% 20.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 57 4.23% 24.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 62 4.60% 29.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 68 5.04% 34.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 2.74% 37.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 2.22% 39.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 2.08% 41.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 788 58.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation -system.physmem.totQLat 76352250 # Total ticks spent queuing -system.physmem.totMemAccLat 367108500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4923.73 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads +system.physmem.totQLat 228948216 # Total ticks spent queuing +system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23673.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 37.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 37.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.29 # Data bus utilization in percentage -system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14147 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1700343.68 # Average gap between requests -system.physmem.pageHitRate 91.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 23819655750 # Time in different power states -system.physmem.memoryStateTime::REF 880360000 # Time in different power states +system.physmem.busUtil 0.16 # Data bus utilization in percentage +system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing +system.physmem.readRowHits 14950 # Number of row buffer hits during reads +system.physmem.writeRowHits 375 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes +system.physmem.avgGap 3096169.77 # Average gap between requests +system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states +system.physmem.memoryStateTime::REF 1927120000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1664500500 # Time in different power states +system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 37639227 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 969 # Transaction distribution -system.membus.trans_dist::ReadResp 969 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 14538 # Transaction distribution -system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31020 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992448 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 18431500 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 17158 # Transaction distribution +system.membus.trans_dist::ReadResp 17158 # Transaction distribution +system.membus.trans_dist::Writeback 1150 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 332 # Transaction distribution +system.membus.trans_dist::ReadExResp 332 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 18642 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 18642 # Request fanout histogram +system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 144905497 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 29708806 # Number of BP lookups -system.cpu.branchPred.condPredicted 24486950 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 848073 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12459505 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12380967 # Number of BTB hits +system.cpu.branchPred.lookups 28272297 # Number of BP lookups +system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.369654 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 77225 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 105 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,238 +376,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 52734771 # number of cpu cycles simulated +system.cpu.numCycles 115425565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15504828 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 141696019 # Number of instructions fetch has processed -system.cpu.fetch.Branches 29708806 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12458192 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 36323119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1712998 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15157439 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 317484 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 52684513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.702798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.249702 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679444 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25447326 48.30% 48.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3927834 7.46% 55.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2643597 5.02% 60.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1975703 3.75% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2124397 4.03% 68.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2942984 5.59% 74.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1825722 3.47% 77.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1288988 2.45% 80.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10507962 19.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 52684513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.563363 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.686956 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11541183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18148303 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18363246 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3783966 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 847815 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4787740 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8797 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133953704 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39951 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 847815 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13130783 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7261973 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 198650 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20259912 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10985380 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 130534992 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3194 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4661957 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 5208173 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 864876 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 151632066 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 568616751 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 140291234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 824 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 44319147 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4700 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4700 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 18678634 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 31297749 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5707560 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2464961 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1558957 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 125335435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8504 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107771373 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34045700 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 86545264 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 286 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 52684513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.045599 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.948200 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15278150 29.00% 29.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10252049 19.46% 48.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8069131 15.32% 63.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6193349 11.76% 75.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6619102 12.56% 88.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3132844 5.95% 94.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1926333 3.66% 97.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 606051 1.15% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 607504 1.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 52684513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 313366 33.84% 33.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 287772 31.08% 64.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 324774 35.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 76600270 71.08% 71.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10764 0.01% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 144 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 193 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25964378 24.09% 95.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5195603 4.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107771373 # Type of FU issued -system.cpu.iq.rate 2.043649 # Inst issue rate -system.cpu.iq.fu_busy_cnt 925939 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008592 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 269171739 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 159396970 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 104914190 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 770 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 346 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 108696926 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 386 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 461125 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued +system.cpu.iq.rate 0.878733 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8821838 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5647 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8949 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 962716 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15326 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 231326 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 847815 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5127616 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 500104 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 125356607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 320162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 31297749 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5707560 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4616 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66442 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 385113 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8949 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 454051 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 452935 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 906986 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106740965 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25734173 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030408 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12668 # number of nop insts executed -system.cpu.iew.exec_refs 30844738 # number of memory reference insts executed -system.cpu.iew.exec_branches 21924000 # Number of branches executed -system.cpu.iew.exec_stores 5110565 # Number of stores executed -system.cpu.iew.exec_rate 2.024110 # Inst execution rate -system.cpu.iew.wb_sent 105227967 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 104914536 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63175597 # num instructions producing a value -system.cpu.iew.wb_consumers 106448562 # num instructions consuming a value +system.cpu.iew.exec_nop 12666 # number of nop insts executed +system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed +system.cpu.iew.exec_branches 20629033 # Number of branches executed +system.cpu.iew.exec_stores 4918889 # Number of stores executed +system.cpu.iew.exec_rate 0.867621 # Inst execution rate +system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59710820 # num instructions producing a value +system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.989476 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.593485 # average fanout of values written-back +system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34317785 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 839389 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 47813008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.904370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.590937 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19048029 39.84% 39.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12579538 26.31% 66.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4065916 8.50% 74.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3224325 6.74% 81.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1531590 3.20% 84.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 701376 1.47% 86.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1004304 2.10% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253211 0.53% 88.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5404719 11.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 47813008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -616,458 +648,490 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction -system.cpu.commit.bw_lim_events 5404719 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 167773978 # The number of ROB reads -system.cpu.rob.rob_writes 255639290 # The number of ROB writes -system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50258 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 217038076 # The number of ROB reads +system.cpu.rob.rob_writes 219583064 # The number of ROB writes +system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.582127 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.582127 # CPI: Total CPI of All Threads -system.cpu.ipc 1.717838 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.717838 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115515398 # number of integer regfile reads -system.cpu.int_regfile_writes 62074294 # number of integer regfile writes -system.cpu.fp_regfile_reads 287 # number of floating regfile reads -system.cpu.fp_regfile_writes 460 # number of floating regfile writes -system.cpu.cc_regfile_reads 391234324 # number of cc regfile reads -system.cpu.cc_regfile_writes 61185455 # number of cc regfile writes -system.cpu.misc_regfile_reads 29410043 # number of misc regfile reads +system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads +system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108123919 # number of integer regfile reads +system.cpu.int_regfile_writes 58738896 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 100 # number of floating regfile writes +system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads +system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes +system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4590653188 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 911002 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 911001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 37393 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 37393 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1448 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839705 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120997056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121043200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121043200 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 320 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888566500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 7.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1205249 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 28370 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424155994 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 624.324849 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15156433 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 721 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 21021.404993 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) +system.cpu.icache.tags.replacements 456 # number of replacements +system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 624.324849 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.304846 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.304846 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 719 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 666 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.351074 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 30315604 # Number of tag accesses -system.cpu.icache.tags.data_accesses 30315604 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 15156433 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15156433 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15156433 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15156433 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15156433 # number of overall hits -system.cpu.icache.overall_hits::total 15156433 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1006 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1006 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1006 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1006 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1006 # number of overall misses -system.cpu.icache.overall_misses::total 1006 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68127998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68127998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68127998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68127998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68127998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68127998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15157439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15157439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15157439 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15157439 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15157439 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15157439 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67721.667992 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67721.667992 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67721.667992 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67721.667992 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 475 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits +system.cpu.icache.overall_hits::total 32315555 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses +system.cpu.icache.overall_misses::total 1024 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 279 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 279 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 279 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 279 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 727 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 727 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 727 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 727 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 727 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 727 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50452500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50452500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50452500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50452500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50452500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50452500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000048 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000048 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000048 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69398.211829 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69398.211829 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10760.665120 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1837803 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15490 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.644480 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.tags.replacements 1672 # number of replacements +system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9918.109380 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 609.591474 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 232.964266 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.302677 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018603 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007110 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.328389 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15490 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1303 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13612 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472717 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15183333 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15183333 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 909994 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 910018 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 22855 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 22855 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54000.343926 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54000.343926 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58386.657102 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54119.378798 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54311.182047 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58386.657102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54119.378798 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54311.182047 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1150 # number of writebacks +system.cpu.l2cache.writebacks::total 1150 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 256 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 418 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 442 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 418 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 442 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 139 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26554 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10286000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 72273751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943572 # number of replacements -system.cpu.dcache.tags.tagsinuse 3673.474741 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28380480 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947668 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.947703 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7812548250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3673.474741 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896844 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896844 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 478 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3177 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 441 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 5486251 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 60432712 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 60432712 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23814120 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23814120 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4557910 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4557910 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 634 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 634 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28372030 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28372030 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28372664 # number of overall hits -system.cpu.dcache.overall_hits::total 28372664 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1184948 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1184948 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 177071 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 177071 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 33 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 33 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1362019 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1362019 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1362052 # number of overall misses -system.cpu.dcache.overall_misses::total 1362052 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14093002232 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14093002232 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8425812922 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8425812922 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 265500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 265500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22518815154 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22518815154 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22518815154 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22518815154 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24999068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24999068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits +system.cpu.dcache.overall_hits::total 18263549 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses +system.cpu.dcache.overall_misses::total 9970085 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 667 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 667 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29734049 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29734049 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29734716 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29734716 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047400 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047400 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037396 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037396 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.049475 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.049475 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002041 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002041 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.045807 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.045807 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.045807 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.045807 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11893.350790 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11893.350790 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47584.375318 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47584.375318 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16533.407503 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16533.407503 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16533.006929 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16533.006929 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 231027 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 44986 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135531 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks -system.cpu.dcache.writebacks::total 942911 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274687 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 274687 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 139679 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 139679 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 414366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 414366 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 414366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 414366 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 910261 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 910261 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 37392 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 37392 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 20 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 20 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947653 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947673 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947673 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10074295509 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10074295509 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254962842 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254962842 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1219250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1219250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11329258351 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11329258351 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11330477601 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11330477601 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036412 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036412 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007897 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007897 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.029985 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.029985 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031871 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11067.480106 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11067.480106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33562.335312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33562.335312 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 60962.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 60962.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11955.070422 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11955.070422 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11956.104691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11956.104691 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks +system.cpu.dcache.writebacks::total 5407164 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index b4b101032..4cbab1671 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000000 # Number of ticks simulated final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1737374 # Simulator instruction rate (inst/s) -host_op_rate 1746027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1038196846 # Simulator tick rate (ticks/s) -host_mem_usage 439336 # Number of bytes of host memory used -host_seconds 52.15 # Real time elapsed on the host +host_inst_rate 2068738 # Simulator instruction rate (inst/s) +host_op_rate 2079040 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1236208278 # Simulator tick rate (ticks/s) +host_mem_usage 428768 # Number of bytes of host memory used +host_seconds 43.80 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 349238802 # Wr system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9978534124 # Throughput (bytes/s) -system.membus.data_through_bus 540247816 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 130287905 # Transaction distribution +system.membus.trans_dist::ReadResp 130291792 # Transaction distribution +system.membus.trans_dist::WriteReq 4734981 # Transaction distribution +system.membus.trans_dist::WriteResp 4734981 # Transaction distribution +system.membus.trans_dist::SoftPFReq 510 # Transaction distribution +system.membus.trans_dist::SoftPFResp 510 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 135031170 # Request fanout histogram +system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 135031170 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 1dc1749e2..cf47ed552 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147041 # Nu sim_ticks 147041218000 # Number of ticks simulated final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1067718 # Simulator instruction rate (inst/s) -host_op_rate 1073024 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1733318334 # Simulator tick rate (ticks/s) -host_mem_usage 449084 # Number of bytes of host memory used -host_seconds 84.83 # Real time elapsed on the host +host_inst_rate 1130471 # Simulator instruction rate (inst/s) +host_op_rate 1136089 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1835190843 # Simulator tick rate (ticks/s) +host_mem_usage 438268 # Number of bytes of host memory used +host_seconds 80.12 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 251576 # In system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 6676767 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 792 # Transaction distribution system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution system.membus.trans_dist::ReadExResp 14548 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 981760 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15340 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15340 # Request fanout histogram system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) @@ -559,7 +567,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 822509400 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution @@ -568,11 +575,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 49ab3ae18..7bd8275ff 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2362566 # Simulator instruction rate (inst/s) -host_op_rate 2362664 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1184221154 # Simulator tick rate (ticks/s) -host_mem_usage 397240 # Number of bytes of host memory used -host_seconds 103.20 # Real time elapsed on the host +host_inst_rate 2069444 # Simulator instruction rate (inst/s) +host_op_rate 2069529 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1037295392 # Simulator tick rate (ticks/s) +host_mem_usage 412436 # Number of bytes of host memory used +host_seconds 117.82 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -37,9 +37,29 @@ system.physmem.bw_write::total 749543606 # Wr system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11438757576 # Throughput (bytes/s) -system.membus.data_through_bus 1397997177 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 326641931 # Transaction distribution +system.membus.trans_dist::ReadResp 326641931 # Transaction distribution +system.membus.trans_dist::WriteReq 22901951 # Transaction distribution +system.membus.trans_dist::WriteResp 22901951 # Transaction distribution +system.membus.trans_dist::SwapReq 3886 # Transaction distribution +system.membus.trans_dist::SwapResp 3886 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 349547768 # Request fanout histogram +system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram +system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 349547768 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 244431648 # number of cpu cycles simulated diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 5300dcfdd..5117716ee 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1070091 # Simulator instruction rate (inst/s) -host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1586487053 # Simulator tick rate (ticks/s) -host_mem_usage 406976 # Number of bytes of host memory used -host_seconds 227.85 # Real time elapsed on the host +host_inst_rate 1379749 # Simulator instruction rate (inst/s) +host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2045576865 # Simulator tick rate (ticks/s) +host_mem_usage 421936 # Number of bytes of host memory used +host_seconds 176.72 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 155623 # In system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 2762444 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1036 # Transaction distribution system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 998592 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15603 # Request fanout histogram system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) @@ -463,7 +471,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution @@ -472,11 +479,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1875719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1875719 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1875719 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 517ef5a2d..7c30be235 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061857 # Nu sim_ticks 61857343500 # Number of ticks simulated final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85967 # Simulator instruction rate (inst/s) -host_op_rate 151374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33658728 # Simulator tick rate (ticks/s) -host_mem_usage 393056 # Number of bytes of host memory used -host_seconds 1837.78 # Real time elapsed on the host +host_inst_rate 115241 # Simulator instruction rate (inst/s) +host_op_rate 202921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45120347 # Simulator tick rate (ticks/s) +host_mem_usage 449832 # Number of bytes of host memory used +host_seconds 1370.94 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Wr system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads -system.physmem.totQLat 130872750 # Total ticks spent queuing -system.physmem.totMemAccLat 700329000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 131010750 # Total ticks spent queuing +system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4309.14 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23059.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s @@ -249,7 +249,6 @@ system.physmem.memoryStateTime::REF 2065440000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 31718918 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1465 # Transaction distribution system.membus.trans_dist::ReadResp 1462 # Transaction distribution system.membus.trans_dist::Writeback 197 # Transaction distribution @@ -258,11 +257,20 @@ system.membus.trans_dist::ReadExResp 28998 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1962048 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30660 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30660 # Request fanout histogram system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks) @@ -574,7 +582,6 @@ system.cpu.cc_regfile_reads 107699117 # nu system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4287758914 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution @@ -583,11 +590,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265229376 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index d0541f8a9..109597618 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1054637 # Simulator instruction rate (inst/s) -host_op_rate 1857047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1127809594 # Simulator tick rate (ticks/s) -host_mem_usage 414920 # Number of bytes of host memory used -host_seconds 149.80 # Real time elapsed on the host +host_inst_rate 1180838 # Simulator instruction rate (inst/s) +host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1262766288 # Simulator tick rate (ticks/s) +host_mem_usage 436624 # Number of bytes of host memory used +host_seconds 133.79 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,33 @@ system.physmem.bw_write::total 1439319677 # Wr system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 15992825110 # Throughput (bytes/s) -system.membus.data_through_bus 2701988442 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 308475611 # Transaction distribution +system.membus.trans_dist::ReadResp 308475611 # Transaction distribution +system.membus.trans_dist::WriteReq 31439752 # Transaction distribution +system.membus.trans_dist::WriteResp 31439752 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 339915363 # Request fanout histogram +system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram +system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 339915363 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 917c42379..deb1ad7af 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 596728 # Simulator instruction rate (inst/s) -host_op_rate 1050742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1382352440 # Simulator tick rate (ticks/s) -host_mem_usage 424660 # Number of bytes of host memory used -host_seconds 264.76 # Real time elapsed on the host +host_inst_rate 756908 # Simulator instruction rate (inst/s) +host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1753418925 # Simulator tick rate (ticks/s) +host_mem_usage 446124 # Number of bytes of host memory used +host_seconds 208.73 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 17487 # To system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 5272114 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1025 # Transaction distribution system.membus.trans_dist::ReadResp 1025 # Transaction distribution system.membus.trans_dist::Writeback 100 # Transaction distribution @@ -45,11 +44,20 @@ system.membus.trans_dist::ReadExResp 29024 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1929536 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30149 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30149 # Request fanout histogram system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) @@ -457,7 +465,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution @@ -466,11 +473,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) |