diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long/se/10.mcf/ref | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long/se/10.mcf/ref')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 760 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1636 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1610 |
3 files changed, 2003 insertions, 2003 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index bf75cb6d5..69b672058 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062553 # Number of seconds simulated -sim_ticks 62553193500 # Number of ticks simulated -final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062555 # Number of seconds simulated +sim_ticks 62555455500 # Number of ticks simulated +final_tick 62555455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 434587 # Simulator instruction rate (inst/s) -host_op_rate 436752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 300043763 # Simulator tick rate (ticks/s) -host_mem_usage 405580 # Number of bytes of host memory used -host_seconds 208.48 # Real time elapsed on the host +host_inst_rate 428742 # Simulator instruction rate (inst/s) +host_op_rate 430877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 296018745 # Simulator tick rate (ticks/s) +host_mem_usage 404460 # Number of bytes of host memory used +host_seconds 211.32 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory -system.physmem.bytes_read::total 996736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 996800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15574 # Number of read requests accepted +system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 791873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15142788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15934661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 791873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 791873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 791873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15142788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15934661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side +system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,7 +48,7 @@ system.physmem.perBankRdBursts::2 949 # Pe system.physmem.perBankRdBursts::3 1027 # Per bank write bursts system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1113 # Per bank write bursts -system.physmem.perBankRdBursts::6 1087 # Per bank write bursts +system.physmem.perBankRdBursts::6 1088 # Per bank write bursts system.physmem.perBankRdBursts::7 1088 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62553092500 # Total gap between requests +system.physmem.totGap 62555354500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15574 # Read request sizes (log2) +system.physmem.readPktSize::6 15575 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15455 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 437.476336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.605762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.465548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.658643 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 178 11.56% 28.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 79 5.13% 33.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 177 11.49% 28.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 80 5.19% 33.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.60% 50.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 4.35% 55.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 211075250 # Total ticks spent queuing -system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst +system.physmem.totQLat 211097500 # Total ticks spent queuing +system.physmem.totMemAccLat 503128750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13553.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32303.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s @@ -217,66 +217,66 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14027 # Number of row buffer hits during reads +system.physmem.readRowHits 14028 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4016507.80 # Average gap between requests +system.physmem.avgGap 4016395.15 # Average gap between requests system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 58540860 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ) -system.physmem_0.averagePower 252.612326 # Core power per rank (mW) -system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 136590240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8764320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 737385060 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 211641120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14429375100 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15802368780 # Total energy per rank (pJ) +system.physmem_0.averagePower 252.613756 # Core power per rank (mW) +system.physmem_0.totalIdleTime 62232966250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states +system.physmem_0.memoryStateTime::SREF 60064867500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 551102250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 223150500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1617057250 # Time in different power states system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ) -system.physmem_1.averagePower 254.503484 # Core power per rank (mW) -system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 136410120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13262400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 827323080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 248273280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14377994265 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15920556885 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.503090 # Core power per rank (mW) +system.physmem_1.totalIdleTime 62220218000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 20808248 # Number of BP lookups -system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8965663 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8840828 # Number of BTB hits +system.physmem_1.memoryStateTime::SREF 59760759500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 646525750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 203991750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1814347500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 20806620 # Number of BP lookups +system.cpu.branchPred.condPredicted 17114048 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 756880 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8968258 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8843232 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.607632 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.605905 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 61975 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectHits 24793 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1418 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 666 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 125106387 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 125110911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2181045 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.380822 # CPI: cycles per instruction -system.cpu.ipc 0.724206 # IPC: instructions per cycle +system.cpu.cpi 1.380872 # CPI: cycles per instruction +system.cpu.ipc 0.724180 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -446,60 +446,60 @@ system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy +system.cpu.tickCycles 110528679 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14582232 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 946104 # number of replacements +system.cpu.dcache.tags.tagsinuse 3621.120784 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274613 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950200 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.651666 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20754332500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.120784 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.884063 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.884063 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2202 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2198 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1666 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55461064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55461064 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605665 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605665 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660666 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660666 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits -system.cpu.dcache.overall_hits::total 26266955 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26266331 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266331 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26266839 # number of overall hits +system.cpu.dcache.overall_hits::total 26266839 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906500 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906500 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74315 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses -system.cpu.dcache.overall_misses::total 980814 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 980815 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980815 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980819 # number of overall misses +system.cpu.dcache.overall_misses::total 980819 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832236000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11832236000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760278000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2760278000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14592514000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14592514000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14592514000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14592514000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22512165 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22512165 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -508,10 +508,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27247257 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27247146 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27247146 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27247658 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27247658 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses @@ -522,50 +522,50 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.659680 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.659680 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.945570 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.945570 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.947421 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14877.947421 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.886746 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14877.886746 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks -system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks +system.cpu.dcache.writebacks::total 943285 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3067 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3067 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27551 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27551 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30618 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30618 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30618 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30618 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 950197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950200 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950200 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889912000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889912000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596274500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596274500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12486186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486356500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12486356500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -574,73 +574,73 @@ system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034873 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.923202 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.923202 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34134.686939 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34134.686939 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.629259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.629259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.766681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.766681 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.583421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27839479 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34712.567332 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 689.583421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336711 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336711 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27835083 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27835083 # number of overall hits -system.cpu.icache.overall_hits::total 27835083 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 801 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 89053.615960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,132 +649,132 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 5 # number of writebacks system.cpu.icache.writebacks::total 5 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 801 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.588306 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.516821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324509 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15575 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # 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number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903433 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 903433 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 950197 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950998 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 801 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 951002 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966292 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966292 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966334 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966334 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966334 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966334 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81293.557481 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81293.557481 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89172.903226 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89172.903226 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187220.532319 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187220.532319 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83473.334617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83473.334617 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,122 +793,122 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 6 system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 774 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 774 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036893500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036893500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61295500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61295500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46236000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46236000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61295500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1144425000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61295500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083129500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1144425000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71293.557481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71293.557481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79193.152455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79193.152455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179906.614786 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179906.614786 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1897111 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 946125 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 943285 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2848102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121234240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903436 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2848113 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 950998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 951002 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 950832 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950836 99.98% 99.98% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 951002 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891845500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1203499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1425302994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 15575 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1030 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1031 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1031 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 15574 # Request fanout histogram +system.membus.snoop_fanout::samples 15575 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 15575 # Request fanout histogram +system.membus.reqLayer0.occupancy 21782500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82144500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 2da35dc4f..e99ff0d50 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058681 # Number of seconds simulated -sim_ticks 58681066500 # Number of ticks simulated -final_tick 58681066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058521 # Number of seconds simulated +sim_ticks 58521086000 # Number of ticks simulated +final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243006 # Simulator instruction rate (inst/s) -host_op_rate 244216 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 157411271 # Simulator tick rate (ticks/s) -host_mem_usage 492224 # Number of bytes of host memory used -host_seconds 372.79 # Real time elapsed on the host +host_inst_rate 243648 # Simulator instruction rate (inst/s) +host_op_rate 244862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157397000 # Simulator tick rate (ticks/s) +host_mem_usage 492140 # Number of bytes of host memory used +host_seconds 371.81 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 219520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 922368 # Number of bytes read from this memory -system.physmem.bytes_read::total 1186688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6784 # Number of bytes written to this memory -system.physmem.bytes_written::total 6784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3430 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18542 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 106 # Number of write requests responded to by this memory -system.physmem.num_writes::total 106 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 763449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3740900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15718324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20222673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 763449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 763449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 115608 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 115608 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 115608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 763449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3740900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15718324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20338281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18543 # Number of read requests accepted -system.physmem.writeReqs 106 # Number of write requests accepted -system.physmem.readBursts 18543 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 106 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1180544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1186752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory +system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory +system.physmem.bytes_written::total 4736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory +system.physmem.num_writes::total 74 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18546 # Number of read requests accepted +system.physmem.writeReqs 74 # Number of write requests accepted +system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue +system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 3245 # Per bank write bursts -system.physmem.perBankRdBursts::1 921 # Per bank write bursts -system.physmem.perBankRdBursts::2 954 # Per bank write bursts +system.physmem.perBankRdBursts::0 3297 # Per bank write bursts +system.physmem.perBankRdBursts::1 920 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::4 1067 # Per bank write bursts +system.physmem.perBankRdBursts::5 1119 # Per bank write bursts system.physmem.perBankRdBursts::6 1093 # Per bank write bursts -system.physmem.perBankRdBursts::7 1100 # Per bank write bursts +system.physmem.perBankRdBursts::7 1097 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 933 # Per bank write bursts +system.physmem.perBankRdBursts::9 961 # Per bank write bursts +system.physmem.perBankRdBursts::10 934 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::12 902 # Per bank write bursts system.physmem.perBankRdBursts::13 895 # Per bank write bursts -system.physmem.perBankRdBursts::14 1401 # Per bank write bursts -system.physmem.perBankRdBursts::15 904 # Per bank write bursts -system.physmem.perBankWrBursts::0 2 # Per bank write bursts +system.physmem.perBankRdBursts::14 1399 # Per bank write bursts +system.physmem.perBankRdBursts::15 903 # Per bank write bursts +system.physmem.perBankWrBursts::0 1 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 2 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 12 # Per bank write bursts -system.physmem.perBankWrBursts::5 8 # Per bank write bursts -system.physmem.perBankWrBursts::6 10 # Per bank write bursts -system.physmem.perBankWrBursts::7 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 1 # Per bank write bursts +system.physmem.perBankWrBursts::5 14 # Per bank write bursts +system.physmem.perBankWrBursts::6 9 # Per bank write bursts +system.physmem.perBankWrBursts::7 3 # Per bank write bursts system.physmem.perBankWrBursts::8 1 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 1 # Per bank write bursts +system.physmem.perBankWrBursts::10 2 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 5 # Per bank write bursts +system.physmem.perBankWrBursts::12 1 # Per bank write bursts system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 8 # Per bank write bursts -system.physmem.perBankWrBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::14 5 # Per bank write bursts +system.physmem.perBankWrBursts::15 1 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58681058000 # Total gap between requests +system.physmem.totGap 58521077500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18543 # Read request sizes (log2) +system.physmem.readPktSize::6 18546 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 106 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 316 # What read queue length does an incoming req see +system.physmem.writePktSize::6 74 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -149,24 +149,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -198,109 +198,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 398.104980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.970166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.874685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 839 28.23% 28.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 987 33.21% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89 2.99% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 64 2.15% 66.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 64 2.15% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 65 2.19% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 54 1.82% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 55 1.85% 74.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 755 25.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2972 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4544.500000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 1447.547305 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7502.381200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.physmem.totQLat 829373528 # Total ticks spent queuing -system.physmem.totMemAccLat 1175236028 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44962.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads +system.physmem.totQLat 837911216 # Total ticks spent queuing +system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63712.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.16 # Data bus utilization in percentage system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.34 # Average write queue length when enqueuing -system.physmem.readRowHits 15527 # Number of row buffer hits during reads -system.physmem.writeRowHits 11 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.00 # Row buffer hit rate for writes -system.physmem.avgGap 3146606.15 # Average gap between requests -system.physmem.pageHitRate 83.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15943620 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8459055 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 75134220 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 203580 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1849451760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 458311920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 99516480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 3997068570 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3182851200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 10077393330 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19767987555 # Total energy per rank (pJ) -system.physmem_0.averagePower 336.871642 # Core power per rank (mW) -system.physmem_0.totalIdleTime 57408712347 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 196273000 # Time in different power states -system.physmem_0.memoryStateTime::REF 786774000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 40354533250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8288648060 # Time in different power states -system.physmem_0.memoryStateTime::ACT 289307153 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 8765531037 # Time in different power states -system.physmem_1.actEnergy 5333580 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2819685 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 56563080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 172260 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 259378080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 131548590 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 14205120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 785395590 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 262919520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 13470232590 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14988765045 # Total energy per rank (pJ) -system.physmem_1.averagePower 255.427603 # Core power per rank (mW) -system.physmem_1.totalIdleTime 58353780091 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 23548250 # Time in different power states -system.physmem_1.memoryStateTime::REF 110212000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 55948105250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 684663397 # Time in different power states -system.physmem_1.memoryStateTime::ACT 192205159 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1722332444 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28234239 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266690 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835421 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829840 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11748052 # Number of BTB hits +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing +system.physmem.readRowHits 15512 # Number of row buffer hits during reads +system.physmem.writeRowHits 18 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes +system.physmem.avgGap 3142915.01 # Average gap between requests +system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ) +system.physmem_0.averagePower 339.947098 # Core power per rank (mW) +system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states +system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states +system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states +system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.906533 # Core power per rank (mW) +system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states +system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states +system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28121660 # Number of BP lookups +system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.308630 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74543 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27224 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25476 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1748 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,240 +423,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117362134 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117042173 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746504 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134908625 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28234239 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11848071 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115710996 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674249 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 948 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275841 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117296446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.155292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.317650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59759710 50.95% 50.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13934020 11.88% 62.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230571 7.87% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34372145 29.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117296446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.240574 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.149507 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8834504 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 65062525 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33013030 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9560979 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825408 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097904 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114396314 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1984657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825408 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15270391 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50319403 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 113009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35408802 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15359433 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110873352 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412133 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11133960 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1550028 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2088318 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 507009 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129946854 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483157007 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119448195 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22633935 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21513701 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805540 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347415 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 519015 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 253842 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109668195 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366364 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074602 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18635448 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41675725 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117296446 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.864190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988217 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55661536 47.45% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31364227 26.74% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008293 18.76% 92.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7064324 6.02% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197751 1.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 315 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117296446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9780929 48.66% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614642 47.84% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702971 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970702 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 57 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337480 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047270 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366364 # Type of FU issued -system.cpu.iq.rate 0.863706 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20098632 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198277 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 341201935 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128312613 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99607782 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 473 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121464746 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288157 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued +system.cpu.iq.rate 0.865106 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329629 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1502 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602571 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130792 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825408 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8297291 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 773487 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109689301 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805540 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347415 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182523 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 427569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435014 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412394 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847408 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100110032 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1256332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12823 # number of nop insts executed -system.cpu.iew.exec_refs 28718949 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621210 # Number of branches executed -system.cpu.iew.exec_stores 4915786 # Number of stores executed -system.cpu.iew.exec_rate 0.853001 # Inst execution rate -system.cpu.iew.wb_sent 99693474 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99607900 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59692176 # num instructions producing a value -system.cpu.iew.wb_consumers 95528763 # num instructions consuming a value -system.cpu.iew.wb_rate 0.848723 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624861 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17363908 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed +system.cpu.iew.exec_branches 20644390 # Number of branches executed +system.cpu.iew.exec_stores 4947526 # Number of stores executed +system.cpu.iew.exec_rate 0.854978 # Inst execution rate +system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59603520 # num instructions producing a value +system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value +system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 114608461 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.794476 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.731976 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78183874 68.22% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18612814 16.24% 84.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7153278 6.24% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469165 3.03% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644308 1.43% 95.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541542 0.47% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703493 0.61% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179022 0.16% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120965 3.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 114608461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,80 +706,80 @@ system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120965 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218899309 # The number of ROB reads -system.cpu.rob.rob_writes 219523661 # The number of ROB writes -system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65688 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218426787 # The number of ROB reads +system.cpu.rob.rob_writes 219173124 # The number of ROB writes +system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.295534 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.295534 # CPI: Total CPI of All Threads -system.cpu.ipc 0.771883 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.771883 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108098001 # number of integer regfile reads -system.cpu.int_regfile_writes 58691976 # number of integer regfile writes +system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads +system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108095256 # number of integer regfile reads +system.cpu.int_regfile_writes 58597145 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 98 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004563 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686890 # number of cc regfile writes -system.cpu.misc_regfile_reads 28409682 # number of misc regfile reads +system.cpu.fp_regfile_writes 127 # number of floating regfile writes +system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads +system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes +system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 5470632 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.769242 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249828 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335651 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38122500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.769242 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61906996 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61906996 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887361 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887361 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4354163 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4354163 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241524 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18242046 # number of overall hits -system.cpu.dcache.overall_hits::total 18242046 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587281 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587281 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 380818 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 380818 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits +system.cpu.dcache.overall_hits::total 18235318 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968099 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968099 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968106 # number of overall misses -system.cpu.dcache.overall_misses::total 9968106 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89375617500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89375617500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4089956224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4089956224 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses +system.cpu.dcache.overall_misses::total 9969606 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93465573724 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93465573724 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93465573724 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93465573724 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474642 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474642 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -786,475 +788,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210152 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210152 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080427 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080427 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353358 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353358 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353352 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353352 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.311248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.311248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10739.923596 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10739.923596 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9376.469247 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9376.469247 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9376.462662 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9376.462662 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331655 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 128757 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121530 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.728997 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.027804 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks system.cpu.dcache.writebacks::total 5470632 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338725 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338725 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158229 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158229 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496954 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496954 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496954 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248556 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248556 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222589 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222589 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43819499500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43819499500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2297613115 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2297613115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46117112615 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46117112615 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46117348115 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46117348115 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223584 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223584 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047009 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047009 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.867670 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.867670 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10322.222190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10322.222190 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.151963 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.151963 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.188844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.188844 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 448 # number of replacements -system.cpu.icache.tags.tagsinuse 427.601453 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32274679 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35623.266004 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 449 # number of replacements +system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.601453 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835159 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.833706 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64552564 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64552564 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32274679 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32274679 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32274679 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32274679 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32274679 # number of overall hits -system.cpu.icache.overall_hits::total 32274679 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1150 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1150 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1150 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1150 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1150 # number of overall misses -system.cpu.icache.overall_misses::total 1150 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 79102980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 79102980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 79102980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 79102980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 79102980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 79102980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275829 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64174375 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64174375 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32085580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32085580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32085580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32085580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32085580 # number of overall hits +system.cpu.icache.overall_hits::total 32085580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81624480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81624480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81624480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81624480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81624480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32086734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32086734 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32086734 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32086734 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32086734 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68785.200000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68785.200000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68785.200000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68785.200000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21255 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 760 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 230 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.413043 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 126.666667 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 448 # number of writebacks -system.cpu.icache.writebacks::total 448 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60408984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 60408984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60408984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 60408984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60408984 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 60408984 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70731.785095 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21770 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1853 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 449 # number of writebacks +system.cpu.icache.writebacks::total 449 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 246 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61609984 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66603.069460 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66603.069460 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3398 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9680 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 832 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003906 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884705 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180526200 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180526200 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180525307 # 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number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 3123 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3622 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4323 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3622 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21300 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21300 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127617.764471 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127617.764471 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82794.159544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82794.159544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198613.694676 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198613.694676 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 106 # number of writebacks -system.cpu.l2cache.writebacks::total 106 # number of writebacks +system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks +system.cpu.l2cache.writebacks::total 74 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001517 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001517 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000589 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000589 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000755 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058618 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3434.482939 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 132970.845481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 132970.845481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76825.249643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76825.249643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 191433.937824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 191433.937824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167137.342691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5543.287704 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943136 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471098 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2874 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 302216 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302215 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245880 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5457301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318509 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226170 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226170 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244974 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415197 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318663 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7168 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790713 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052689 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223412 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318326 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485610 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305102 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790713 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942648026 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1361495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18697 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3032 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18200 # Transaction distribution -system.membus.trans_dist::WritebackDirty 106 # Transaction distribution -system.membus.trans_dist::CleanEvict 42 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18205 # Transaction distribution +system.membus.trans_dist::WritebackDirty 74 # Transaction distribution +system.membus.trans_dist::CleanEvict 25 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 342 # Transaction distribution -system.membus.trans_dist::ReadExResp 342 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18201 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37239 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1193472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1193472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18549 # Request fanout histogram +system.membus.snoop_fanout::samples 18552 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18549 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18552 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18549 # Request fanout histogram -system.membus.reqLayer0.occupancy 29669004 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 18552 # Request fanout histogram +system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97336094 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 716a9adc9..8690264ef 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065833 # Number of seconds simulated -sim_ticks 65832730500 # Number of ticks simulated -final_tick 65832730500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065721 # Number of seconds simulated +sim_ticks 65721494500 # Number of ticks simulated +final_tick 65721494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190384 # Simulator instruction rate (inst/s) -host_op_rate 335236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79331786 # Simulator tick rate (ticks/s) -host_mem_usage 416808 # Number of bytes of host memory used -host_seconds 829.84 # Real time elapsed on the host +host_inst_rate 191999 # Simulator instruction rate (inst/s) +host_op_rate 338080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79869594 # Simulator tick rate (ticks/s) +host_mem_usage 415448 # Number of bytes of host memory used +host_seconds 822.86 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69952 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory -system.physmem.bytes_read::total 1962496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory -system.physmem.bytes_written::total 19776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1093 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19136 # Number of bytes written to this memory +system.physmem.bytes_written::total 19136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30664 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory -system.physmem.num_writes::total 309 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1062572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28747767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29810339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1062572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1062572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 300398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 300398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 300398 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1062572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28747767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30110736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30664 # Number of read requests accepted -system.physmem.writeReqs 309 # Number of write requests accepted -system.physmem.readBursts 30664 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1954304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 18368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1962496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 299 # Number of write requests responded to by this memory +system.physmem.num_writes::total 299 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1046842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28796424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29843265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1046842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1046842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 291168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 291168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 291168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1046842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28796424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30134433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30646 # Number of read requests accepted +system.physmem.writeReqs 299 # Number of write requests accepted +system.physmem.readBursts 30646 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 299 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 17216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1961344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1947 # Per bank write bursts -system.physmem.perBankRdBursts::1 2076 # Per bank write bursts -system.physmem.perBankRdBursts::2 2053 # Per bank write bursts -system.physmem.perBankRdBursts::3 1954 # Per bank write bursts -system.physmem.perBankRdBursts::4 2067 # Per bank write bursts +system.physmem.perBankRdBursts::0 1937 # Per bank write bursts +system.physmem.perBankRdBursts::1 2081 # Per bank write bursts +system.physmem.perBankRdBursts::2 2039 # Per bank write bursts +system.physmem.perBankRdBursts::3 1941 # Per bank write bursts +system.physmem.perBankRdBursts::4 2068 # Per bank write bursts system.physmem.perBankRdBursts::5 1911 # Per bank write bursts -system.physmem.perBankRdBursts::6 1975 # Per bank write bursts -system.physmem.perBankRdBursts::7 1868 # Per bank write bursts -system.physmem.perBankRdBursts::8 1952 # Per bank write bursts -system.physmem.perBankRdBursts::9 1938 # Per bank write bursts +system.physmem.perBankRdBursts::6 1977 # Per bank write bursts +system.physmem.perBankRdBursts::7 1878 # Per bank write bursts +system.physmem.perBankRdBursts::8 1945 # Per bank write bursts +system.physmem.perBankRdBursts::9 1939 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts -system.physmem.perBankRdBursts::13 1799 # Per bank write bursts -system.physmem.perBankRdBursts::14 1826 # Per bank write bursts +system.physmem.perBankRdBursts::13 1800 # Per bank write bursts +system.physmem.perBankRdBursts::14 1827 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 25 # Per bank write bursts -system.physmem.perBankWrBursts::1 120 # Per bank write bursts -system.physmem.perBankWrBursts::2 28 # Per bank write bursts -system.physmem.perBankWrBursts::3 32 # Per bank write bursts +system.physmem.perBankWrBursts::0 8 # Per bank write bursts +system.physmem.perBankWrBursts::1 125 # Per bank write bursts +system.physmem.perBankWrBursts::2 25 # Per bank write bursts +system.physmem.perBankWrBursts::3 26 # Per bank write bursts system.physmem.perBankWrBursts::4 54 # Per bank write bursts -system.physmem.perBankWrBursts::5 2 # Per bank write bursts -system.physmem.perBankWrBursts::6 17 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::6 14 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 6 # Per bank write bursts @@ -83,28 +83,28 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65832525500 # Total gap between requests +system.physmem.totGap 65721290500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30664 # Read request sizes (log2) +system.physmem.readPktSize::6 30646 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 299 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -145,14 +145,14 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see @@ -160,18 +160,18 @@ system.physmem.wrQLenPdf::26 16 # Wh system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,355 +194,353 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 688.995108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 484.121076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 395.829774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 415 14.50% 14.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 275 9.61% 24.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 149 5.21% 29.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 128 4.47% 33.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 140 4.89% 38.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 122 4.26% 42.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 77 2.69% 45.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 86 3.00% 48.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1470 51.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2862 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1905.625000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 24.516989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7552.373489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 15 93.75% 93.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 6.25% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.937500 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.914548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.928709 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 12 75.00% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 6.25% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 411710000 # Total ticks spent queuing -system.physmem.totMemAccLat 984260000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152680000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13482.77 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2852 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 690.064516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 482.522488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 397.377699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2852 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 15 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2030.466667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.801531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7801.447410 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 15 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 15 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.933333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.931540 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.258199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 6.67% 6.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 14 93.33% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 15 # Writes before turning the bus around for reads +system.physmem.totQLat 402617750 # Total ticks spent queuing +system.physmem.totMemAccLat 974736500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13194.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32232.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.69 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.28 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31944.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.03 # Average write queue length when enqueuing -system.physmem.readRowHits 27751 # Number of row buffer hits during reads -system.physmem.writeRowHits 206 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 2125481.08 # Average gap between requests -system.physmem.pageHitRate 90.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11059860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5878455 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 113176140 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1451160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 315310320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 256763340 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 17698560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 981638610 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 270128640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15008515620 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 16981623105 # Total energy per rank (pJ) -system.physmem_0.averagePower 257.950589 # Core power per rank (mW) -system.physmem_0.totalIdleTime 65223686000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 24830750 # Time in different power states -system.physmem_0.memoryStateTime::REF 133713250 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62367507500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 703478750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 450500500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 2152699750 # Time in different power states -system.physmem_1.actEnergy 9403380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4982835 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 104850900 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 12.51 # Average write queue length when enqueuing +system.physmem.readRowHits 27734 # Number of row buffer hits during reads +system.physmem.writeRowHits 187 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.54 # Row buffer hit rate for writes +system.physmem.avgGap 2123809.68 # Average gap between requests +system.physmem.pageHitRate 90.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11052720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5855685 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 113040480 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1357200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 309163920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 263324610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 16569120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 979073610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 268447200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14975920920 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 16943805465 # Total energy per rank (pJ) +system.physmem_0.averagePower 257.812234 # Core power per rank (mW) +system.physmem_0.totalIdleTime 65100637750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 22061500 # Time in different power states +system.physmem_0.memoryStateTime::REF 131194000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62254705500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 699065250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 467433500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 2147034750 # Time in different power states +system.physmem_1.actEnergy 9374820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4967655 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 104822340 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 389067120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 256987920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 20546880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1156119600 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 409490400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14841811380 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17194149375 # Total energy per rank (pJ) -system.physmem_1.averagePower 261.179341 # Core power per rank (mW) -system.physmem_1.totalIdleTime 65212352000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 31901000 # Time in different power states -system.physmem_1.memoryStateTime::REF 165222000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 61612056250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1066374000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 421666750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2535510500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40426123 # Number of BP lookups -system.cpu.branchPred.condPredicted 40426123 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1402729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26580139 # Number of BTB lookups +system.physmem_1.refreshEnergy 372471840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 249536310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 19488480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1119740490 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 403290240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14835337125 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17119488570 # Total energy per rank (pJ) +system.physmem_1.averagePower 260.485370 # Core power per rank (mW) +system.physmem_1.totalIdleTime 65120969250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 28589000 # Time in different power states +system.physmem_1.memoryStateTime::REF 158136000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 61616793750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1050209250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 412212500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2455554000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40406290 # Number of BP lookups +system.cpu.branchPred.condPredicted 40406290 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1431845 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26031629 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6011508 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 87453 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26580139 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21161652 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5418487 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 517301 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 6025963 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 91921 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26031629 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 20992529 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5039100 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 530263 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131665462 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131442990 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30553171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219967171 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40426123 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27173160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99460538 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2919977 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 306 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5927 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 105822 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 73 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 157 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29763575 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 354176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 15 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131585982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.941987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30464048 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219898668 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40406290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27018492 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99269738 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2979935 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 465 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 128961 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29660171 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 359072 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 17 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131360995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.946103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.409063 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65985920 50.15% 50.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4028379 3.06% 53.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3611314 2.74% 55.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6113229 4.65% 60.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7745533 5.89% 66.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5553246 4.22% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3377028 2.57% 73.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2847646 2.16% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32323687 24.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65827184 50.11% 50.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4032527 3.07% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3600376 2.74% 55.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6081929 4.63% 60.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7728911 5.88% 66.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5535416 4.21% 70.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3331669 2.54% 73.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2842658 2.16% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32380325 24.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131585982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307037 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.670652 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15243618 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64765794 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40224064 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9892518 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1459988 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 362269877 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1459988 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20789530 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11237370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18362 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44279240 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53801492 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 352719757 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 793095 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46882908 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5193491 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 355158766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934950269 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 575705414 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 24139 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131360995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307405 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.672959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15255907 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64520496 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40208811 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9885814 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1489967 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 362265652 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1489967 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20796133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11129664 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23832 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44255424 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53665975 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352608748 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23342 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 777450 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46732943 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5205031 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 354925639 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 934456502 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575559102 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 21159 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 75946019 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 487 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 484 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64820498 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112428453 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38501164 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51645718 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9056873 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344114716 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4351 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 317908509 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166833 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65926603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 102202913 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131585982 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.415976 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.164934 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75712892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 482 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 483 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64647332 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112313472 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38475522 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51426374 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8868395 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343765046 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3883 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317634440 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 163759 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65576465 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 101836454 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3438 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131360995 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.418027 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.167913 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35686444 27.12% 27.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20105227 15.28% 42.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17162197 13.04% 55.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17623881 13.39% 68.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15350950 11.67% 80.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12863479 9.78% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6692822 5.09% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4078738 3.10% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2022244 1.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131585982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131360995 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 364988 8.91% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3541451 86.44% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 188937 4.61% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 10 0.00% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1524 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181836417 57.20% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11458 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 362 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 334 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101309174 31.87% 89.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34711229 10.92% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 553 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 5642 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 317908509 # Type of FU issued -system.cpu.iq.rate 2.414517 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4096910 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012887 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 771648435 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410069961 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 313720076 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18308 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321964016 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8063 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57535034 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317634440 # Type of FU issued +system.cpu.iq.rate 2.416519 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4120029 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012971 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770896978 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 409373525 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313389776 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16685 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 31480 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3775 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321713926 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7204 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57497351 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21649068 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67666 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 63141 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7061412 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21534087 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66072 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 62227 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7035770 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4025 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141941 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4204 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141777 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1459988 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8072611 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3068372 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344119067 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 127232 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112428453 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38501164 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2921 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3074772 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 63141 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 534039 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1041947 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1575986 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 315496434 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100557512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2412075 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1489967 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8057522 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2987683 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343768929 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139556 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112313472 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38475522 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1604 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2862 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2991864 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 62227 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 520614 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1090823 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1611437 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315197484 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100490397 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2436956 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134869578 # number of memory reference insts executed -system.cpu.iew.exec_branches 32108537 # Number of branches executed -system.cpu.iew.exec_stores 34312066 # Number of stores executed -system.cpu.iew.exec_rate 2.396197 # Inst execution rate -system.cpu.iew.wb_sent 314359591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 313724392 # cumulative count of insts written-back -system.cpu.iew.wb_producers 237724315 # num instructions producing a value -system.cpu.iew.wb_consumers 343443925 # num instructions consuming a value -system.cpu.iew.wb_rate 2.382739 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692178 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 66051294 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134782236 # number of memory reference insts executed +system.cpu.iew.exec_branches 32089039 # Number of branches executed +system.cpu.iew.exec_stores 34291839 # Number of stores executed +system.cpu.iew.exec_rate 2.397979 # Inst execution rate +system.cpu.iew.wb_sent 314036708 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313393551 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237399400 # num instructions producing a value +system.cpu.iew.wb_consumers 342887037 # num instructions consuming a value +system.cpu.iew.wb_rate 2.384255 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692355 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 65692241 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1408834 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122136825 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.277712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.048100 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1439325 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121896437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.282203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.051706 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57021615 46.69% 46.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16508640 13.52% 60.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11210798 9.18% 69.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8746505 7.16% 76.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2078517 1.70% 78.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1759712 1.44% 79.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 926228 0.76% 80.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 725763 0.59% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23159047 18.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56939574 46.71% 46.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122136825 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 121896437 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -592,466 +590,466 @@ system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23159047 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 443221536 # The number of ROB reads -system.cpu.rob.rob_writes 698006714 # The number of ROB writes -system.cpu.timesIdled 877 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79480 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23179490 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 442601652 # The number of ROB reads +system.cpu.rob.rob_writes 697313320 # The number of ROB writes +system.cpu.timesIdled 909 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 81995 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.833386 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.833386 # CPI: Total CPI of All Threads -system.cpu.ipc 1.199924 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.199924 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 502917784 # number of integer regfile reads -system.cpu.int_regfile_writes 247848787 # number of integer regfile writes -system.cpu.fp_regfile_reads 4075 # number of floating regfile reads -system.cpu.fp_regfile_writes 819 # number of floating regfile writes -system.cpu.cc_regfile_reads 109098841 # number of cc regfile reads -system.cpu.cc_regfile_writes 65494445 # number of cc regfile writes -system.cpu.misc_regfile_reads 201957201 # number of misc regfile reads +system.cpu.cpi 0.831978 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.831978 # CPI: Total CPI of All Threads +system.cpu.ipc 1.201955 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.201955 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502529726 # number of integer regfile reads +system.cpu.int_regfile_writes 247564665 # number of integer regfile writes +system.cpu.fp_regfile_reads 3566 # number of floating regfile reads +system.cpu.fp_regfile_writes 731 # number of floating regfile writes +system.cpu.cc_regfile_reads 108994485 # number of cc regfile reads +system.cpu.cc_regfile_writes 65428204 # number of cc regfile writes +system.cpu.misc_regfile_reads 201784346 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073306 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.354566 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71520008 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077402 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.427621 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21024099500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.354566 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993006 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993006 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073509 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.268199 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71482624 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077605 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.406263 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21075173500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992985 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 500 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3447 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 504 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150691296 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150691296 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40173982 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40173982 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31346026 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31346026 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71520008 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71520008 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71520008 # number of overall hits -system.cpu.dcache.overall_hits::total 71520008 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93726 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93726 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2786939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2786939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2786939 # number of overall misses -system.cpu.dcache.overall_misses::total 2786939 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32416728500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32416728500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3181034987 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3181034987 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35597763487 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35597763487 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35597763487 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35597763487 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42867195 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42867195 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150633517 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150633517 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40136683 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40136683 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345941 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345941 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71482624 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71482624 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71482624 # number of overall hits +system.cpu.dcache.overall_hits::total 71482624 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2701521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2701521 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93811 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93811 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2795332 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795332 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795332 # number of overall misses +system.cpu.dcache.overall_misses::total 2795332 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32454671000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3177582491 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35632253491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35632253491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35632253491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35632253491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42838204 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42838204 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74306947 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74306947 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74306947 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74306947 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062827 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062827 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037506 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037506 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037506 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037506 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12036.451814 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12036.451814 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33939.728432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33939.728432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12773.068764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12773.068764 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 220832 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 385 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43178 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.114456 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066926 # number of writebacks -system.cpu.dcache.writebacks::total 2066926 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697625 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 697625 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11912 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11912 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 709537 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 709537 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 709537 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 709537 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995588 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995588 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81814 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81814 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077402 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077402 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077402 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077402 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24271228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24271228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3023849487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3023849487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27295077987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27295077987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27295077987 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27295077987 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046553 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046553 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002602 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002602 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027957 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027957 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.444603 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.444603 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36960.049466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36960.049466 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 93 # number of replacements -system.cpu.icache.tags.tagsinuse 878.108473 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29762089 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1121 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26549.588760 # Average number of references to valid blocks. +system.cpu.dcache.demand_accesses::cpu.data 74277956 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74277956 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74277956 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74277956 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063063 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002984 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12747.055982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12747.055982 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219709 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 682 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43158 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2066902 # number of writebacks +system.cpu.dcache.writebacks::total 2066902 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 705827 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11900 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 717727 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 717727 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 717727 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 717727 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995694 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81911 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077605 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077605 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077605 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077605 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3020316491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3020316491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27293249991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27293249991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27293249991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27293249991 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002605 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002605 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027971 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027971 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.652942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.652942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36873.148796 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36873.148796 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 86 # number of replacements +system.cpu.icache.tags.tagsinuse 865.699388 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29658716 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1101 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26937.980018 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 878.108473 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.428764 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.428764 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1028 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 910 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59528269 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59528269 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29762089 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29762089 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29762089 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29762089 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29762089 # number of overall hits -system.cpu.icache.overall_hits::total 29762089 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1485 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1485 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1485 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1485 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1485 # number of overall misses -system.cpu.icache.overall_misses::total 1485 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 149774999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 149774999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 149774999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 149774999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 149774999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 149774999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29763574 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29763574 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29763574 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100858.585185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100858.585185 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2965 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 865.699388 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.422705 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.422705 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1015 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.495605 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59321439 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59321439 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 29658716 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29658716 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29658716 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29658716 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29658716 # number of overall hits +system.cpu.icache.overall_hits::total 29658716 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1453 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1453 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1453 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1453 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1453 # number of overall misses +system.cpu.icache.overall_misses::total 1453 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 154504998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 154504998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 154504998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 154504998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 154504998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 154504998 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1101 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1101 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995663 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1995663 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1101 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2077605 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2078706 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1101 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2077605 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078706 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353860 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353860 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014743 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014743 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks -system.cpu.l2cache.writebacks::total 309 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28990 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28990 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1093 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1093 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 581 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 581 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 299 # number of writebacks +system.cpu.l2cache.writebacks::total 299 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1093 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30664 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055891000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055891000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 101960000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 101960000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 86879500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 86879500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2142770500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2244730500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2142770500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2244730500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.975022 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000291 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000291 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70917.247327 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70917.247327 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93284.537969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93284.537969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 149534.423408 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 149534.423408 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4151922 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073402 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 335 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 335 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4152301 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 330 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6765 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995554 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2335 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228110 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6230445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265236992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265314688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 694 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19776 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079217 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000172 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.013121 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 86 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231007 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265324416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 680 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19136 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2079386 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000170 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013047 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2078859 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 358 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079217 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4142980000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079386 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143138500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1681500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1652498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116103000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3116407500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 31023 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 359 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 30996 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 350 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1674 # Transaction distribution -system.membus.trans_dist::WritebackDirty 309 # Transaction distribution -system.membus.trans_dist::CleanEvict 50 # Transaction distribution -system.membus.trans_dist::ReadExReq 28990 # Transaction distribution -system.membus.trans_dist::ReadExResp 28990 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1674 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1650 # Transaction distribution +system.membus.trans_dist::WritebackDirty 299 # Transaction distribution +system.membus.trans_dist::CleanEvict 51 # Transaction distribution +system.membus.trans_dist::ReadExReq 28996 # Transaction distribution +system.membus.trans_dist::ReadExResp 28996 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1650 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1980480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30664 # Request fanout histogram +system.membus.snoop_fanout::samples 30646 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30646 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30664 # Request fanout histogram -system.membus.reqLayer0.occupancy 43676000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30646 # Request fanout histogram +system.membus.reqLayer0.occupancy 43591500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161581250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161486250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |