diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/long/se/10.mcf/ref | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/long/se/10.mcf/ref')
8 files changed, 1594 insertions, 1308 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 7e42f0dae..0e2c469d2 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026923 # Number of seconds simulated -sim_ticks 26922512500 # Number of ticks simulated -final_tick 26922512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026909 # Number of seconds simulated +sim_ticks 26909234500 # Number of ticks simulated +final_tick 26909234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143955 # Simulator instruction rate (inst/s) -host_op_rate 144989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42782119 # Simulator tick rate (ticks/s) -host_mem_usage 446112 # Number of bytes of host memory used -host_seconds 629.29 # Real time elapsed on the host +host_inst_rate 142304 # Simulator instruction rate (inst/s) +host_op_rate 143325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42270537 # Simulator tick rate (ticks/s) +host_mem_usage 446544 # Number of bytes of host memory used +host_seconds 636.60 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 992896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 992640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1680675 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35199092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36879767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1680675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1680675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1680675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35199092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36879767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15514 # Number of read requests accepted +system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1671991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35216461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36888452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1671991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1671991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1671991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35216461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36888452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15510 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 992640 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side +system.physmem.bytesReadSys 992640 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 988 # Per bank write bursts -system.physmem.perBankRdBursts::1 886 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 987 # Per bank write bursts +system.physmem.perBankRdBursts::1 885 # Per bank write bursts system.physmem.perBankRdBursts::2 942 # Per bank write bursts system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1050 # Per bank write bursts +system.physmem.perBankRdBursts::4 1049 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts system.physmem.perBankRdBursts::6 1078 # Per bank write bursts system.physmem.perBankRdBursts::7 1078 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 956 # Per bank write bursts -system.physmem.perBankRdBursts::10 938 # Per bank write bursts +system.physmem.perBankRdBursts::9 957 # Per bank write bursts +system.physmem.perBankRdBursts::10 935 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::12 905 # Per bank write bursts system.physmem.perBankRdBursts::13 865 # Per bank write bursts system.physmem.perBankRdBursts::14 877 # Per bank write bursts system.physmem.perBankRdBursts::15 896 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26922312500 # Total gap between requests +system.physmem.totGap 26909036500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15514 # Read request sizes (log2) +system.physmem.readPktSize::6 15510 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,72 +186,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 880 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 935.927273 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 827.602742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 262.440032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41 4.66% 4.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 26 2.95% 7.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 1.48% 9.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 0.45% 9.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 0.57% 10.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 0.23% 10.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 0.23% 10.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.11% 10.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 786 89.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 880 # Bytes accessed per row activation -system.physmem.totQLat 108095000 # Total ticks spent queuing -system.physmem.totMemAccLat 369557500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers -system.physmem.totBankLat 183892500 # Total ticks spent accessing banks -system.physmem.avgQLat 6967.58 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11853.33 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 1363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 726.491563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 533.334896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.223532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 140 10.27% 10.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 158 11.59% 21.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56 4.11% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.99% 30.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 4.18% 35.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.86% 38.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 1.76% 39.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 39 2.86% 42.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 782 57.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1363 # Bytes accessed per row activation +system.physmem.totQLat 83369750 # Total ticks spent queuing +system.physmem.totMemAccLat 374182250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5375.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23820.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24125.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14141 # Number of row buffer hits during reads +system.physmem.readRowHits 14137 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1735355.97 # Average gap between requests +system.physmem.avgGap 1734947.55 # Average gap between requests system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.09 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 36879767 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 976 # Transaction distribution -system.membus.trans_dist::ReadResp 976 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1 # Transaction distribution +system.physmem.memoryStateTime::IDLE 24303660500 # Time in different power states +system.physmem.memoryStateTime::REF 898300000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1704463000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 36888452 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 972 # Transaction distribution +system.membus.trans_dist::ReadResp 972 # Transaction distribution +system.membus.trans_dist::UpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31030 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992896 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31026 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31026 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992640 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19225500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19094500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 144897999 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145899997 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 26688187 # Number of BP lookups -system.cpu.branchPred.condPredicted 22005801 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842567 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11378681 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11285656 # Number of BTB hits +system.cpu.branchPred.lookups 26684247 # Number of BP lookups +system.cpu.branchPred.condPredicted 22003797 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 841589 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11372801 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11278925 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.182462 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69960 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 176 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.174557 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69990 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,239 +339,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53845026 # number of cpu cycles simulated +system.cpu.numCycles 53818470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14173388 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127901014 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26688187 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11355616 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24038968 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4766662 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11320590 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14166768 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127874482 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26684247 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11348915 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24030832 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4761225 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11326508 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13845523 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 330018 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53440501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214653 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13838942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329737 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53427318 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.409937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214887 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29439765 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3390250 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2029247 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1554755 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1667292 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2920236 5.46% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1512043 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1089860 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9837053 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29434889 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3387974 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2027945 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1552978 2.91% 68.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1665988 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2918810 5.46% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1512193 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1089826 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9836715 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53440501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495648 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.375354 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16937222 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9166719 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22408314 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1029433 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3898813 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4444354 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8681 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126084070 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42675 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3898813 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18718559 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3593311 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 188330 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21554671 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5486817 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123168222 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 424808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4599857 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1460 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143625263 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536555031 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 500037832 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 718 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53427318 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495820 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.376033 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16930628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9172800 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22402161 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1027234 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3894495 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4441775 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8644 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126055074 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42561 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3894495 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18710503 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3595532 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186271 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21547494 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5493023 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123139917 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 426575 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4604902 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1527 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143588109 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536432016 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 499923969 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 641 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36211077 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4609 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4607 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12545622 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29481569 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5520172 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2131780 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1278964 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118183319 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105169429 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79348 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26754797 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65616265 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53440501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967972 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.909350 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36173923 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4624 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4622 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12547663 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29472846 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5519091 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2169224 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1269381 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118159243 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8489 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105145248 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78272 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26728441 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65602174 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 271 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53427318 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968005 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908888 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15384800 28.79% 28.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11651642 21.80% 50.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8259769 15.46% 66.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6813523 12.75% 78.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4933870 9.23% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2968386 5.55% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2461371 4.61% 98.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 525076 0.98% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442064 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15370604 28.77% 28.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11662585 21.83% 50.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8230563 15.41% 66.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6832993 12.79% 78.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4979120 9.32% 88.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2926966 5.48% 93.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2444206 4.57% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 536236 1.00% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 444045 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53440501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53427318 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 46222 6.98% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 26 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 339934 51.34% 58.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275932 41.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 46059 6.94% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 26 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 341162 51.43% 58.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 276052 41.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74431142 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10980 0.01% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 132 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 172 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25611933 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5115067 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74418244 70.78% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 122 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 157 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25603497 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5112252 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105169429 # Type of FU issued -system.cpu.iq.rate 1.953187 # Inst issue rate -system.cpu.iq.fu_busy_cnt 662114 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006296 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264520145 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144951370 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102696867 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 925 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105831206 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 441415 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105145248 # Type of FU issued +system.cpu.iq.rate 1.953702 # Inst issue rate +system.cpu.iq.fu_busy_cnt 663299 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006308 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264458762 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144900942 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102674293 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 623 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 845 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 263 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105808235 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 312 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 440410 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6907603 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6432 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6446 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 775328 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6898880 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6071 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6331 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 774247 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31602 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31563 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3898813 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 959371 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127029 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118204490 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309594 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29481569 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5520172 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66074 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6711 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6446 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446623 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445838 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892461 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104194994 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25292197 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 974435 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3894495 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 960394 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127228 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118180427 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309851 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29472846 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5519091 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4601 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65954 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6808 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6331 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446096 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445462 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891558 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104169534 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25284727 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 975714 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12694 # number of nop insts executed -system.cpu.iew.exec_refs 30350924 # number of memory reference insts executed -system.cpu.iew.exec_branches 21328461 # Number of branches executed -system.cpu.iew.exec_stores 5058727 # Number of stores executed -system.cpu.iew.exec_rate 1.935090 # Inst execution rate -system.cpu.iew.wb_sent 102975092 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102697154 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62242577 # num instructions producing a value -system.cpu.iew.wb_consumers 104291686 # num instructions consuming a value +system.cpu.iew.exec_nop 12695 # number of nop insts executed +system.cpu.iew.exec_refs 30339844 # number of memory reference insts executed +system.cpu.iew.exec_branches 21324580 # Number of branches executed +system.cpu.iew.exec_stores 5055117 # Number of stores executed +system.cpu.iew.exec_rate 1.935572 # Inst execution rate +system.cpu.iew.wb_sent 102952816 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102674556 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62244775 # num instructions producing a value +system.cpu.iew.wb_consumers 104288684 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907273 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596812 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907794 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26954537 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26930418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833969 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49541688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.841943 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.539958 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833018 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49532823 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842273 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541112 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20036957 40.44% 40.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13159597 26.56% 67.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4169965 8.42% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431804 6.93% 82.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1536139 3.10% 85.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 734203 1.48% 86.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 944467 1.91% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 252800 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275756 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20056290 40.49% 40.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13134081 26.52% 67.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4165062 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431851 6.93% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1531687 3.09% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 719294 1.45% 86.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 966848 1.95% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 252784 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5274926 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49541688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49532823 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -580,237 +582,274 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275756 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 63923653 70.05% 70.05% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.06% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22573966 24.74% 94.80% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction +system.cpu.commit.bw_lim_events 5274926 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162467695 # The number of ROB reads -system.cpu.rob.rob_writes 240333520 # The number of ROB writes -system.cpu.timesIdled 46195 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 404525 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162435541 # The number of ROB reads +system.cpu.rob.rob_writes 240280947 # The number of ROB writes +system.cpu.timesIdled 46113 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 391152 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.594383 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594383 # CPI: Total CPI of All Threads -system.cpu.ipc 1.682417 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.682417 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495621667 # number of integer regfile reads -system.cpu.int_regfile_writes 120557380 # number of integer regfile writes -system.cpu.fp_regfile_reads 149 # number of floating regfile reads -system.cpu.fp_regfile_writes 361 # number of floating regfile writes -system.cpu.misc_regfile_reads 29211256 # number of misc regfile reads +system.cpu.cpi 0.594090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594090 # CPI: Total CPI of All Threads +system.cpu.ipc 1.683247 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.683247 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495503749 # number of integer regfile reads +system.cpu.int_regfile_writes 120538753 # number of integer regfile writes +system.cpu.fp_regfile_reads 136 # number of floating regfile reads +system.cpu.fp_regfile_writes 324 # number of floating regfile writes +system.cpu.misc_regfile_reads 29202777 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4495994050 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942932 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43718 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1467 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838210 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120996480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121043392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121043392 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888584500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4498112646 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43808 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888546500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1214249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1423941741 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424437743 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 632.458088 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13844537 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18887.499318 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 629.782020 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13837957 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 727 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19034.328748 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 632.458088 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.308817 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.308817 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 730 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 629.782020 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.307511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.307511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 723 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.356445 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27691778 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27691778 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13844537 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13844537 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13844537 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13844537 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13844537 # number of overall hits -system.cpu.icache.overall_hits::total 13844537 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 985 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 985 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 985 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 985 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 985 # number of overall misses -system.cpu.icache.overall_misses::total 985 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65965748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65965748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65965748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65965748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65965748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65965748 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50737500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50737500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50737500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50737500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69524.182561 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 464 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3129 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 461 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3114 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 521 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 59988388 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 59988388 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23603660 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23603660 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532519 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532519 # 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number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28136179 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28136179 # number of overall hits -system.cpu.dcache.overall_hits::total 28136179 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173928 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173928 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202462 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202462 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28129461 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28129461 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28129461 # number of overall hits +system.cpu.dcache.overall_hits::total 28129461 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173693 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173693 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202649 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202649 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1376390 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1376390 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1376390 # number of overall misses -system.cpu.dcache.overall_misses::total 1376390 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893768230 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13893768230 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8571552365 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8571552365 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1376342 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1376342 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1376342 # number of overall misses +system.cpu.dcache.overall_misses::total 1376342 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13892857479 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13892857479 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8552070346 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8552070346 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22465320595 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22465320595 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22465320595 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22465320595 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24777588 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24777588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 22444927825 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22444927825 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22444927825 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22444927825 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24770822 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24770822 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29512569 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29512569 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29512569 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29512569 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047379 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047379 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042759 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042759 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046637 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046637 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046637 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046637 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.281406 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.281406 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42336.598300 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42336.598300 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29505803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29505803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29505803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29505803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047382 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047382 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042798 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042798 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001783 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001783 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046646 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046646 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046646 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046646 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.875127 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.875127 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42201.394263 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42201.394263 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16321.915006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16321.915006 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154484 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16307.667589 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16307.667589 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16307.667589 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16307.667589 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154301 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23933 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23947 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.454853 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.443438 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942932 # number of writebacks -system.cpu.dcache.writebacks::total 942932 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269988 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269988 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158763 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158763 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942913 # number of writebacks +system.cpu.dcache.writebacks::total 942913 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269863 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269863 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158857 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158857 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428751 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428751 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428751 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428751 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903940 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903940 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43699 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43699 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947639 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947639 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947639 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947639 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994791010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994791010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1332397702 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1332397702 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11327188712 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11327188712 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11327188712 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11327188712 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036482 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036482 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009229 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009229 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.918612 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.918612 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30490.347651 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30490.347651 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 428720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903830 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903830 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43792 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43792 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947622 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947622 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947622 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947622 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9993578260 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9993578260 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1330001932 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1330001932 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323580192 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11323580192 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323580192 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11323580192 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036488 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036488 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009249 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009249 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.922496 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.922496 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30370.888107 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30370.888107 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.469506 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.469506 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.469506 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.469506 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 0d20a5545..53bbc79f1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240661000 # Number of ticks simulated final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2151308 # Simulator instruction rate (inst/s) -host_op_rate 2166754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1287915883 # Simulator tick rate (ticks/s) -host_mem_usage 391064 # Number of bytes of host memory used -host_seconds 42.12 # Real time elapsed on the host +host_inst_rate 1753346 # Simulator instruction rate (inst/s) +host_op_rate 1765935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1049669772 # Simulator tick rate (ticks/s) +host_mem_usage 433744 # Number of bytes of host memory used +host_seconds 51.67 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91252960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 108481323 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91253402 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index c88119d29..a84dd1567 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1098833 # Simulator instruction rate (inst/s) -host_op_rate 1106711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1784978875 # Simulator tick rate (ticks/s) -host_mem_usage 400800 # Number of bytes of host memory used -host_seconds 82.43 # Real time elapsed on the host +host_inst_rate 805246 # Simulator instruction rate (inst/s) +host_op_rate 811020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1308067541 # Simulator tick rate (ticks/s) +host_mem_usage 443480 # Number of bytes of host memory used +host_seconds 112.48 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -153,6 +153,41 @@ system.cpu.num_busy_cycles 294271952 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction +system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91253402 # Class of executed instruction system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 04e67f508..49ab3ae18 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3086610 # Simulator instruction rate (inst/s) -host_op_rate 3086737 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1547143112 # Simulator tick rate (ticks/s) -host_mem_usage 361240 # Number of bytes of host memory used -host_seconds 78.99 # Real time elapsed on the host +host_inst_rate 2362566 # Simulator instruction rate (inst/s) +host_op_rate 2362664 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1184221154 # Simulator tick rate (ticks/s) +host_mem_usage 397240 # Number of bytes of host memory used +host_seconds 103.20 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,5 +65,40 @@ system.cpu.num_busy_cycles 244431648 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched +system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction +system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 244431613 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 5dcd0f89a..5300dcfdd 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1454320 # Simulator instruction rate (inst/s) -host_op_rate 1454380 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2156135283 # Simulator tick rate (ticks/s) -host_mem_usage 371132 # Number of bytes of host memory used -host_seconds 167.66 # Real time elapsed on the host +host_inst_rate 1070091 # Simulator instruction rate (inst/s) +host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1586487053 # Simulator tick rate (ticks/s) +host_mem_usage 406976 # Number of bytes of host memory used +host_seconds 227.85 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -69,6 +69,41 @@ system.cpu.num_busy_cycles 722977060 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched +system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction +system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.icache.tags.replacements 25 # number of replacements system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1b324ac26..53217cf02 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065578 # Number of seconds simulated -sim_ticks 65578127500 # Number of ticks simulated -final_tick 65578127500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065585 # Number of seconds simulated +sim_ticks 65585340000 # Number of ticks simulated +final_tick 65585340000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88175 # Simulator instruction rate (inst/s) -host_op_rate 155262 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36599742 # Simulator tick rate (ticks/s) -host_mem_usage 427692 # Number of bytes of host memory used -host_seconds 1791.76 # Real time elapsed on the host +host_inst_rate 87128 # Simulator instruction rate (inst/s) +host_op_rate 153419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36169402 # Simulator tick rate (ticks/s) +host_mem_usage 428764 # Number of bytes of host memory used +host_seconds 1813.28 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 63744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882880 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10368 # Number of bytes written to this memory -system.physmem.bytes_written::total 10368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29420 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30416 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 162 # Number of write requests responded to by this memory -system.physmem.num_writes::total 162 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 972031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28712012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29684044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 972031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 972031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 158101 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 158101 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 158101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 972031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28712012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29842145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30418 # Number of read requests accepted -system.physmem.writeReqs 162 # Number of write requests accepted -system.physmem.readBursts 30418 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1942912 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3840 # Total number of bytes read from write queue -system.physmem.bytesWritten 8384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1946752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 60 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883456 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory +system.physmem.bytes_written::total 11200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29429 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory +system.physmem.num_writes::total 175 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 976804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28717637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29694441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 976804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 976804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 170770 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 170770 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 170770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 976804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28717637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29865211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30432 # Number of read requests accepted +system.physmem.writeReqs 175 # Number of write requests accepted +system.physmem.readBursts 30432 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1942848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4800 # Total number of bytes read from write queue +system.physmem.bytesWritten 10048 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1947648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1927 # Per bank write bursts -system.physmem.perBankRdBursts::1 2065 # Per bank write bursts -system.physmem.perBankRdBursts::2 2026 # Per bank write bursts -system.physmem.perBankRdBursts::3 1928 # Per bank write bursts -system.physmem.perBankRdBursts::4 2026 # Per bank write bursts +system.physmem.perBankRdBursts::0 1922 # Per bank write bursts +system.physmem.perBankRdBursts::1 2061 # Per bank write bursts +system.physmem.perBankRdBursts::2 2029 # Per bank write bursts +system.physmem.perBankRdBursts::3 1929 # Per bank write bursts +system.physmem.perBankRdBursts::4 2025 # Per bank write bursts system.physmem.perBankRdBursts::5 1900 # Per bank write bursts -system.physmem.perBankRdBursts::6 1961 # Per bank write bursts -system.physmem.perBankRdBursts::7 1862 # Per bank write bursts +system.physmem.perBankRdBursts::6 1964 # Per bank write bursts +system.physmem.perBankRdBursts::7 1863 # Per bank write bursts system.physmem.perBankRdBursts::8 1940 # Per bank write bursts -system.physmem.perBankRdBursts::9 1933 # Per bank write bursts -system.physmem.perBankRdBursts::10 1805 # Per bank write bursts +system.physmem.perBankRdBursts::9 1934 # Per bank write bursts +system.physmem.perBankRdBursts::10 1804 # Per bank write bursts system.physmem.perBankRdBursts::11 1796 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1818 # Per bank write bursts -system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 10 # Per bank write bursts -system.physmem.perBankWrBursts::1 71 # Per bank write bursts -system.physmem.perBankWrBursts::2 3 # Per bank write bursts -system.physmem.perBankWrBursts::3 17 # Per bank write bursts -system.physmem.perBankWrBursts::4 12 # Per bank write bursts +system.physmem.perBankRdBursts::14 1820 # Per bank write bursts +system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankWrBursts::0 7 # Per bank write bursts +system.physmem.perBankWrBursts::1 84 # Per bank write bursts +system.physmem.perBankWrBursts::2 9 # Per bank write bursts +system.physmem.perBankWrBursts::3 29 # Per bank write bursts +system.physmem.perBankWrBursts::4 7 # Per bank write bursts system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 10 # Per bank write bursts +system.physmem.perBankWrBursts::6 12 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 5 # Per bank write bursts +system.physmem.perBankWrBursts::9 6 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts @@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65578111000 # Total gap between requests +system.physmem.totGap 65585323000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30418 # Read request sizes (log2) +system.physmem.readPktSize::6 30432 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 175 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,179 +193,181 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 934.162679 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 823.717230 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 264.349754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 77 4.61% 4.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 54 3.23% 7.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 19 1.14% 8.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 0.60% 9.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 11 0.66% 10.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5 0.30% 10.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 0.36% 10.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 0.24% 11.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1486 88.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1672 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4327.142857 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 47.742498 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 11404.448466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6 85.71% 85.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 14.29% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.714286 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.459831 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.545621 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3 42.86% 42.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 42.86% 85.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 14.29% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.physmem.totQLat 98355750 # Total ticks spent queuing -system.physmem.totMemAccLat 704267000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151790000 # Total ticks spent in databus transfers -system.physmem.totBankLat 454121250 # Total ticks spent accessing banks -system.physmem.avgQLat 3239.86 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14958.87 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 2701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 722.766383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 519.037520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.855736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 380 14.07% 14.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 203 7.52% 21.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 114 4.22% 25.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 3.89% 29.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 110 4.07% 33.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 132 4.89% 38.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 83 3.07% 41.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 80 2.96% 44.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1494 55.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2701 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3366.777778 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 25.330646 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10057.961719 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.444444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.423969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.881917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 22.22% 22.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 11.11% 33.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6 66.67% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads +system.physmem.totQLat 122012500 # Total ticks spent queuing +system.physmem.totMemAccLat 691206250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4019.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23198.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.69 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 22769.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.72 # Average write queue length when enqueuing -system.physmem.readRowHits 27690 # Number of row buffer hits during reads -system.physmem.writeRowHits 93 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes -system.physmem.avgGap 2144477.14 # Average gap between requests -system.physmem.pageHitRate 91.03 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.03 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 29841169 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1415 # Transaction distribution -system.membus.trans_dist::ReadResp 1412 # Transaction distribution -system.membus.trans_dist::Writeback 162 # Transaction distribution -system.membus.trans_dist::ReadExReq 29003 # Transaction distribution -system.membus.trans_dist::ReadExResp 29003 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60995 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1956928 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1956928 # Total data (bytes) +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.09 # Average write queue length when enqueuing +system.physmem.readRowHits 27699 # Number of row buffer hits during reads +system.physmem.writeRowHits 110 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.86 # Row buffer hit rate for writes +system.physmem.avgGap 2142821.02 # Average gap between requests +system.physmem.pageHitRate 91.08 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 59149173500 # Time in different power states +system.physmem.memoryStateTime::REF 2189980000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 4244704000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 29864235 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1427 # Transaction distribution +system.membus.trans_dist::ReadResp 1424 # Transaction distribution +system.membus.trans_dist::Writeback 175 # Transaction distribution +system.membus.trans_dist::ReadExReq 29005 # Transaction distribution +system.membus.trans_dist::ReadExResp 29005 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61036 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1958656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1958656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1958656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34882000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 35026000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284250750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284359000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 33848859 # Number of BP lookups -system.cpu.branchPred.condPredicted 33848859 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 773675 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19289255 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19197917 # Number of BTB hits +system.cpu.branchPred.lookups 33857939 # Number of BP lookups +system.cpu.branchPred.condPredicted 33857939 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774699 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19294742 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19202488 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.526482 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5013789 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5382 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.521870 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5017287 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5447 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 131156258 # number of cpu cycles simulated +system.cpu.numCycles 131170685 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26124618 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182201449 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33848859 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24211706 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55441130 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5339784 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44953696 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 26133192 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182246280 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33857939 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24219775 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55455334 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5351155 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44937204 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 289 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25565447 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166050 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131050652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.451103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 25572777 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166462 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131067108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.451414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313936 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78085477 59.58% 59.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1960121 1.50% 61.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2941365 2.24% 63.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3832581 2.92% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7765611 5.93% 72.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4754905 3.63% 75.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2663892 2.03% 77.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1315906 1.00% 78.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27730794 21.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78089059 59.58% 59.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1960403 1.50% 61.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2941378 2.24% 63.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3833422 2.92% 66.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7766051 5.93% 72.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4756858 3.63% 75.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2667148 2.03% 77.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1317375 1.01% 78.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27735414 21.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131050652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258080 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.389194 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36811004 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37176024 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43889002 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8643749 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4530873 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318736109 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4530873 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42298555 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9762867 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46737142 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27713810 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 314904511 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 131067108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258121 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.389383 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36820362 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37159698 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43897766 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8648241 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4541041 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318820485 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4541041 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42311218 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9731436 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7378 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46747775 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27728260 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 314978384 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26056 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25855633 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 317074927 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836235433 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 514870937 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 492 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 26284 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25867087 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 317148193 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836430617 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 514996548 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 444 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37862180 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 484 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 482 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62586078 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101522320 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34765778 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39602927 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5818030 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311370743 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1646 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300208382 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 88815 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32598997 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 45935189 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131050652 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290781 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700647 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37935446 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 481 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 479 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62636107 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101548078 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34773749 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39632863 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5801803 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311454794 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1640 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300260019 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90405 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32683934 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46065887 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1195 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131067108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290888 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.699985 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24364795 18.59% 18.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23214690 17.71% 36.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25426307 19.40% 55.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25814267 19.70% 75.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18862103 14.39% 89.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8277108 6.32% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3959654 3.02% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 947423 0.72% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 184305 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24336657 18.57% 18.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23236619 17.73% 36.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25445511 19.41% 55.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25817468 19.70% 75.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18870400 14.40% 89.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8268823 6.31% 96.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3966909 3.03% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 944963 0.72% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 179758 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131050652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131067108 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31474 1.53% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31509 1.53% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available @@ -394,14 +396,14 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1916835 93.04% 94.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 111878 5.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1916553 93.05% 94.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111592 5.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169792966 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11226 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 332 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169826780 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11192 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued @@ -428,84 +430,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97287204 32.41% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33085346 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97302133 32.41% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33088277 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300208382 # Type of FU issued -system.cpu.iq.rate 2.288937 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2060187 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006863 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733615929 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344003056 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 297961989 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 489 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 706 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 149 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302237064 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 228 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54184589 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300260019 # Type of FU issued +system.cpu.iq.rate 2.289079 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2059654 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733736743 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344172361 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298003080 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 638 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 138 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302288185 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 212 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54177955 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10742935 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32064 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33208 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3326026 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10768693 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31319 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33463 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3333997 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8575 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3215 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4530873 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2837927 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162034 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311372389 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 196090 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101522320 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34765778 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2524 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73590 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33208 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 392510 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427924 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 820434 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298810960 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96874788 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1397422 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4541041 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2814889 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 161942 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311456434 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 197084 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101548078 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34773749 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2528 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73554 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33463 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393542 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427902 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821444 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298855458 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96888981 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1404561 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129797042 # number of memory reference insts executed -system.cpu.iew.exec_branches 30816203 # Number of branches executed -system.cpu.iew.exec_stores 32922254 # Number of stores executed -system.cpu.iew.exec_rate 2.278282 # Inst execution rate -system.cpu.iew.wb_sent 298329085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 297962138 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218205948 # num instructions producing a value -system.cpu.iew.wb_consumers 296684532 # num instructions consuming a value +system.cpu.iew.exec_refs 129814280 # number of memory reference insts executed +system.cpu.iew.exec_branches 30819367 # Number of branches executed +system.cpu.iew.exec_stores 32925299 # Number of stores executed +system.cpu.iew.exec_rate 2.278371 # Inst execution rate +system.cpu.iew.wb_sent 298372320 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298003218 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218247752 # num instructions producing a value +system.cpu.iew.wb_consumers 296740863 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.271810 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735481 # average fanout of values written-back +system.cpu.iew.wb_rate 2.271874 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735483 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33192838 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33277101 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 773712 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126519779 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.198806 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.971927 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774736 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126526067 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.198697 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.971805 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58265880 46.05% 46.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19155859 15.14% 61.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11581370 9.15% 70.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9445264 7.47% 77.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880302 1.49% 79.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2071430 1.64% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1302334 1.03% 81.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 693009 0.55% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22124331 17.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58264985 46.05% 46.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19162475 15.15% 61.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11581155 9.15% 70.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9447794 7.47% 77.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880712 1.49% 79.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2075089 1.64% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1295892 1.02% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 693068 0.55% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22124897 17.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126519779 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126526067 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -516,231 +518,266 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22124331 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction +system.cpu.commit.bw_lim_events 22124897 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415780750 # The number of ROB reads -system.cpu.rob.rob_writes 627305222 # The number of ROB writes -system.cpu.timesIdled 13712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 105606 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415870735 # The number of ROB reads +system.cpu.rob.rob_writes 627483927 # The number of ROB writes +system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 103577 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.830163 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.830163 # CPI: Total CPI of All Threads -system.cpu.ipc 1.204583 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.204583 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483659759 # number of integer regfile reads -system.cpu.int_regfile_writes 234542237 # number of integer regfile writes -system.cpu.fp_regfile_reads 137 # number of floating regfile reads -system.cpu.fp_regfile_writes 71 # number of floating regfile writes -system.cpu.cc_regfile_reads 107049810 # number of cc regfile reads -system.cpu.cc_regfile_writes 63997871 # number of cc regfile writes -system.cpu.misc_regfile_reads 191792946 # number of misc regfile reads +system.cpu.cpi 0.830254 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.830254 # CPI: Total CPI of All Threads +system.cpu.ipc 1.204450 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.204450 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 483721911 # number of integer regfile reads +system.cpu.int_regfile_writes 234579114 # number of integer regfile writes +system.cpu.fp_regfile_reads 126 # number of floating regfile reads +system.cpu.fp_regfile_writes 70 # number of floating regfile writes +system.cpu.cc_regfile_reads 107055944 # number of cc regfile reads +system.cpu.cc_regfile_writes 64002928 # number of cc regfile writes +system.cpu.misc_regfile_reads 191820739 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4044284064 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82322 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221626 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265151808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265216576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265216576 # Total data (bytes) +system.cpu.toL2Bus.throughput 4043936892 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066459 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82321 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2030 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221762 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265158016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265222976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265222976 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138401000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138515000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1688749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1696250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121628749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3121723249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) system.cpu.icache.tags.replacements 55 # number of replacements -system.cpu.icache.tags.tagsinuse 821.703802 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25564150 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1012 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25261.017787 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 822.073751 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25571467 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1015 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25193.563547 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 821.703802 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.401223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.401223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 957 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 822.073751 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.401403 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.401403 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.467285 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51131906 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51131906 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25564150 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25564150 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25564150 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25564150 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25564150 # number of overall hits -system.cpu.icache.overall_hits::total 25564150 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1297 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1297 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1297 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1297 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1297 # number of overall misses -system.cpu.icache.overall_misses::total 1297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 90379749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 90379749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 90379749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 90379749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 90379749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 90379749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25565447 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25565447 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25565447 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25565447 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25565447 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25565447 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 51146569 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51146569 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25571467 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25571467 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25571467 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25571467 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25571467 # number of overall hits +system.cpu.icache.overall_hits::total 25571467 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1310 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1310 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1310 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1310 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1310 # number of overall misses +system.cpu.icache.overall_misses::total 1310 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 88805250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 88805250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 88805250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 88805250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 88805250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 88805250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25572777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25572777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25572777 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25572777 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25572777 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25572777 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69683.692367 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69683.692367 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69683.692367 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69683.692367 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69683.692367 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69683.692367 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67790.267176 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67790.267176 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67790.267176 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67790.267176 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67790.267176 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67790.267176 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 116 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38.666667 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1012 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1012 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1012 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70911751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 70911751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70911751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 70911751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70911751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 70911751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 295 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 295 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1560302500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1617550750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 57248250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1560302500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1617550750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352312 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352312 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52910.345482 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57478.162651 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53031.829923 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53177.419620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57478.162651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53031.829923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53177.419620 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks +system.cpu.l2cache.writebacks::total 175 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1001 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000715 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986207 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014172 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014647 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986207 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014172 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014647 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56167.582418 # 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Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71382775 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076635 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.374252 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20654566000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.510002 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993533 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993533 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 573 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3367 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 584 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150248380 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150248380 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 40019790 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40019790 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341704 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341704 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71361494 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71361494 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71361494 # number of overall hits -system.cpu.dcache.overall_hits::total 71361494 # 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miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036773 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.570307 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.570307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28575.157035 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28575.157035 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12556.583112 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12556.583112 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12556.583112 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12556.583112 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32689 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74106766 # 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average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11957.282231 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28468.783436 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28468.783436 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12551.413347 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12551.413347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12551.413347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12551.413347 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32593 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9492 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9513 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443847 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.426154 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066395 # number of writebacks -system.cpu.dcache.writebacks::total 2066395 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631958 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631958 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15832 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15832 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647790 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647790 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647790 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647790 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994389 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994389 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076605 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076605 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076605 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076605 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21997400000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21997400000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514181749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514181749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24511581749 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24511581749 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24511581749 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24511581749 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046766 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046766 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066459 # number of writebacks +system.cpu.dcache.writebacks::total 2066459 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631537 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631537 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15816 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15816 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647353 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994437 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994437 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82201 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82201 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996919001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996919001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502949746 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502949746 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24499868747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24499868747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24499868747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24499868747 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046744 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046744 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028030 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028030 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.643665 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.643665 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30580.200314 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30580.200314 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11803.680406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11803.680406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11803.680406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11803.680406 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028022 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028022 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028022 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028022 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.137045 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.137045 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30449.139864 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30449.139864 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.852465 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.852465 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.852465 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.852465 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 2af726aad..d0541f8a9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1603557 # Simulator instruction rate (inst/s) -host_op_rate 2823605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1714813271 # Simulator tick rate (ticks/s) -host_mem_usage 379092 # Number of bytes of host memory used -host_seconds 98.52 # Real time elapsed on the host +host_inst_rate 1054637 # Simulator instruction rate (inst/s) +host_op_rate 1857047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1127809594 # Simulator tick rate (ticks/s) +host_mem_usage 414920 # Number of bytes of host memory used +host_seconds 149.80 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -66,5 +66,40 @@ system.cpu.num_busy_cycles 337900081 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction +system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 278192465 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 9f0a8c755..917c42379 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 696180 # Simulator instruction rate (inst/s) -host_op_rate 1225861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1612738645 # Simulator tick rate (ticks/s) -host_mem_usage 388852 # Number of bytes of host memory used -host_seconds 226.94 # Real time elapsed on the host +host_inst_rate 596728 # Simulator instruction rate (inst/s) +host_op_rate 1050742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1382352440 # Simulator tick rate (ticks/s) +host_mem_usage 424660 # Number of bytes of host memory used +host_seconds 264.76 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -82,6 +82,41 @@ system.cpu.num_busy_cycles 731978130 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction +system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 278192465 # Class of executed instruction system.cpu.icache.tags.replacements 24 # number of replacements system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. |