diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/10.mcf/ref | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/10.mcf/ref')
7 files changed, 2377 insertions, 2389 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 4f1cfb81e..2c11d0b34 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061494 # Number of seconds simulated -sim_ticks 61493732000 # Number of ticks simulated -final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061593 # Number of seconds simulated +sim_ticks 61592600500 # Number of ticks simulated +final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 144123 # Simulator instruction rate (inst/s) -host_op_rate 144840 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 97818525 # Simulator tick rate (ticks/s) -host_mem_usage 433504 # Number of bytes of host memory used -host_seconds 628.65 # Real time elapsed on the host +host_inst_rate 271325 # Simulator instruction rate (inst/s) +host_op_rate 272676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 184448880 # Simulator tick rate (ticks/s) +host_mem_usage 445184 # Number of bytes of host memory used +host_seconds 333.93 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49600 # Nu system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61493643500 # Total gap between requests +system.physmem.totGap 61592506000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation -system.physmem.totQLat 73247750 # Total ticks spent queuing -system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation +system.physmem.totQLat 77242000 # Total ticks spent queuing +system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14031 # Number of row buffer hits during reads +system.physmem.readRowHits 14018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3948227.51 # Average gap between requests -system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 3954575.02 # Average gap between requests +system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.483541 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.572046 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.402933 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.509428 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20789429 # Number of BP lookups -system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20789446 # Number of BP lookups +system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,89 +377,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122987464 # number of cpu cycles simulated +system.cpu.numCycles 123185201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602849 # Number of instructions committed system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.357435 # CPI: cycles per instruction -system.cpu.ipc 0.736684 # IPC: instructions per cycle -system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.359617 # CPI: cycles per instruction +system.cpu.ipc 0.735501 # IPC: instructions per cycle +system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946107 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits -system.cpu.dcache.overall_hits::total 26259886 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses -system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits +system.cpu.dcache.overall_hits::total 26259649 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses +system.cpu.dcache.overall_misses::total 989105 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,14 +470,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks system.cpu.dcache.writebacks::total 943286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses @@ -486,14 +486,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950203 system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses @@ -502,67 +502,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits -system.cpu.icache.overall_hits::total 27857009 # number of overall hits +system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits +system.cpu.icache.overall_hits::total 27857028 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.icache.overall_misses::total 803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,38 +577,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803 system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -618,41 +618,41 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits -system.cpu.l2cache.overall_hits::total 935423 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 935422 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 778 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1040 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 778 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses +system.cpu.l2cache.demand_misses::total 15584 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses -system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52344250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19360000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 958084250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 52344250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 977444250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 52344250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 977444250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 15584 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) @@ -666,28 +666,28 @@ system.cpu.l2cache.demand_accesses::total 951006 # n system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,15 +696,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses @@ -716,17 +716,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15575 system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses @@ -738,17 +738,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution @@ -763,25 +763,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1031 # Transaction distribution @@ -802,9 +800,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15575 # Request fanout histogram -system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index ea993d96c..8fe6f61b1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057719 # Number of seconds simulated -sim_ticks 57719377000 # Number of ticks simulated -final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058203 # Number of seconds simulated +sim_ticks 58202727500 # Number of ticks simulated +final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125223 # Simulator instruction rate (inst/s) -host_op_rate 125847 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79786059 # Simulator tick rate (ticks/s) -host_mem_usage 443544 # Number of bytes of host memory used -host_seconds 723.43 # Real time elapsed on the host +host_inst_rate 129726 # Simulator instruction rate (inst/s) +host_op_rate 130372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83346935 # Simulator tick rate (ticks/s) +host_mem_usage 443628 # Number of bytes of host memory used +host_seconds 698.32 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory -system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory -system.physmem.bytes_written::total 19776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory -system.physmem.num_writes::total 309 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15872 # Number of read requests accepted -system.physmem.writeReqs 309 # Number of write requests accepted -system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue -system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 45376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 930112 # Number of bytes read from this memory +system.physmem.bytes_read::total 1019968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 22912 # Number of bytes written to this memory +system.physmem.bytes_written::total 22912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15937 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 358 # Number of write requests responded to by this memory +system.physmem.num_writes::total 358 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 764225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 779620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15980557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17524402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 764225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 764225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 393659 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 393659 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 393659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 764225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 779620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15980557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17918061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15937 # Number of read requests accepted +system.physmem.writeReqs 358 # Number of write requests accepted +system.physmem.readBursts 15937 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 358 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1010432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.physmem.bytesWritten 21184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1019968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 22912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 999 # Per bank write bursts +system.physmem.perBankRdBursts::0 1009 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 956 # Per bank write bursts -system.physmem.perBankRdBursts::3 1023 # Per bank write bursts +system.physmem.perBankRdBursts::2 958 # Per bank write bursts +system.physmem.perBankRdBursts::3 1024 # Per bank write bursts system.physmem.perBankRdBursts::4 1064 # Per bank write bursts -system.physmem.perBankRdBursts::5 1127 # Per bank write bursts -system.physmem.perBankRdBursts::6 1115 # Per bank write bursts -system.physmem.perBankRdBursts::7 1101 # Per bank write bursts -system.physmem.perBankRdBursts::8 1033 # Per bank write bursts +system.physmem.perBankRdBursts::5 1132 # Per bank write bursts +system.physmem.perBankRdBursts::6 1124 # Per bank write bursts +system.physmem.perBankRdBursts::7 1103 # Per bank write bursts +system.physmem.perBankRdBursts::8 1046 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts system.physmem.perBankRdBursts::10 937 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 910 # Per bank write bursts -system.physmem.perBankRdBursts::13 886 # Per bank write bursts -system.physmem.perBankRdBursts::14 919 # Per bank write bursts -system.physmem.perBankRdBursts::15 912 # Per bank write bursts -system.physmem.perBankWrBursts::0 23 # Per bank write bursts +system.physmem.perBankRdBursts::12 909 # Per bank write bursts +system.physmem.perBankRdBursts::13 889 # Per bank write bursts +system.physmem.perBankRdBursts::14 926 # Per bank write bursts +system.physmem.perBankRdBursts::15 930 # Per bank write bursts +system.physmem.perBankWrBursts::0 30 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 4 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 9 # Per bank write bursts +system.physmem.perBankWrBursts::2 8 # Per bank write bursts +system.physmem.perBankWrBursts::3 1 # Per bank write bursts +system.physmem.perBankWrBursts::4 10 # Per bank write bursts system.physmem.perBankWrBursts::5 29 # Per bank write bursts -system.physmem.perBankWrBursts::6 62 # Per bank write bursts -system.physmem.perBankWrBursts::7 30 # Per bank write bursts -system.physmem.perBankWrBursts::8 15 # Per bank write bursts +system.physmem.perBankWrBursts::6 69 # Per bank write bursts +system.physmem.perBankWrBursts::7 31 # Per bank write bursts +system.physmem.perBankWrBursts::8 36 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 10 # Per bank write bursts -system.physmem.perBankWrBursts::11 1 # Per bank write bursts -system.physmem.perBankWrBursts::12 9 # Per bank write bursts +system.physmem.perBankWrBursts::10 7 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 7 # Per bank write bursts system.physmem.perBankWrBursts::13 27 # Per bank write bursts -system.physmem.perBankWrBursts::14 48 # Per bank write bursts -system.physmem.perBankWrBursts::15 21 # Per bank write bursts +system.physmem.perBankWrBursts::14 45 # Per bank write bursts +system.physmem.perBankWrBursts::15 31 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57719226000 # Total gap between requests +system.physmem.totGap 58202569500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15872 # Read request sizes (log2) +system.physmem.readPktSize::6 15937 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 358 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,95 +197,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 179464908 # Total ticks spent queuing -system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 551.268840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 315.885566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 433.770323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 552 29.50% 29.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 218 11.65% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 92 4.92% 46.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 3.05% 49.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 3.37% 52.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 44 2.35% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 55 2.94% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 42 2.24% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 39.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1871 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 18 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 874.777778 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 39.760140 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3541.219224 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17 94.44% 94.44% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 5.56% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 18 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.388889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.356746 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.195033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 15 83.33% 83.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 11.11% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 5.56% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 18 # Writes before turning the bus around for reads +system.physmem.totQLat 172783990 # Total ticks spent queuing +system.physmem.totMemAccLat 468808990 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10944.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29694.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing -system.physmem.readRowHits 14166 # Number of row buffer hits during reads -system.physmem.writeRowHits 92 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes -system.physmem.avgGap 3567098.82 # Average gap between requests -system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.607894 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states -system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.15 # Average write queue length when enqueuing +system.physmem.readRowHits 14154 # Number of row buffer hits during reads +system.physmem.writeRowHits 93 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.20 # Row buffer hit rate for writes +system.physmem.avgGap 3571805.43 # Average gap between requests +system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64638600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1153440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2451888630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32770707750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39101711325 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.822097 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54506616189 # Time in different power states +system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1752376311 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.433104 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states -system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58484400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 991440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2431326735 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32788744500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39091058805 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.639072 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54537138662 # Time in different power states +system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1721853838 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28271166 # Number of BP lookups -system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits +system.cpu.branchPred.lookups 28259323 # Number of BP lookups +system.cpu.branchPred.condPredicted 23281308 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11850778 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11785443 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.448686 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75758 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,83 +403,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 115438755 # number of cpu cycles simulated +system.cpu.numCycles 116405456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 749294 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134993998 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28259323 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11861201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114761716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679249 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1000 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 840 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32304088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 579 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116352474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165469 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319047 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58780581 50.52% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13944559 11.98% 62.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9221403 7.93% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34405931 29.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116352474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242766 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.159688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8844184 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64087377 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33032699 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560836 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827378 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101289 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114434840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1995518 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15306554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49837632 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 110028 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35408205 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14862677 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110902804 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415247 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133046 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1143083 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1515709 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 570063 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129962368 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483290389 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119478713 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22649449 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle +system.cpu.rename.skidInsts 21572068 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26814283 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349560 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 615072 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 351208 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109694902 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54656656 46.98% 46.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31447896 27.03% 74.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21997479 18.91% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7054961 6.06% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1195165 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -488,149 +487,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116352474 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9796147 48.71% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9605529 47.77% 96.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 708223 3.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71985557 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24344215 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049315 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued -system.cpu.iq.rate 0.878644 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101389982 # Type of FU issued +system.cpu.iq.rate 0.871007 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 282708 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4338372 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1511 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1302 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7561 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130367 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8117043 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 661508 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109715814 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26814283 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349560 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178487 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 319637 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1302 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436579 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412967 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849546 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100128293 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23807365 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1261689 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12667 # number of nop insts executed -system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed -system.cpu.iew.exec_branches 20629236 # Number of branches executed -system.cpu.iew.exec_stores 4918943 # Number of stores executed -system.cpu.iew.exec_rate 0.867532 # Inst execution rate -system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59706662 # num instructions producing a value -system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value +system.cpu.iew.exec_nop 12666 # number of nop insts executed +system.cpu.iew.exec_refs 28725194 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624883 # Number of branches executed +system.cpu.iew.exec_stores 4917829 # Number of stores executed +system.cpu.iew.exec_rate 0.860168 # Inst execution rate +system.cpu.iew.wb_sent 99711182 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99626193 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59706016 # num instructions producing a value +system.cpu.iew.wb_consumers 95562461 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back +system.cpu.iew.wb_rate 0.855855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17390136 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113659456 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737097 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77211009 67.93% 67.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18641585 16.40% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7152887 6.29% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3463018 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1652627 1.45% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 524640 0.46% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 723684 0.64% 96.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178635 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4111371 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113659456 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -676,383 +675,383 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction -system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 217026090 # The number of ROB reads -system.cpu.rob.rob_writes 219584249 # The number of ROB writes -system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 217986125 # The number of ROB reads +system.cpu.rob.rob_writes 219581178 # The number of ROB writes +system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads -system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108125012 # number of integer regfile reads -system.cpu.int_regfile_writes 58739124 # number of integer regfile writes +system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778226 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778226 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108112973 # number of integer regfile reads +system.cpu.int_regfile_writes 58701982 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 99 # number of floating regfile writes -system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads -system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes -system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads +system.cpu.fp_regfile_writes 95 # number of floating regfile writes +system.cpu.cc_regfile_reads 369069288 # number of cc regfile reads +system.cpu.cc_regfile_writes 58692619 # number of cc regfile writes +system.cpu.misc_regfile_reads 28415446 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5486247 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5469543 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.788616 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18297454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470055 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.345022 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35157000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.788616 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999587 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61924995 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61924995 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13934183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13934183 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354974 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354974 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits -system.cpu.dcache.overall_hits::total 18263472 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 18289157 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18289157 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18289679 # number of overall hits +system.cpu.dcache.overall_hits::total 18289679 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9550003 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9550003 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380007 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380007 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses -system.cpu.dcache.overall_misses::total 9970594 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9930010 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9930010 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9930017 # number of overall misses +system.cpu.dcache.overall_misses::total 9930017 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88443276736 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88443276736 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962066244 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3962066244 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92405342980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92405342980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92405342980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92405342980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23484186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23484186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28219167 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28219167 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28219696 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28219696 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080255 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080255 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.351889 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.351889 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.351882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.351882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.073189 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.073189 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10426.298052 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10426.298052 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.664645 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9305.664645 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.658085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9305.658085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 306020 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 36082 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120709 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535188 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.839333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks -system.cpu.dcache.writebacks::total 5460017 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154868 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5439051 # number of writebacks +system.cpu.dcache.writebacks::total 5439051 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4313021 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4313021 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146936 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 146936 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4483830 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4483830 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4483830 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4483830 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263967 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5263967 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222789 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222789 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 4459957 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4459957 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4459957 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4459957 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236982 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5236982 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233071 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 233071 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 5470053 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470053 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470057 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470057 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40519086258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40519086258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2295163471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2295163471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42814249729 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42814249729 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42814462729 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42814462729 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 32302915 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35497.708791 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 428.263511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836452 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836452 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64631998 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64631998 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32314402 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32314402 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32314402 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32314402 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32314402 # number of overall hits -system.cpu.icache.overall_hits::total 32314402 # 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses +system.cpu.icache.overall_misses::total 1158 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62669987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62669987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62669987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62669987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62669987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62669987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32304073 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32304073 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32304073 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32304073 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54119.159758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54119.159758 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19414 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 238 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 81.571429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 238 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 238 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 238 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 238 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 906 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 906 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 906 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 906 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 906 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44276742 # 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number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50368733 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50368733 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50368733 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50368733 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50368733 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50368733 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48870.576159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48870.576159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48870.576159 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1059 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 175404109 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 175404109 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 211 # 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Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 174809424 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 174809424 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 213 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5236439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5236652 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 5439051 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 5439051 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232688 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232688 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 213 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5469127 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5469340 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 213 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 709 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1404 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 709 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20246 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 21650 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42518507 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21103750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63622257 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 830590289 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25988008 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25988008 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42518507 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47091758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 89610265 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42518507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47091758 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 920200554 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000203 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000257 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61177.707914 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57347.146739 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59851.605833 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41024.908081 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76211.167155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76211.167155 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63824.975071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.489792 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5237765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5237765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5439051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22132 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 22341 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 233200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 233200 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1820 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16379167 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16380987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698182912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 698241152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 22134 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10932150 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10910018 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 22132 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10932150 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10894060998 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1497004 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 15531 # Transaction distribution -system.membus.trans_dist::ReadResp 15531 # Transaction distribution -system.membus.trans_dist::Writeback 309 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 8205133181 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 15596 # Transaction distribution +system.membus.trans_dist::ReadResp 15596 # Transaction distribution +system.membus.trans_dist::Writeback 358 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 341 # Transaction distribution system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32236 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32236 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1042880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1042880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16183 # Request fanout histogram +system.membus.snoop_fanout::samples 16297 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16297 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16183 # Request fanout histogram -system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16297 # Request fanout histogram +system.membus.reqLayer0.occupancy 26854780 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 83365318 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 16d507b60..b143a6790 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000000 # Number of ticks simulated final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1669323 # Simulator instruction rate (inst/s) -host_op_rate 1677636 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 997531404 # Simulator tick rate (ticks/s) -host_mem_usage 433488 # Number of bytes of host memory used -host_seconds 54.28 # Real time elapsed on the host +host_inst_rate 1893120 # Simulator instruction rate (inst/s) +host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1131265211 # Simulator tick rate (ticks/s) +host_mem_usage 433636 # Number of bytes of host memory used +host_seconds 47.86 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 135031170 # Request fanout histogram -system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram +system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 135031170 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 3f9742fb4..7176a8af9 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041218000 # Number of ticks simulated -final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 147041218500 # Number of ticks simulated +final_tick 147041218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114927 # Simulator instruction rate (inst/s) -host_op_rate 1120467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1809956176 # Simulator tick rate (ticks/s) -host_mem_usage 442716 # Number of bytes of host memory used -host_seconds 81.24 # Real time elapsed on the host +host_inst_rate 937429 # Simulator instruction rate (inst/s) +host_op_rate 942087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1521808702 # Simulator tick rate (ticks/s) +host_mem_usage 442868 # Number of bytes of host memory used +host_seconds 96.62 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082436 # number of cpu cycles simulated +system.cpu.numCycles 294082437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576861 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082435.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294082436.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.593939 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 54410414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593939 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11508315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508433500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11508433500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120572 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120575 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120572 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id @@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32073500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32073500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32073500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32073500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32073500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32073500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32074000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32074000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32074000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32074000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses @@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.075125 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53545.075125 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53545.075125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53545.075125 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53545.909850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53545.909850 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30875500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30875500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30875500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30875500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30875500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30875500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31175500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31175500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31175500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31175500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31175500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31175500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51545.075125 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51545.075125 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52045.909850 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852615 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.852421 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172981 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233101 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233100 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy @@ -477,17 +477,17 @@ system.cpu.l2cache.demand_misses::total 15340 # nu system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30066500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11130000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 41196500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756746500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 756746500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30066500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 767876500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 797943000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30066500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 767876500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 797943000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11237000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 41593000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 775257500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 805613500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 775257500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 805613500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) @@ -512,17 +512,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52018.166090 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.345794 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.782828 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52017.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52017.218862 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52017.144720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52017.144720 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,17 +542,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15340 system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 613600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 613600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23409000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597861000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23409000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597861000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses @@ -564,17 +564,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution @@ -589,19 +589,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1889731 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) @@ -628,9 +626,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 76963500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 86f47af4e..b81c12b39 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488530000 # Number of ticks simulated -final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 361488530500 # Number of ticks simulated +final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1379749 # Simulator instruction rate (inst/s) -host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2045576865 # Simulator tick rate (ticks/s) -host_mem_usage 421936 # Number of bytes of host memory used -host_seconds 176.72 # Real time elapsed on the host +host_inst_rate 1163469 # Simulator instruction rate (inst/s) +host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1724927568 # Simulator tick rate (ticks/s) +host_mem_usage 425840 # Number of bytes of host memory used +host_seconds 209.57 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,32 +29,9 @@ system.physmem.bw_inst_read::total 155623 # In system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1036 # Transaction distribution -system.membus.trans_dist::ReadResp 1036 # Transaction distribution -system.membus.trans_dist::ReadExReq 14567 # Transaction distribution -system.membus.trans_dist::ReadExResp 14567 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15603 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977060 # number of cpu cycles simulated +system.cpu.numCycles 722977061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977059.998000 # Number of busy cycles +system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -112,13 +89,141 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits +system.cpu.dcache.overall_hits::total 104182817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses +system.cpu.dcache.overall_misses::total 939567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks +system.cpu.dcache.writebacks::total 935266 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id @@ -141,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -159,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -179,33 +284,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy @@ -244,17 +349,17 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) @@ -279,17 +384,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,17 +414,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses @@ -331,146 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits -system.cpu.dcache.overall_hits::total 104182817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses -system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks -system.cpu.dcache.writebacks::total 935266 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution @@ -500,5 +477,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1036 # Transaction distribution +system.membus.trans_dist::ReadResp 1036 # Transaction distribution +system.membus.trans_dist::ReadExReq 14567 # Transaction distribution +system.membus.trans_dist::ReadExResp 14567 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15603 # Request fanout histogram +system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index a20619a99..22cc57507 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061857 # Number of seconds simulated -sim_ticks 61857343500 # Number of ticks simulated -final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062113 # Number of seconds simulated +sim_ticks 62113055500 # Number of ticks simulated +final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113051 # Simulator instruction rate (inst/s) -host_op_rate 199065 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44263102 # Simulator tick rate (ticks/s) -host_mem_usage 453712 # Number of bytes of host memory used -host_seconds 1397.49 # Real time elapsed on the host +host_inst_rate 113198 # Simulator instruction rate (inst/s) +host_op_rate 199324 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44503726 # Simulator tick rate (ticks/s) +host_mem_usage 454072 # Number of bytes of host memory used +host_seconds 1395.68 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory -system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12608 # Number of bytes written to this memory -system.physmem.bytes_written::total 12608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29452 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30462 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1044985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30472178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31517163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1044985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1044985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 203824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 203824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 203824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1044985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30472178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31720987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30463 # Number of read requests accepted -system.physmem.writeReqs 197 # Number of write requests accepted -system.physmem.readBursts 30463 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 197 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5888 # Total number of bytes read from write queue -system.physmem.bytesWritten 11328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1949632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 92 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 64896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10624 # Number of bytes written to this memory +system.physmem.bytes_written::total 10624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1014 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30436 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 166 # Number of write requests responded to by this memory +system.physmem.num_writes::total 166 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1044805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30315817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31360621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1044805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1044805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 171043 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 171043 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 171043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1044805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30315817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31531664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30436 # Number of read requests accepted +system.physmem.writeReqs 166 # Number of write requests accepted +system.physmem.readBursts 30436 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 166 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1943680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4224 # Total number of bytes read from write queue +system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1947904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1927 # Per bank write bursts -system.physmem.perBankRdBursts::1 2067 # Per bank write bursts -system.physmem.perBankRdBursts::2 2027 # Per bank write bursts -system.physmem.perBankRdBursts::3 1932 # Per bank write bursts +system.physmem.perBankRdBursts::0 1923 # Per bank write bursts +system.physmem.perBankRdBursts::1 2063 # Per bank write bursts +system.physmem.perBankRdBursts::2 2030 # Per bank write bursts +system.physmem.perBankRdBursts::3 1928 # Per bank write bursts system.physmem.perBankRdBursts::4 2026 # Per bank write bursts system.physmem.perBankRdBursts::5 1903 # Per bank write bursts system.physmem.perBankRdBursts::6 1964 # Per bank write bursts -system.physmem.perBankRdBursts::7 1863 # Per bank write bursts -system.physmem.perBankRdBursts::8 1937 # Per bank write bursts -system.physmem.perBankRdBursts::9 1937 # Per bank write bursts -system.physmem.perBankRdBursts::10 1804 # Per bank write bursts -system.physmem.perBankRdBursts::11 1796 # Per bank write bursts +system.physmem.perBankRdBursts::7 1866 # Per bank write bursts +system.physmem.perBankRdBursts::8 1938 # Per bank write bursts +system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts +system.physmem.perBankRdBursts::11 1795 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts system.physmem.perBankRdBursts::14 1818 # Per bank write bursts -system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts system.physmem.perBankWrBursts::0 15 # Per bank write bursts -system.physmem.perBankWrBursts::1 94 # Per bank write bursts -system.physmem.perBankWrBursts::2 13 # Per bank write bursts -system.physmem.perBankWrBursts::3 21 # Per bank write bursts +system.physmem.perBankWrBursts::1 80 # Per bank write bursts +system.physmem.perBankWrBursts::2 11 # Per bank write bursts +system.physmem.perBankWrBursts::3 10 # Per bank write bursts system.physmem.perBankWrBursts::4 7 # Per bank write bursts -system.physmem.perBankWrBursts::5 7 # Per bank write bursts -system.physmem.perBankWrBursts::6 12 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 13 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts @@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61857329000 # Total gap between requests +system.physmem.totGap 62113012500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30463 # Read request sizes (log2) +system.physmem.readPktSize::6 30436 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 197 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 166 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -146,22 +146,22 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,327 +193,324 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2724 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 716.922173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 515.538805 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 389.679049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 350 12.85% 12.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 254 9.32% 22.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 128 4.70% 26.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 108 3.96% 30.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 103 3.78% 34.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 103 3.78% 38.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 111 4.07% 42.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 70 2.57% 45.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1497 54.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2724 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 10 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3031.200000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.218074 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 9548.252985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 9 90.00% 90.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 10.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 10 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads -system.physmem.totQLat 130999000 # Total ticks spent queuing -system.physmem.totMemAccLat 700455250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4313.29 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 714.471449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 512.855124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 389.294613 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 368 13.47% 13.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 227 8.31% 21.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 131 4.80% 26.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 130 4.76% 31.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 109 3.99% 35.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 99 3.62% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 107 3.92% 42.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 79 2.89% 45.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1482 54.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2732 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3788.500000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.757307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10676.303052 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads +system.physmem.totQLat 135350500 # Total ticks spent queuing +system.physmem.totMemAccLat 704788000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151850000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4456.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23063.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23206.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 31.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage -system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing -system.physmem.readRowHits 27696 # Number of row buffer hits during reads -system.physmem.writeRowHits 119 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes -system.physmem.avgGap 2017525.41 # Average gap between requests -system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10939320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5968875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1095120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2776043070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34677412500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41633685525 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.093587 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57673269750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing +system.physmem.readRowHits 27681 # Number of row buffer hits during reads +system.physmem.writeRowHits 96 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes +system.physmem.avgGap 2029704.35 # Average gap between requests +system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 10931760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5964750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122311800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 881280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2875200840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34744599750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41816673300 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.255215 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57785258250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2074020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2115534000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2252296250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9623880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5251125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114246600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114332400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2977027920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34501101750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41647303755 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.313903 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57380456750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem_1.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3044489985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34596104250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41826776820 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.417815 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57536988500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2074020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2409426750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2500187750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37414357 # Number of BP lookups -system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits +system.cpu.branchPred.lookups 37409115 # Number of BP lookups +system.cpu.branchPred.condPredicted 37409115 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 796961 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 21404292 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21297612 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.501595 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5520840 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5370 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 123714688 # number of cpu cycles simulated +system.cpu.numCycles 124226112 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28240185 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94568946 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1664995 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.872113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.370891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28235935 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 201516528 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37409115 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26818452 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 95078093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1665601 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13635 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 27845177 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 203940 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 124161279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.860308 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.369086 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62738354 50.74% 50.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3652838 2.95% 53.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3508504 2.84% 56.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5967471 4.83% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7654257 6.19% 67.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5436238 4.40% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3366087 2.72% 74.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 63245394 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3661074 2.95% 53.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3505984 2.82% 56.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5966145 4.81% 61.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7636259 6.15% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5451035 4.39% 72.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3359633 2.71% 74.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2076013 1.67% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29259742 23.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13285381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63221156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18592314 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54481538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48119117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 124161279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.301137 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.622175 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13292806 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63720296 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 36521548 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9793829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 832800 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 335002829 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 832800 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18597256 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8862328 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16249 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 40799373 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55053273 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328652486 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2589 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 765140 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48300530 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4998296 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 330629230 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 873051813 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537695602 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 524 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 475 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66201491 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106325920 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36528653 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49813174 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8481864 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 325481116 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307976733 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 51416483 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 478 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 66182076 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106321382 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36530805 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49812358 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8510426 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 325477303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 46683880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.480559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.127626 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30107102 24.35% 24.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16727632 13.53% 53.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16031841 12.96% 80.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12684150 10.26% 90.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5762404 4.66% 95.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4173789 3.38% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1554837 1.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30601082 24.65% 24.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19574247 15.77% 40.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16779908 13.51% 53.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17045625 13.73% 67.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15969415 12.86% 80.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12663210 10.20% 90.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5764205 4.64% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4169219 3.36% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1594368 1.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 124161279 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 316999 7.53% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3711822 88.14% 95.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 182351 4.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 316891 7.52% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3711549 88.13% 95.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 182770 4.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 175394846 56.95% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11227 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 339 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 53 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 175395413 56.95% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11214 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98514236 31.99% 88.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34034780 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued -system.cpu.iq.rate 2.489411 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4211172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 743874545 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 312154274 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58255905 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307989355 # Type of FU issued +system.cpu.iq.rate 2.479264 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 372203676 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 58260510 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15541997 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 57887 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42363 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5091053 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 105171 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3649 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 124471 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 832497 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5705091 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3134574 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 325483411 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125197 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106325920 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36528653 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2776 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3138754 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41794 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 401755 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445201 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 846956 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 306897357 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98135370 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1079376 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 832800 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5705086 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3056605 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 325479429 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124396 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106321382 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36530805 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2770 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3059848 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42363 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 401945 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 444615 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 846560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 306916313 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98157297 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1073042 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed -system.cpu.iew.exec_branches 31536734 # Number of branches executed -system.cpu.iew.exec_stores 33824606 # Number of stores executed -system.cpu.iew.exec_rate 2.480687 # Inst execution rate -system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231632886 # num instructions producing a value -system.cpu.iew.wb_consumers 336126880 # num instructions consuming a value +system.cpu.iew.exec_refs 131977680 # number of memory reference insts executed +system.cpu.iew.exec_branches 31536553 # Number of branches executed +system.cpu.iew.exec_stores 33820383 # Number of stores executed +system.cpu.iew.exec_rate 2.470626 # Inst execution rate +system.cpu.iew.wb_sent 306317735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 305987161 # cumulative count of insts written-back +system.cpu.iew.wb_producers 231581512 # num instructions producing a value +system.cpu.iew.wb_consumers 336076811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back +system.cpu.iew.wb_rate 2.463147 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.689073 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 47389031 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117208008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 797726 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117712955 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.363312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.086758 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52857679 45.10% 45.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10970811 9.36% 68.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8748487 7.46% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1731776 1.48% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 53359699 45.33% 45.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15949045 13.55% 58.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10998829 9.34% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8750765 7.43% 75.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1918688 1.63% 77.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1725778 1.47% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 854994 0.73% 79.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 681396 0.58% 80.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23473761 19.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117208008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117712955 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,325 +556,325 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23468572 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 419324213 # The number of ROB reads -system.cpu.rob.rob_writes 657627213 # The number of ROB writes -system.cpu.timesIdled 611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58315 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 419820689 # The number of ROB reads +system.cpu.rob.rob_writes 657620446 # The number of ROB writes +system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.783061 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.783061 # CPI: Total CPI of All Threads -system.cpu.ipc 1.277040 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.277040 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 493625454 # number of integer regfile reads -system.cpu.int_regfile_writes 240898259 # number of integer regfile writes -system.cpu.fp_regfile_reads 178 # number of floating regfile reads -system.cpu.fp_regfile_writes 135 # number of floating regfile writes -system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads -system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes -system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads +system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads +system.cpu.ipc 1.271782 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.271782 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 493661924 # number of integer regfile reads +system.cpu.int_regfile_writes 240899982 # number of integer regfile writes +system.cpu.fp_regfile_reads 121 # number of floating regfile reads +system.cpu.fp_regfile_writes 99 # number of floating regfile writes +system.cpu.cc_regfile_reads 107697498 # number of cc regfile reads +system.cpu.cc_regfile_writes 64570083 # number of cc regfile writes +system.cpu.misc_regfile_reads 196298941 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072433 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68459745 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.968355 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072451 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.920590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68431233 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076547 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.954339 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19749732250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.920590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993145 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993145 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 585 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3383 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144502465 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144502465 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37113882 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37113882 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68459745 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68459745 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68459745 # number of overall hits -system.cpu.dcache.overall_hits::total 68459745 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses -system.cpu.dcache.overall_misses::total 2753223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861027000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31861027000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2765155494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34626182494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34626182494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34626182494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34626182494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39773216 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39773216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 144497109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 144497109 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37085404 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37085404 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345829 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345829 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68431233 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68431233 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68431233 # number of overall hits +system.cpu.dcache.overall_hits::total 68431233 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2685125 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2685125 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93923 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93923 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2779048 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2779048 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2779048 # number of overall misses +system.cpu.dcache.overall_misses::total 2779048 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32124036248 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32124036248 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2977938994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2977938994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35101975242 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35101975242 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35101975242 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35101975242 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39770529 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39770529 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71212968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71212968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71212968 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71212968 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.829411 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.829411 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.325437 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.325437 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12576.599314 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12576.599314 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 71210281 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 71210281 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 71210281 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 71210281 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067515 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039026 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039026 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039026 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039026 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11963.702341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11963.702341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31706.174143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31706.174143 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12630.935213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12630.935213 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 199096 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 39942 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.984628 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks -system.cpu.dcache.writebacks::total 2066654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009124500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009124500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972744 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972744 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524097244 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24524097244 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524097244 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24524097244 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066749 # number of writebacks +system.cpu.dcache.writebacks::total 2066749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690617 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 690617 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 702500 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 702500 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 702500 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 702500 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82040 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82040 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076548 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076548 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076548 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076548 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23032838251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23032838251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2765865745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2765865745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25798703996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25798703996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25798703996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25798703996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050150 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.913780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.913780 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.061317 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.061317 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11548.130291 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11548.130291 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33713.624391 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33713.624391 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 58 # number of replacements +system.cpu.icache.tags.tagsinuse 832.593358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27843840 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1028 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27085.447471 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.404157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55700266 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55700266 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27848273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27848273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27848273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27848273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits -system.cpu.icache.overall_hits::total 27848273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses -system.cpu.icache.overall_misses::total 1347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 92877749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 92877749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 92877749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 92877749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 92877749 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 880 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.473633 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55691382 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55691382 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27843840 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27843840 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27843840 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27843840 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27843840 # number of overall hits +system.cpu.icache.overall_hits::total 27843840 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1395 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27655 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913666 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33267098 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33267098 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1994043 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1994057 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066749 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066749 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2158751250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2237185250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 78434000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2158751250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2237185250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1028 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994469 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995497 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1028 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076548 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077576 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1028 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076548 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077576 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000722 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353269 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353269 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986381 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014650 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986381 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014650 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77351.084813 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76067.488263 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76971.354167 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73332.407918 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73332.407918 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73504.575174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73504.575174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,109 +883,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 197 # number of writebacks -system.cpu.l2cache.writebacks::total 197 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1465 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58476750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26090500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84567250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58476750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556132750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1614609500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58476750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556132750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1614609500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57897.772277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57341.758242 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57725.085324 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.716463 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.716463 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 166 # number of writebacks +system.cpu.l2cache.writebacks::total 166 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1440 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29422 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30436 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29422 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30436 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65771000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27116250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92887250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1763882000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1763882000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65771000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1790998250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1856769250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65771000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1790998250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1856769250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353269 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353269 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014650 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014650 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64862.919132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63653.169014 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64505.034722 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60831.907849 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60831.907849 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1995497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995496 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066749 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82079 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219844 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265170944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265236736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4144325 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4144325 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4144325 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4138911500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1734248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121417250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3121601499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1465 # Transaction distribution -system.membus.trans_dist::ReadResp 1462 # Transaction distribution -system.membus.trans_dist::Writeback 197 # Transaction distribution -system.membus.trans_dist::ReadExReq 28998 # Transaction distribution -system.membus.trans_dist::ReadExResp 28998 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1440 # Transaction distribution +system.membus.trans_dist::ReadResp 1439 # Transaction distribution +system.membus.trans_dist::Writeback 166 # Transaction distribution +system.membus.trans_dist::ReadExReq 28996 # Transaction distribution +system.membus.trans_dist::ReadExResp 28996 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1958464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30660 # Request fanout histogram +system.membus.snoop_fanout::samples 30602 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30602 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30660 # Request fanout histogram -system.membus.reqLayer0.occupancy 43499500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30602 # Request fanout histogram +system.membus.reqLayer0.occupancy 42540000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 291787500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 160392250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index f80736ade..05a346173 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365989065000 # Number of ticks simulated -final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 365989065500 # Number of ticks simulated +final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 756908 # Simulator instruction rate (inst/s) -host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1753418925 # Simulator tick rate (ticks/s) -host_mem_usage 446124 # Number of bytes of host memory used -host_seconds 208.73 # Real time elapsed on the host +host_inst_rate 638452 # Simulator instruction rate (inst/s) +host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1479007835 # Simulator tick rate (ticks/s) +host_mem_usage 450980 # Number of bytes of host memory used +host_seconds 247.46 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,36 +36,10 @@ system.physmem.bw_total::writebacks 17487 # To system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1025 # Transaction distribution -system.membus.trans_dist::ReadResp 1025 # Transaction distribution -system.membus.trans_dist::Writeback 100 # Transaction distribution -system.membus.trans_dist::ReadExReq 29024 # Transaction distribution -system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30149 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30149 # Request fanout histogram -system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731978130 # number of cpu cycles simulated +system.cpu.numCycles 731978131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 731978129.998000 # Number of busy cycles +system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -125,13 +99,121 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits +system.cpu.dcache.overall_hits::total 120152370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses +system.cpu.dcache.overall_misses::total 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks +system.cpu.dcache.writebacks::total 2062484 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -153,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -171,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -191,33 +273,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20041.899592 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646380 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy @@ -256,17 +338,17 @@ system.cpu.l2cache.demand_misses::total 30049 # nu system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses system.cpu.l2cache.overall_misses::total 30049 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11655000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 53813000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1535446000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1577604000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42158000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1535446000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1577604000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) @@ -291,17 +373,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,17 +405,17 @@ system.cpu.l2cache.demand_mshr_misses::total 30049 system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32521500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8991000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41512500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1175472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1175472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32521500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1184463000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1216984500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32521500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1184463000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1216984500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses @@ -345,126 +427,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits -system.cpu.dcache.overall_hits::total 120152370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses -system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks -system.cpu.dcache.writebacks::total 2062484 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution @@ -496,5 +470,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 1212000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1025 # Transaction distribution +system.membus.trans_dist::ReadResp 1025 # Transaction distribution +system.membus.trans_dist::Writeback 100 # Transaction distribution +system.membus.trans_dist::ReadExReq 29024 # Transaction distribution +system.membus.trans_dist::ReadExResp 29024 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30149 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30149 # Request fanout histogram +system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |