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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-06-06 17:16:44 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-06-06 17:16:44 +0100
commit85997e66a08b71d701e5b41462d1cfd42660b0c7 (patch)
treebc242f1a2bfc3a92b18da04805d9ebd8864b5320 /tests/long/se/10.mcf/ref
parent21b66f45422bc449d4a8b86ab452d6b6ae5838bf (diff)
downloadgem5-85997e66a08b71d701e5b41462d1cfd42660b0c7.tar.xz
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
Diffstat (limited to 'tests/long/se/10.mcf/ref')
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt25
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt26
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt21
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt24
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt24
5 files changed, 95 insertions, 25 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index be7e45565..c8a3d5425 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.061235 # Nu
sim_ticks 61234797500 # Number of ticks simulated
final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 196562 # Simulator instruction rate (inst/s)
-host_op_rate 197541 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 132848546 # Simulator tick rate (ticks/s)
-host_mem_usage 399976 # Number of bytes of host memory used
-host_seconds 460.94 # Real time elapsed on the host
+host_inst_rate 433531 # Simulator instruction rate (inst/s)
+host_op_rate 435690 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 293005809 # Simulator tick rate (ticks/s)
+host_mem_usage 447448 # Number of bytes of host memory used
+host_seconds 208.99 # Real time elapsed on the host
sim_insts 90602850 # Number of instructions simulated
sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
@@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 2044640000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 20750031 # Number of BP lookups
system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
@@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu
system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -381,6 +387,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 122469595 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class_0::total 91054081 # Class of committed instruction
system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 946097 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks.
@@ -443,6 +451,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits
@@ -563,6 +572,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
@@ -580,6 +590,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 740
system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits
@@ -648,6 +659,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236
system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
@@ -670,6 +682,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
@@ -820,6 +833,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
@@ -852,6 +866,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1202498 # La
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1029 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index d33c4ab3b..6265572cd 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.058199 # Nu
sim_ticks 58199030500 # Number of ticks simulated
final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 218368 # Simulator instruction rate (inst/s)
-host_op_rate 219455 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 140289424 # Simulator tick rate (ticks/s)
-host_mem_usage 534192 # Number of bytes of host memory used
-host_seconds 414.85 # Real time elapsed on the host
+host_inst_rate 220490 # Simulator instruction rate (inst/s)
+host_op_rate 221588 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 141652578 # Simulator tick rate (ticks/s)
+host_mem_usage 534836 # Number of bytes of host memory used
+host_seconds 410.86 # Real time elapsed on the host
sim_insts 90589799 # Number of instructions simulated
sim_ops 91041030 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory
@@ -273,6 +274,7 @@ system.physmem_1.memoryStateTime::REF 1943240000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 28233538 # Number of BP lookups
system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect
@@ -287,6 +289,7 @@ system.cpu.branchPred.indirectHits 25478 # Nu
system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -316,6 +319,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -345,6 +349,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -374,6 +379,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -404,6 +410,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 116398062 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -693,6 +700,7 @@ system.cpu.cc_regfile_reads 369004699 # nu
system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes
system.cpu.misc_regfile_reads 28410103 # number of misc regfile reads
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 5470634 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks.
@@ -708,6 +716,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 168
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits
@@ -838,6 +847,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 447 # number of replacements
system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks.
@@ -855,6 +865,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 335
system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses
system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits
@@ -929,12 +940,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044
system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 248 # number of replacements
system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks.
@@ -961,6 +974,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits
@@ -1146,6 +1160,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877
system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution
@@ -1184,6 +1199,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1357497 # La
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 16175 # Transaction distribution
system.membus.trans_dist::WritebackDirty 175 # Transaction distribution
system.membus.trans_dist::CleanEvict 63 # Transaction distribution
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 95463debe..b73adbdfb 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.361598 # Nu
sim_ticks 361597758500 # Number of ticks simulated
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 779266 # Simulator instruction rate (inst/s)
-host_op_rate 779298 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1155667536 # Simulator tick rate (ticks/s)
-host_mem_usage 379236 # Number of bytes of host memory used
-host_seconds 312.89 # Real time elapsed on the host
+host_inst_rate 1652209 # Simulator instruction rate (inst/s)
+host_op_rate 1652277 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2450259534 # Simulator tick rate (ticks/s)
+host_mem_usage 427260 # Number of bytes of host memory used
+host_seconds 147.58 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
@@ -29,8 +30,10 @@ system.physmem.bw_inst_read::total 155576 # In
system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 723195517 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -89,6 +92,7 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 935475 # number of replacements
system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
@@ -106,6 +110,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 46
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
@@ -214,6 +219,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 25 # number of replacements
system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
@@ -231,6 +237,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 781
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
@@ -299,6 +306,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948
system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
@@ -321,6 +329,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
@@ -461,6 +470,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
@@ -493,6 +503,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 7579adace..a14ecd97e 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.065987 # Nu
sim_ticks 65986743500 # Number of ticks simulated
final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 84238 # Simulator instruction rate (inst/s)
-host_op_rate 148330 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35183666 # Simulator tick rate (ticks/s)
-host_mem_usage 410392 # Number of bytes of host memory used
-host_seconds 1875.49 # Real time elapsed on the host
+host_inst_rate 167131 # Simulator instruction rate (inst/s)
+host_op_rate 294291 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69805272 # Simulator tick rate (ticks/s)
+host_mem_usage 458048 # Number of bytes of host memory used
+host_seconds 945.30 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory
system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory
@@ -272,6 +273,7 @@ system.physmem_1.memoryStateTime::REF 2203240000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 40828848 # Number of BP lookups
system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect
@@ -286,8 +288,12 @@ system.cpu.branchPred.indirectHits 21202389 # Nu
system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 131973488 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -582,6 +588,7 @@ system.cpu.cc_regfile_reads 109261684 # nu
system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes
system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2073508 # number of replacements
system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks.
@@ -598,6 +605,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 150
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits
@@ -694,6 +702,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 93 # number of replacements
system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks.
@@ -712,6 +721,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 906
system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses
system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits
@@ -786,6 +796,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707
system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 650 # number of replacements
system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks.
@@ -808,6 +819,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits
@@ -950,6 +962,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20
system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution
@@ -982,6 +995,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1670997 # La
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1640 # Transaction distribution
system.membus.trans_dist::WritebackDirty 280 # Transaction distribution
system.membus.trans_dist::CleanEvict 45 # Transaction distribution
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index be41a6e0b..8ce0adaa4 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.366199 # Nu
sim_ticks 366199170500 # Number of ticks simulated
final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 433838 # Simulator instruction rate (inst/s)
-host_op_rate 763918 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1005585249 # Simulator tick rate (ticks/s)
-host_mem_usage 405532 # Number of bytes of host memory used
-host_seconds 364.17 # Real time elapsed on the host
+host_inst_rate 926071 # Simulator instruction rate (inst/s)
+host_op_rate 1630662 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2146525407 # Simulator tick rate (ticks/s)
+host_mem_usage 453968 # Number of bytes of host memory used
+host_seconds 170.60 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory
system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory
@@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 17826 # To
system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 732398341 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 278192465 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2062733 # number of replacements
system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
@@ -116,6 +123,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 6
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
@@ -204,6 +212,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 24 # number of replacements
system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
@@ -220,6 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 715
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
@@ -288,6 +298,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921
system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 313 # number of replacements
system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks.
@@ -310,6 +321,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits
@@ -452,6 +464,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution
@@ -484,6 +497,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1212000 # La
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1020 # Transaction distribution
system.membus.trans_dist::WritebackDirty 102 # Transaction distribution
system.membus.trans_dist::CleanEvict 14 # Transaction distribution