diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
| commit | ebd9018a139178aed432b257ff4ce6dc2d5f795f (patch) | |
| tree | 0d844028751908a7c7f66f82e5bd9564467086c9 /tests/long/se/10.mcf/ref | |
| parent | 9e57e4e89d3c6b6d7e0f0f182bfd01c5585c16c5 (diff) | |
| download | gem5-ebd9018a139178aed432b257ff4ce6dc2d5f795f.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long/se/10.mcf/ref')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 386 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1482 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1520 |
3 files changed, 1694 insertions, 1694 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 0c54e3227..bf75cb6d5 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.062553 # Number of seconds simulated -sim_ticks 62552970500 # Number of ticks simulated -final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 62553193500 # Number of ticks simulated +final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 423901 # Simulator instruction rate (inst/s) -host_op_rate 426012 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 292664487 # Simulator tick rate (ticks/s) -host_mem_usage 404124 # Number of bytes of host memory used -host_seconds 213.74 # Real time elapsed on the host +host_inst_rate 434587 # Simulator instruction rate (inst/s) +host_op_rate 436752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 300043763 # Simulator tick rate (ticks/s) +host_mem_usage 405580 # Number of bytes of host memory used +host_seconds 208.48 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 790882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15143390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15934271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 790882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 790882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 790882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15143390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15934271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62552869500 # Total gap between requests +system.physmem.totGap 62553092500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # By system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 211081250 # Total ticks spent queuing -system.physmem.totMemAccLat 503093750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 211075250 # Total ticks spent queuing +system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13553.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32303.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s @@ -221,24 +221,24 @@ system.physmem.readRowHits 14027 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4016493.48 # Average gap between requests +system.physmem.avgGap 4016507.80 # Average gap between requests system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 136599930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8776800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 736788270 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 212075520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 14428808400 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 15801654720 # Total energy per rank (pJ) -system.physmem_0.averagePower 252.612376 # Core power per rank (mW) -system.physmem_0.totalIdleTime 62230500750 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ) +system.physmem_0.averagePower 252.612326 # Core power per rank (mW) +system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 60062510500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states @@ -247,21 +247,21 @@ system.physmem_1.preEnergy 2641320 # En system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 136420380 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13274400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 827381220 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 248160000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14377425165 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 15919954335 # Total energy per rank (pJ) -system.physmem_1.averagePower 254.503567 # Core power per rank (mW) -system.physmem_1.totalIdleTime 62217855000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.503484 # Core power per rank (mW) +system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 59758396500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 646214750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 203977250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1814551000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 20808248 # Number of BP lookups system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect @@ -276,7 +276,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62552970500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 125105941 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 125106387 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.380817 # CPI: cycles per instruction -system.cpu.ipc 0.724209 # IPC: instructions per cycle +system.cpu.cpi 1.380822 # CPI: cycles per instruction +system.cpu.ipc 0.724206 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110521627 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14584314 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.108293 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274912 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.652068 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.108293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -465,9 +465,9 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605963 # number of ReadReq hits +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits @@ -476,28 +476,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266630 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266630 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26267138 # number of overall hits -system.cpu.dcache.overall_hits::total 26267138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906313 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906313 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits +system.cpu.dcache.overall_hits::total 26266955 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980627 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980627 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980631 # number of overall misses -system.cpu.dcache.overall_misses::total 980631 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11831745500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11831745500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760211000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2760211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14591956500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14591956500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14591956500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14591956500 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses +system.cpu.dcache.overall_misses::total 980814 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -512,24 +512,24 @@ system.cpu.dcache.demand_accesses::cpu.data 27247257 # system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035990 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035990 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14880.231219 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14880.170523 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,14 +538,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2883 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2883 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30433 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30433 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30433 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30433 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses @@ -556,16 +556,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194 system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889954000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889954000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596188500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486142500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12486142500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486312500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12486312500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -576,24 +576,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.568004 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.568004 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id @@ -604,7 +604,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 740 system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits @@ -617,12 +617,12 @@ system.cpu.icache.demand_misses::cpu.inst 801 # n system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses system.cpu.icache.overall_misses::total 801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71410000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 71410000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71410000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 71410000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71410000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 71410500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 71410500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71410500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 71410500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71410500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27835884 # number of demand (read+write) accesses @@ -635,12 +635,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 89151.061174 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 89151.061174 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 89151.685393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 89151.685393 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,36 +655,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801 system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 70609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 70609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 70609000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70609500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 70609500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 70609500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11307.978899 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 11307.993669 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.572897 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.573080 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.345092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id @@ -694,7 +694,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -723,18 +723,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses system.cpu.l2cache.overall_misses::total 15581 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182252000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1182252000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69100500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 69100500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182247000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1182247000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69101000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 69101000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49237000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 69100500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1231489000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1300589500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 69100500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1231489000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1300589500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 69101000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1231484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1300585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 69101000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1231484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1300585000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) @@ -763,18 +763,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -803,18 +803,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036812000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036812000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083046000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1144343000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083046000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1144343000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses @@ -827,25 +827,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -885,7 +885,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution @@ -906,7 +906,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21777000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 4f68c8fbf..2da35dc4f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058675 # Number of seconds simulated -sim_ticks 58675371500 # Number of ticks simulated -final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058681 # Number of seconds simulated +sim_ticks 58681066500 # Number of ticks simulated +final_tick 58681066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 241655 # Simulator instruction rate (inst/s) -host_op_rate 242858 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 156520643 # Simulator tick rate (ticks/s) -host_mem_usage 492304 # Number of bytes of host memory used -host_seconds 374.87 # Real time elapsed on the host +host_inst_rate 243006 # Simulator instruction rate (inst/s) +host_op_rate 244216 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157411271 # Simulator tick rate (ticks/s) +host_mem_usage 492224 # Number of bytes of host memory used +host_seconds 372.79 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory -system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory -system.physmem.bytes_written::total 6656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18533 # Number of read requests accepted -system.physmem.writeReqs 104 # Number of write requests accepted -system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 219520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 922368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1186688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6784 # Number of bytes written to this memory +system.physmem.bytes_written::total 6784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14412 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18542 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 106 # Number of write requests responded to by this memory +system.physmem.num_writes::total 106 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 763449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3740900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15718324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20222673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 763449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 763449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 115608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 115608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 115608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 763449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3740900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15718324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20338281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18543 # Number of read requests accepted +system.physmem.writeReqs 106 # Number of write requests accepted +system.physmem.readBursts 18543 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 106 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1180544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one +system.physmem.bytesReadSys 1186752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 3245 # Per bank write bursts system.physmem.perBankRdBursts::1 921 # Per bank write bursts -system.physmem.perBankRdBursts::2 952 # Per bank write bursts +system.physmem.perBankRdBursts::2 954 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1118 # Per bank write bursts -system.physmem.perBankRdBursts::6 1097 # Per bank write bursts -system.physmem.perBankRdBursts::7 1096 # Per bank write bursts +system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::6 1093 # Per bank write bursts +system.physmem.perBankRdBursts::7 1100 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 932 # Per bank write bursts +system.physmem.perBankRdBursts::10 933 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts system.physmem.perBankRdBursts::13 895 # Per bank write bursts system.physmem.perBankRdBursts::14 1401 # Per bank write bursts -system.physmem.perBankRdBursts::15 903 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankWrBursts::0 2 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 3 # Per bank write bursts -system.physmem.perBankWrBursts::3 3 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts system.physmem.perBankWrBursts::4 12 # Per bank write bursts -system.physmem.perBankWrBursts::5 10 # Per bank write bursts -system.physmem.perBankWrBursts::6 15 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::6 10 # Per bank write bursts +system.physmem.perBankWrBursts::7 7 # Per bank write bursts system.physmem.perBankWrBursts::8 1 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts system.physmem.perBankWrBursts::10 1 # Per bank write bursts -system.physmem.perBankWrBursts::11 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 5 # Per bank write bursts system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 7 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 8 # Per bank write bursts +system.physmem.perBankWrBursts::15 6 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58675363000 # Total gap between requests +system.physmem.totGap 58681058000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18533 # Read request sizes (log2) +system.physmem.readPktSize::6 18543 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 104 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see +system.physmem.writePktSize::6 106 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 12536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 100 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -162,7 +162,7 @@ system.physmem.wrQLenPdf::24 5 # Wh system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see @@ -198,24 +198,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.104980 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.970166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.874685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 839 28.23% 28.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 987 33.21% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89 2.99% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 64 2.15% 66.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 64 2.15% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 65 2.19% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 54 1.82% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 55 1.85% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 755 25.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2972 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4544.500000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 1447.547305 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7502.381200 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes @@ -225,82 +225,82 @@ system.physmem.wrPerTurnAround::mean 18 # Wr system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.physmem.totQLat 819558662 # Total ticks spent queuing -system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst +system.physmem.totQLat 829373528 # Total ticks spent queuing +system.physmem.totMemAccLat 1175236028 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44962.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 63712.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.16 # Data bus utilization in percentage system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing -system.physmem.readRowHits 15523 # Number of row buffer hits during reads -system.physmem.writeRowHits 12 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes -system.physmem.avgGap 3148326.61 # Average gap between requests -system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ) -system.physmem_0.averagePower 336.815504 # Core power per rank (mW) -system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states -system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states -system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states -system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ) -system.physmem_1.averagePower 255.006594 # Core power per rank (mW) -system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states -system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states -system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28234010 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.34 # Average write queue length when enqueuing +system.physmem.readRowHits 15527 # Number of row buffer hits during reads +system.physmem.writeRowHits 11 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.00 # Row buffer hit rate for writes +system.physmem.avgGap 3146606.15 # Average gap between requests +system.physmem.pageHitRate 83.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15943620 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8459055 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 75134220 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 203580 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1849451760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 458311920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 99516480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 3997068570 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3182851200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 10077393330 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19767987555 # Total energy per rank (pJ) +system.physmem_0.averagePower 336.871642 # Core power per rank (mW) +system.physmem_0.totalIdleTime 57408712347 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 196273000 # Time in different power states +system.physmem_0.memoryStateTime::REF 786774000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 40354533250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8288648060 # Time in different power states +system.physmem_0.memoryStateTime::ACT 289307153 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 8765531037 # Time in different power states +system.physmem_1.actEnergy 5333580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2819685 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 56563080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 172260 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 259378080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 131548590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 14205120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 785395590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 262919520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 13470232590 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14988765045 # Total energy per rank (pJ) +system.physmem_1.averagePower 255.427603 # Core power per rank (mW) +system.physmem_1.totalIdleTime 58353780091 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23548250 # Time in different power states +system.physmem_1.memoryStateTime::REF 110212000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 55948105250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 684663397 # Time in different power states +system.physmem_1.memoryStateTime::ACT 192205159 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1722332444 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28234239 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835421 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829840 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11748052 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.308630 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74543 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 27224 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25476 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1748 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,132 +421,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117350744 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117362134 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746504 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134908625 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28234239 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11848071 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115710996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674249 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 948 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275841 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117296446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.155292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.317650 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59759710 50.95% 50.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13934020 11.88% 62.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230571 7.87% 70.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34372145 29.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 117296446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.240574 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.149507 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8834504 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 65062525 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33013030 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825408 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097904 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 114396314 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1984657 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825408 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15270391 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50319403 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 113009 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35408802 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15359433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110873352 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412133 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133960 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1550028 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2088318 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 507009 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129946854 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483157007 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119448195 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22633935 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21513701 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805540 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347415 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 519015 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253842 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109668195 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101366364 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074602 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18635448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41675725 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 117296446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.864190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988217 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55661536 47.45% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31364227 26.74% 74.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008293 18.76% 92.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7064324 6.02% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197751 1.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 315 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117296446 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615891 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702910 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9780929 48.66% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614642 47.84% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702971 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970702 71.00% 71.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued @@ -571,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 57 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337764 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047220 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337480 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047270 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued -system.cpu.iq.rate 0.863794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20102384 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 467 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 247 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101366364 # Type of FU issued +system.cpu.iq.rate 0.863706 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20098632 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198277 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 341201935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128312613 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99607782 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 473 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121464746 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288157 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329629 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1502 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1344 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602571 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 130792 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825408 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8297291 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 773487 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109689301 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26805540 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347415 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 182523 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 427569 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1344 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435014 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412394 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847408 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100110032 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23803163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1256332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12823 # number of nop insts executed -system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621332 # Number of branches executed -system.cpu.iew.exec_stores 4915668 # Number of stores executed -system.cpu.iew.exec_rate 0.853083 # Inst execution rate -system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59691499 # num instructions producing a value -system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value -system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28718949 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621210 # Number of branches executed +system.cpu.iew.exec_stores 4915786 # Number of stores executed +system.cpu.iew.exec_rate 0.853001 # Inst execution rate +system.cpu.iew.wb_sent 99693474 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99607900 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59692176 # num instructions producing a value +system.cpu.iew.wb_consumers 95528763 # num instructions consuming a value +system.cpu.iew.wb_rate 0.848723 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624861 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17363908 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823705 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 114608461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.794476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.731976 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78183874 68.22% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18612814 16.24% 84.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7153278 6.24% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469165 3.03% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644308 1.43% 95.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541542 0.47% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703493 0.61% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179022 0.16% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120965 3.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 114608461 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,80 +704,80 @@ system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218887121 # The number of ROB reads -system.cpu.rob.rob_writes 219522508 # The number of ROB writes -system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120965 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218899309 # The number of ROB reads +system.cpu.rob.rob_writes 219523661 # The number of ROB writes +system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 65688 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108097860 # number of integer regfile reads -system.cpu.int_regfile_writes 58692141 # number of integer regfile writes +system.cpu.cpi 1.295534 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.295534 # CPI: Total CPI of All Threads +system.cpu.ipc 0.771883 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.771883 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108098001 # number of integer regfile reads +system.cpu.int_regfile_writes 58691976 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes -system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads +system.cpu.fp_regfile_writes 98 # number of floating regfile writes +system.cpu.cc_regfile_reads 369004563 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686890 # number of cc regfile writes +system.cpu.misc_regfile_reads 28409682 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470621 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 5470632 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.769242 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249828 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335651 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38122500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.769242 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61906996 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906996 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13887361 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887361 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354163 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354163 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits -system.cpu.dcache.overall_hits::total 18241616 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18241524 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18241524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18242046 # number of overall hits +system.cpu.dcache.overall_hits::total 18242046 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380818 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380818 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses -system.cpu.dcache.overall_misses::total 9968629 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9968099 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968099 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968106 # number of overall misses +system.cpu.dcache.overall_misses::total 9968106 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89375617500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89375617500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4089956224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4089956224 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 93465573724 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93465573724 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93465573724 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93465573724 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474642 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474642 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -786,307 +786,307 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210152 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210152 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080427 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080427 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353358 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353358 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353352 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353352 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.311248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.311248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10739.923596 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10739.923596 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9376.469247 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9376.469247 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9376.462662 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9376.462662 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331655 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 128757 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121530 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks -system.cpu.dcache.writebacks::total 5470621 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.728997 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.027804 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks +system.cpu.dcache.writebacks::total 5470632 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338725 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338725 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158229 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158229 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496954 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496954 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248556 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248556 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222589 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222589 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43819499500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43819499500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2297613115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2297613115 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46117112615 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46117112615 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46117348115 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46117348115 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047009 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047009 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.867670 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.867670 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10322.222190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10322.222190 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.151963 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.151963 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.188844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.188844 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 448 # number of replacements -system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 427.601453 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32274679 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35623.266004 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 427.601453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835159 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64552224 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64552224 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32274508 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32274508 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32274508 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32274508 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32274508 # number of overall hits -system.cpu.icache.overall_hits::total 32274508 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1151 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1151 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1151 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1151 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1151 # number of overall misses -system.cpu.icache.overall_misses::total 1151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 79113980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 79113980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 79113980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 79113980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 79113980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 79113980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275659 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275659 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275659 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275659 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275659 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275659 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64552564 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64552564 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32274679 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32274679 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32274679 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32274679 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32274679 # number of overall hits +system.cpu.icache.overall_hits::total 32274679 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1150 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1150 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1150 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1150 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1150 # number of overall misses +system.cpu.icache.overall_misses::total 1150 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 79102980 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 79102980 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 79102980 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 79102980 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 79102980 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 79102980 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32275829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32275829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32275829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32275829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32275829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32275829 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68734.995656 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68734.995656 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21173 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 759 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68785.200000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68785.200000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68785.200000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68785.200000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21255 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 760 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 230 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.102222 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 126.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.413043 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 126.666667 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 448 # number of writebacks system.cpu.icache.writebacks::total 448 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60405484 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 60405484 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60405484 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 60405484 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60405484 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 60405484 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60408984 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 60408984 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60408984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 60408984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60408984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 60408984 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66599.210584 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66599.210584 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 4988856 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5295771 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 266816 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66603.069460 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66603.069460 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66603.069460 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66603.069460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66603.069460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66603.069460 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 4986166 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5293297 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 266998 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074045 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 140 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11212.925557 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5291618 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14696 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 360.071992 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074663 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 148 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11219.998633 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5292017 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14707 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 359.829809 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11154.278216 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 58.647341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.680803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003580 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.684383 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 60 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 477 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3389 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9672 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11153.900503 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.098130 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.680780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004034 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.684814 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 64 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14495 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3398 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9680 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 839 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003662 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180525801 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180525801 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 5457281 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5457281 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10913 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10913 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226015 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226015 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 206 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 206 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241513 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5241513 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 206 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5467528 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5467734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 206 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5467528 # number of overall hits -system.cpu.l2cache.overall_hits::total 5467734 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 505 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 505 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3605 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4306 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3605 # number of overall misses -system.cpu.l2cache.overall_misses::total 4306 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 63500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 63500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64129500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64129500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58109500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 58109500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 616309000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 616309000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58109500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 680438500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 738548000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58109500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 680438500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 738548000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457281 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 5457281 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10913 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10913 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 226520 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 226520 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 832 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003906 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884705 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180526200 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180526200 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 5457195 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5457195 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 11011 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 11011 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 225669 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 225669 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 205 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 205 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241856 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 5241856 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 205 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5467525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5467730 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 205 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5467525 # number of overall hits +system.cpu.l2cache.overall_hits::total 5467730 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 501 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 501 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 702 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 702 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3118 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 3118 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 702 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3619 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4321 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 702 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3619 # number of overall misses +system.cpu.l2cache.overall_misses::total 4321 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 106500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 106500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63936500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 63936500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58121500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 58121500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 619277500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 619277500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58121500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 683214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 741335500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58121500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 683214000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 741335500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457195 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5457195 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226170 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 226170 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 907 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 907 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244613 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 5244613 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244974 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 5244974 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 907 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5471133 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5472040 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 907 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5471133 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5472040 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002229 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002229 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772878 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772878 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772878 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000787 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772878 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000787 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002215 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002215 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.773980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.773980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000594 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000594 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.773980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000661 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.773980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000661 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21300 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21300 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127617.764471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127617.764471 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82794.159544 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82794.159544 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198613.694676 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198613.694676 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 171565.725526 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 171565.725526 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1094,167 +1094,167 @@ system.cpu.l2cache.blocked::no_targets 0 # nu system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks -system.cpu.l2cache.writebacks::total 104 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 106 # number of writebacks +system.cpu.l2cache.writebacks::total 106 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 30 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 188 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 195 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316848 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 316848 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 188 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 189 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316628 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 316628 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3068 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3068 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3411 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4111 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3411 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316848 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 320959 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1079223443 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45646000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45646000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53848500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53848500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 589212500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 589212500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53848500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 634858500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 688707000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53848500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 701 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 701 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3088 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3088 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3431 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4132 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3431 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 320760 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1087453464 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53854500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53854500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 591148000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 591148000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53854500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 636757000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 690611500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53854500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 636757000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1778064964 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001517 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001517 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000589 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000589 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000755 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058618 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3434.482939 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 132970.845481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 132970.845481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76825.249643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76825.249643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 191433.937824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 191433.937824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167137.342691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5543.287704 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943136 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471098 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2874 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 302216 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302215 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5245880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5457301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318509 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226170 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226170 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244974 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415197 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318864 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318663 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7168 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052689 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223412 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485610 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305102 5.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5790713 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942648026 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1361495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 18697 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3032 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18190 # Transaction distribution -system.membus.trans_dist::WritebackDirty 104 # Transaction distribution -system.membus.trans_dist::CleanEvict 36 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18200 # Transaction distribution +system.membus.trans_dist::WritebackDirty 106 # Transaction distribution +system.membus.trans_dist::CleanEvict 42 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::ReadExReq 342 # Transaction distribution system.membus.trans_dist::ReadExResp 342 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 18201 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37239 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1193472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1193472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18537 # Request fanout histogram +system.membus.snoop_fanout::samples 18549 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18549 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18537 # Request fanout histogram -system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 18549 # Request fanout histogram +system.membus.reqLayer0.occupancy 29669004 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 97336094 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 48f2e7ba9..716a9adc9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.066079 # Number of seconds simulated -sim_ticks 66079350000 # Number of ticks simulated -final_tick 66079350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065833 # Number of seconds simulated +sim_ticks 65832730500 # Number of ticks simulated +final_tick 65832730500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185548 # Simulator instruction rate (inst/s) -host_op_rate 326721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77606283 # Simulator tick rate (ticks/s) -host_mem_usage 417148 # Number of bytes of host memory used -host_seconds 851.47 # Real time elapsed on the host +host_inst_rate 190384 # Simulator instruction rate (inst/s) +host_op_rate 335236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79331786 # Simulator tick rate (ticks/s) +host_mem_usage 416808 # Number of bytes of host memory used +host_seconds 829.84 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1892800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 69952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory system.physmem.bytes_read::total 1962496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19520 # Number of bytes written to this memory -system.physmem.bytes_written::total 19520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29575 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 69952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory +system.physmem.bytes_written::total 19776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory system.physmem.num_reads::total 30664 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 305 # Number of write requests responded to by this memory -system.physmem.num_writes::total 305 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1054732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28644350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29699081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1054732 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1054732 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 295402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 295402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 295402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1054732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28644350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29994484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory +system.physmem.num_writes::total 309 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1062572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28747767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29810339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1062572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1062572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 300398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 300398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 300398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1062572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28747767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30110736 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 30664 # Number of read requests accepted -system.physmem.writeReqs 305 # Number of write requests accepted +system.physmem.writeReqs 309 # Number of write requests accepted system.physmem.readBursts 30664 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 305 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1954304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue system.physmem.bytesWritten 18368 # Total number of bytes written to DRAM system.physmem.bytesReadSys 1962496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1940 # Per bank write bursts -system.physmem.perBankRdBursts::1 2080 # Per bank write bursts -system.physmem.perBankRdBursts::2 2040 # Per bank write bursts -system.physmem.perBankRdBursts::3 1947 # Per bank write bursts -system.physmem.perBankRdBursts::4 2062 # Per bank write bursts +system.physmem.perBankRdBursts::0 1947 # Per bank write bursts +system.physmem.perBankRdBursts::1 2076 # Per bank write bursts +system.physmem.perBankRdBursts::2 2053 # Per bank write bursts +system.physmem.perBankRdBursts::3 1954 # Per bank write bursts +system.physmem.perBankRdBursts::4 2067 # Per bank write bursts system.physmem.perBankRdBursts::5 1911 # Per bank write bursts system.physmem.perBankRdBursts::6 1975 # Per bank write bursts -system.physmem.perBankRdBursts::7 1870 # Per bank write bursts -system.physmem.perBankRdBursts::8 1951 # Per bank write bursts -system.physmem.perBankRdBursts::9 1941 # Per bank write bursts +system.physmem.perBankRdBursts::7 1868 # Per bank write bursts +system.physmem.perBankRdBursts::8 1952 # Per bank write bursts +system.physmem.perBankRdBursts::9 1938 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1799 # Per bank write bursts system.physmem.perBankRdBursts::14 1826 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 26 # Per bank write bursts -system.physmem.perBankWrBursts::1 125 # Per bank write bursts -system.physmem.perBankWrBursts::2 27 # Per bank write bursts -system.physmem.perBankWrBursts::3 24 # Per bank write bursts +system.physmem.perBankWrBursts::0 25 # Per bank write bursts +system.physmem.perBankWrBursts::1 120 # Per bank write bursts +system.physmem.perBankWrBursts::2 28 # Per bank write bursts +system.physmem.perBankWrBursts::3 32 # Per bank write bursts system.physmem.perBankWrBursts::4 54 # Per bank write bursts -system.physmem.perBankWrBursts::5 3 # Per bank write bursts -system.physmem.perBankWrBursts::6 18 # Per bank write bursts -system.physmem.perBankWrBursts::7 1 # Per bank write bursts +system.physmem.perBankWrBursts::5 2 # Per bank write bursts +system.physmem.perBankWrBursts::6 17 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 6 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 66079146500 # Total gap between requests +system.physmem.totGap 65832525500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,12 +97,12 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 305 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -147,12 +147,12 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see @@ -160,18 +160,18 @@ system.physmem.wrQLenPdf::26 16 # Wh system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,355 +194,355 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 685.122783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 477.283945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 398.354531 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 431 14.99% 14.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 281 9.77% 24.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 140 4.87% 29.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 134 4.66% 34.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 130 4.52% 38.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 125 4.35% 43.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 77 2.68% 45.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 84 2.92% 48.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1473 51.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 688.995108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 484.121076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 395.829774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 415 14.50% 14.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 275 9.61% 24.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 149 5.21% 29.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 128 4.47% 33.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 140 4.89% 38.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 122 4.26% 42.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 77 2.69% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 86 3.00% 48.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1470 51.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2862 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1904.687500 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.337942 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7552.888425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1905.625000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 24.516989 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7552.373489 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 15 93.75% 93.75% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 6.25% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.937500 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.900644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.181454 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3 18.75% 18.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 10 62.50% 81.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 6.25% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2 12.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.914548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.928709 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 12 75.00% 87.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 6.25% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 407578000 # Total ticks spent queuing -system.physmem.totMemAccLat 979678000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13357.96 # Average queueing delay per DRAM burst +system.physmem.totQLat 411710000 # Total ticks spent queuing +system.physmem.totMemAccLat 984260000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152680000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13482.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32107.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32232.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.69 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.28 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.50 # Average write queue length when enqueuing -system.physmem.readRowHits 27718 # Number of row buffer hits during reads -system.physmem.writeRowHits 199 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.25 # Row buffer hit rate for writes -system.physmem.avgGap 2133719.09 # Average gap between requests -system.physmem.pageHitRate 90.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11095560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5886045 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 112990500 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 14.03 # Average write queue length when enqueuing +system.physmem.readRowHits 27751 # Number of row buffer hits during reads +system.physmem.writeRowHits 206 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes +system.physmem.avgGap 2125481.08 # Average gap between requests +system.physmem.pageHitRate 90.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11059860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5878455 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 113176140 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 1451160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 311007840.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 261882510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 17017920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 979925760 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 266852640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15064489440 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 17032599375 # Total energy per rank (pJ) -system.physmem_0.averagePower 257.759790 # Core power per rank (mW) -system.physmem_0.totalIdleTime 65460562250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 23034750 # Time in different power states -system.physmem_0.memoryStateTime::REF 131986000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62616842500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 694916500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 463599750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 2148970500 # Time in different power states -system.physmem_1.actEnergy 9481920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5024580 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 104865180 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 315310320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 256763340 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17698560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 981638610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 270128640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15008515620 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 16981623105 # Total energy per rank (pJ) +system.physmem_0.averagePower 257.950589 # Core power per rank (mW) +system.physmem_0.totalIdleTime 65223686000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 24830750 # Time in different power states +system.physmem_0.memoryStateTime::REF 133713250 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62367507500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 703478750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 450500500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 2152699750 # Time in different power states +system.physmem_1.actEnergy 9403380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4982835 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 104850900 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 381691440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 255809160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 19980960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1151008410 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 399268320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14907041175 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17234823375 # Total energy per rank (pJ) -system.physmem_1.averagePower 260.820111 # Core power per rank (mW) -system.physmem_1.totalIdleTime 65463256000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 30077000 # Time in different power states -system.physmem_1.memoryStateTime::REF 162078000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 61901089500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1039749000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 422083750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2524272750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40670761 # Number of BP lookups -system.cpu.branchPred.condPredicted 40670761 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1447235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26704882 # Number of BTB lookups +system.physmem_1.refreshEnergy 389067120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 256987920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 20546880 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1156119600 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 409490400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14841811380 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17194149375 # Total energy per rank (pJ) +system.physmem_1.averagePower 261.179341 # Core power per rank (mW) +system.physmem_1.totalIdleTime 65212352000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 31901000 # Time in different power states +system.physmem_1.memoryStateTime::REF 165222000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 61612056250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1066374000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 421666750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2535510500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40426123 # Number of BP lookups +system.cpu.branchPred.condPredicted 40426123 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1402729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26580139 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6058055 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92918 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26704882 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21174798 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5530084 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 547932 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 6011508 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 87453 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26580139 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21161652 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5418487 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 517301 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 132158701 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131665462 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30720551 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 221310466 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40670761 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27232853 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99729501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3011659 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 476 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6367 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 115460 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 59 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29905952 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 30553171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219967171 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40426123 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27173160 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99460538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2919977 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 306 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5927 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 105822 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 73 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 157 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29763575 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 354176 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 15 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 132078466 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.949325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.409240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 131585982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.941987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.406730 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66113924 50.06% 50.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4057337 3.07% 53.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3620378 2.74% 55.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6125698 4.64% 60.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7769884 5.88% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5562288 4.21% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3378570 2.56% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2898316 2.19% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32552071 24.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65985920 50.15% 50.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4028379 3.06% 53.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3611314 2.74% 55.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6113229 4.65% 60.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7745533 5.89% 66.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5553246 4.22% 70.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3377028 2.57% 73.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2847646 2.16% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32323687 24.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 132078466 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307742 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.674581 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15424627 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64723504 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40539404 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9885102 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1505829 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 364367574 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1505829 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20975204 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11377644 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18396 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44575622 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53625771 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 354569179 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16511 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 791289 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46695905 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5223216 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 357047318 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 939748965 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 578695140 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 22535 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131585982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307037 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.670652 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15243618 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64765794 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40224064 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9892518 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1459988 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 362269877 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1459988 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20789530 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11237370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18362 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44279240 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53801492 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352719757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16498 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 793095 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46882908 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5193491 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 355158766 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 934950269 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575705414 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 24139 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 77834571 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 494 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 495 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64563941 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112883257 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38651230 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51754424 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9024100 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 345545955 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 318634973 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 172634 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 67357749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 104786759 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3813 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 132078466 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.412467 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.166876 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75946019 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 487 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 484 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64820498 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112428453 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38501164 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51645718 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9056873 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344114716 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4351 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317908509 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166833 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65926603 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 102202913 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3906 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131585982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.415976 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.164934 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 36007190 27.26% 27.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20156467 15.26% 42.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17165000 13.00% 55.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17631185 13.35% 68.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15357300 11.63% 80.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12905365 9.77% 90.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6726655 5.09% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4095436 3.10% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2033868 1.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35686444 27.12% 27.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20105227 15.28% 42.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17162197 13.04% 55.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17623881 13.39% 68.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15350950 11.67% 80.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12863479 9.78% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6692822 5.09% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4078738 3.10% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2022244 1.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 132078466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131585982 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 366214 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3544032 86.41% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 189377 4.62% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 6 0.00% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1660 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364988 8.91% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3541451 86.44% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 188937 4.61% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 10 0.00% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1524 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 182328648 57.22% 57.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11540 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 353 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101489286 31.85% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34764932 10.91% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 469 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 6130 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181836417 57.20% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11458 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 362 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 334 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101309174 31.87% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34711229 10.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 553 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 5642 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 318634973 # Type of FU issued -system.cpu.iq.rate 2.411003 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4101289 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012871 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 773603045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 412934380 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314305089 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 19290 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 34996 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4478 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 322694382 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8540 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57471685 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317908509 # Type of FU issued +system.cpu.iq.rate 2.414517 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4096910 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012887 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 771648435 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410069961 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313720076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18308 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36184 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321964016 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8063 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57535034 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 22103872 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67270 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 64283 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7211478 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21649068 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67666 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 63141 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7061412 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3969 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 140998 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4025 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141941 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1505829 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8247421 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3042364 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 345550213 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133191 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112883257 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38651230 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1745 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2963 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3048582 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 64283 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 545574 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1082259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1627833 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 316133024 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100718075 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2501949 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1459988 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8072611 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3068372 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344119067 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 127232 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112428453 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38501164 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1782 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2921 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3074772 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 63141 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 534039 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1041947 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1575986 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315496434 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100557512 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2412075 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 135067596 # number of memory reference insts executed -system.cpu.iew.exec_branches 32155475 # Number of branches executed -system.cpu.iew.exec_stores 34349521 # Number of stores executed -system.cpu.iew.exec_rate 2.392071 # Inst execution rate -system.cpu.iew.wb_sent 314966910 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314309567 # cumulative count of insts written-back -system.cpu.iew.wb_producers 238188610 # num instructions producing a value -system.cpu.iew.wb_consumers 344086280 # num instructions consuming a value -system.cpu.iew.wb_rate 2.378274 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692235 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 67483313 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134869578 # number of memory reference insts executed +system.cpu.iew.exec_branches 32108537 # Number of branches executed +system.cpu.iew.exec_stores 34312066 # Number of stores executed +system.cpu.iew.exec_rate 2.396197 # Inst execution rate +system.cpu.iew.wb_sent 314359591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313724392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237724315 # num instructions producing a value +system.cpu.iew.wb_consumers 343443925 # num instructions consuming a value +system.cpu.iew.wb_rate 2.382739 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692178 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 66051294 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1453904 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122408865 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.272650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.045643 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1408834 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122136825 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.277712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.048100 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57244612 46.77% 46.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16526306 13.50% 60.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11253907 9.19% 69.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8747083 7.15% 76.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2074138 1.69% 78.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1764583 1.44% 79.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 930878 0.76% 80.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 726504 0.59% 81.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23140854 18.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57021615 46.69% 46.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16508640 13.52% 60.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11210798 9.18% 69.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8746505 7.16% 76.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2078517 1.70% 78.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1759712 1.44% 79.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 926228 0.76% 80.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 725763 0.59% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23159047 18.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122408865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122136825 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -592,451 +592,451 @@ system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23140854 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 444943788 # The number of ROB reads -system.cpu.rob.rob_writes 701094607 # The number of ROB writes -system.cpu.timesIdled 892 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80235 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23159047 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 443221536 # The number of ROB reads +system.cpu.rob.rob_writes 698006714 # The number of ROB writes +system.cpu.timesIdled 877 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79480 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.836508 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.836508 # CPI: Total CPI of All Threads -system.cpu.ipc 1.195446 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.195446 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 503639899 # number of integer regfile reads -system.cpu.int_regfile_writes 248370602 # number of integer regfile writes -system.cpu.fp_regfile_reads 4288 # number of floating regfile reads -system.cpu.fp_regfile_writes 677 # number of floating regfile writes -system.cpu.cc_regfile_reads 109192725 # number of cc regfile reads -system.cpu.cc_regfile_writes 65564647 # number of cc regfile writes -system.cpu.misc_regfile_reads 202344104 # number of misc regfile reads +system.cpu.cpi 0.833386 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.833386 # CPI: Total CPI of All Threads +system.cpu.ipc 1.199924 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.199924 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502917784 # number of integer regfile reads +system.cpu.int_regfile_writes 247848787 # number of integer regfile writes +system.cpu.fp_regfile_reads 4075 # number of floating regfile reads +system.cpu.fp_regfile_writes 819 # number of floating regfile writes +system.cpu.cc_regfile_reads 109098841 # number of cc regfile reads +system.cpu.cc_regfile_writes 65494445 # number of cc regfile writes +system.cpu.misc_regfile_reads 201957201 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073334 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.317880 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71743454 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077430 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.534715 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21320595500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.317880 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992998 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992998 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073306 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.354566 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71520008 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077402 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.427621 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21024099500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.354566 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993006 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993006 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3441 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3447 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 151138894 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 151138894 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40397499 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40397499 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345955 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71743454 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71743454 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71743454 # number of overall hits -system.cpu.dcache.overall_hits::total 71743454 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693481 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693481 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93797 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93797 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2787278 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2787278 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2787278 # number of overall misses -system.cpu.dcache.overall_misses::total 2787278 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32417345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32417345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3182155993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3182155993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35599500993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35599500993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35599500993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35599500993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43090980 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150691296 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150691296 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40173982 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40173982 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31346026 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31346026 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71520008 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71520008 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71520008 # number of overall hits +system.cpu.dcache.overall_hits::total 71520008 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93726 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93726 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2786939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2786939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2786939 # number of overall misses +system.cpu.dcache.overall_misses::total 2786939 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32416728500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32416728500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3181034987 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3181034987 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35597763487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35597763487 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35597763487 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35597763487 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42867195 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42867195 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74530732 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74530732 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74530732 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74530732 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062507 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062507 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002983 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002983 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037398 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037398 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037398 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037398 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12035.483079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12035.483079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33925.989029 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33925.989029 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12772.138622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12772.138622 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 219409 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74306947 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74306947 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74306947 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74306947 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062827 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062827 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037506 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037506 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037506 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037506 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12036.451814 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12036.451814 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33939.728432 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33939.728432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12773.068764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12773.068764 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 220832 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 385 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43429 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43178 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.052131 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.114456 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 96.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066585 # number of writebacks -system.cpu.dcache.writebacks::total 2066585 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697929 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 697929 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11919 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11919 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 709848 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 709848 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 709848 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 709848 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995552 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995552 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81878 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81878 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077430 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077430 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077430 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077430 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24266554500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24266554500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3024734993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3024734993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27291289493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27291289493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27291289493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27291289493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046310 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046310 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027873 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027873 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12160.321806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12160.321806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36941.974560 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36941.974560 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 871.416193 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29904477 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26772.136974 # Average number of references to valid blocks. +system.cpu.dcache.writebacks::writebacks 2066926 # number of writebacks +system.cpu.dcache.writebacks::total 2066926 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697625 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 697625 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11912 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11912 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 709537 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 709537 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 709537 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 709537 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995588 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995588 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81814 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81814 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077402 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077402 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077402 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077402 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24271228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24271228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3023849487 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3023849487 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27295077987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27295077987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27295077987 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27295077987 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046553 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046553 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027957 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027957 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.444603 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.444603 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36960.049466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36960.049466 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 93 # number of replacements +system.cpu.icache.tags.tagsinuse 878.108473 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29762089 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26549.588760 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 871.416193 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.425496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.425496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1023 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 878.108473 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.428764 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.428764 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1028 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 905 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.499512 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59813021 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59813021 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29904477 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29904477 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29904477 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29904477 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29904477 # number of overall hits -system.cpu.icache.overall_hits::total 29904477 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1475 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1475 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1475 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1475 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1475 # number of overall misses -system.cpu.icache.overall_misses::total 1475 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 154630499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 154630499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 154630499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 154630499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 154630499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 154630499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29905952 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29905952 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29905952 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29905952 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29905952 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29905952 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 104834.236610 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 104834.236610 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 104834.236610 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 104834.236610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 104834.236610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 104834.236610 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3285 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 910 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59528269 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59528269 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 29762089 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29762089 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29762089 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29762089 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29762089 # number of overall hits +system.cpu.icache.overall_hits::total 29762089 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1485 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1485 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1485 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1485 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1485 # number of overall misses +system.cpu.icache.overall_misses::total 1485 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 149774999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 149774999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 149774999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 149774999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 149774999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 149774999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29763574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29763574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29763574 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29763574 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29763574 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29763574 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100858.585185 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100858.585185 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100858.585185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100858.585185 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2965 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 219 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 211.785714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 94 # number of writebacks -system.cpu.icache.writebacks::total 94 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 358 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 358 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 358 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 358 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 358 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1117 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1117 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1117 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1117 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1117 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1117 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 115157499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 115157499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 115157499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 115157499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 115157499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 115157499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 103095.343778 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 103095.343778 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 103095.343778 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 103095.343778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 103095.343778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 103095.343778 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 93 # number of writebacks +system.cpu.icache.writebacks::total 93 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 364 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 364 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 364 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 364 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 364 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1121 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1121 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1121 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1121 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1121 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1121 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 114880499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 114880499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 114880499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 114880499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 114880499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 114880499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000038 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000038 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000038 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102480.373773 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102480.373773 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102480.373773 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 102480.373773 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102480.373773 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 102480.373773 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 694 # number of replacements -system.cpu.l2cache.tags.tagsinuse 21600.967235 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4121275 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 21678.088627 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4121221 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30681 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 134.326619 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 134.324859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.261837 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.389241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20887.316157 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000100 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.637430 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.659209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2.638364 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 712.370564 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20963.079700 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000081 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021740 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.639742 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.661563 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29987 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29627 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29624 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915131 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33246329 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33246329 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2066585 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2066585 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 94 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 94 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 52930 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 52930 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 33245897 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33245897 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066926 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2066926 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 52858 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 52858 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1994925 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1994925 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1994973 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1994973 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2047855 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2047883 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2047831 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2047859 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2047855 # number of overall hits -system.cpu.l2cache.overall_hits::total 2047883 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 28997 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28997 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1089 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1089 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 578 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 578 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1089 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29575 # number of demand (read+write) misses +system.cpu.l2cache.overall_hits::cpu.data 2047831 # number of overall hits +system.cpu.l2cache.overall_hits::total 2047859 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 28990 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28990 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1093 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1093 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 581 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 581 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1093 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29571 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 30664 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1089 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29575 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 1093 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29571 # number of overall misses system.cpu.l2cache.overall_misses::total 30664 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2345855500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2345855500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 113174000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 113174000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 87677000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 87677000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 113174000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2433532500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2546706500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 113174000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2433532500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2546706500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066585 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2066585 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 94 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 94 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 81927 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 81927 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1117 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1117 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995503 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1995503 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1117 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2077430 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2078547 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1117 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2077430 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2078547 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353937 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.353937 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974933 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974933 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.974933 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014236 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2345791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2345791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 112890000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 112890000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 92689500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 92689500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 112890000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2438480500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2551370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 112890000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2438480500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2551370500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066926 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2066926 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81848 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81848 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1121 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1121 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995554 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1995554 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1121 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2077402 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2078523 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1121 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2077402 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078523 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.354193 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.354193 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.975022 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.975022 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.975022 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014235 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.014753 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.974933 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014236 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.975022 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014235 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014753 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80899.937925 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80899.937925 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103924.701561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103924.701561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 151690.311419 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 151690.311419 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103924.701561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82283.431953 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83051.999087 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103924.701561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82283.431953 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83051.999087 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80917.247327 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80917.247327 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103284.537969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103284.537969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 159534.423408 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 159534.423408 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103284.537969 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82461.888337 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83204.099270 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103284.537969 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82461.888337 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83204.099270 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 305 # number of writebacks -system.cpu.l2cache.writebacks::total 305 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28997 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28997 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1089 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1089 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 578 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 578 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1089 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks +system.cpu.l2cache.writebacks::total 309 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28990 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28990 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1093 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1093 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 581 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 581 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 30664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1089 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1093 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30664 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055885500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055885500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 102284000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 102284000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 81897000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 81897000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102284000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2137782500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2240066500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102284000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2137782500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2240066500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353937 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353937 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974933 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000290 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000290 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 101960000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 101960000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 86879500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 86879500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2142770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2244730500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2142770500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2244730500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354193 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354193 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.975022 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000291 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000291 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70899.937925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70899.937925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93924.701561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93924.701561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 141690.311419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 141690.311419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4151975 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073430 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70917.247327 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70917.247327 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93284.537969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93284.537969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 149534.423408 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 149534.423408 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4151922 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073402 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 335 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 335 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2066890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 94 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 7138 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6230522 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265216960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265294464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995554 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2335 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228110 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6230445 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265236992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265314688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 694 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19520 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079241 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000169 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.013010 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 19776 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2079217 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013121 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2078889 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 352 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2078859 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 358 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079241 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4142666500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079217 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4142980000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1681500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116145000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3116103000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 31027 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 363 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 31023 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 359 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1667 # Transaction distribution -system.membus.trans_dist::WritebackDirty 305 # Transaction distribution -system.membus.trans_dist::CleanEvict 58 # Transaction distribution -system.membus.trans_dist::ReadExReq 28997 # Transaction distribution -system.membus.trans_dist::ReadExResp 28997 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1667 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1982016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1674 # Transaction distribution +system.membus.trans_dist::WritebackDirty 309 # Transaction distribution +system.membus.trans_dist::CleanEvict 50 # Transaction distribution +system.membus.trans_dist::ReadExReq 28990 # Transaction distribution +system.membus.trans_dist::ReadExResp 28990 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1674 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1982272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 30664 # Request fanout histogram @@ -1049,9 +1049,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30664 # Request fanout histogram -system.membus.reqLayer0.occupancy 43847500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 43676000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161573250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161581250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |