regressions: stats update due to decoder changes

2 files changed, 135 insertions, 153 deletions

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 31bcf2795..f5f3830e6 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -78,7 +78,6 @@ iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
 interrupts=system.cpu.interrupts
-isa=system.cpu.isa
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -458,23 +457,6 @@ mem_side=system.cpu.toL2Bus.slave[0]
 [system.cpu.interrupts]
 type=ArmInterrupts
 
-[system.cpu.isa]
-type=ArmISA
-fpsid=1090793632
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=3
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=4027589137
-id_pfr0=49
-id_pfr1=1
-midr=890224640
-
 [system.cpu.itb]
 type=ArmTLB
 children=walker
@@ -536,9 +518,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index c26c8db9e..fae2b58b3 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.026786                       # Nu
 sim_ticks                                 26786364500                       # Number of ticks simulated
 final_tick                                26786364500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 151377                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152464                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               44755705                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 363280                       # Number of bytes of host memory used
-host_seconds                                   598.50                       # Real time elapsed on the host
+host_inst_rate                                 184396                       # Simulator instruction rate (inst/s)
+host_op_rate                                   185720                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54518089                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410024                       # Number of bytes of host memory used
+host_seconds                                   491.33                       # Real time elapsed on the host
 sim_insts                                    90599358                       # Number of instructions simulated
 sim_ops                                      91249911                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             45248                       # Number of bytes read from this memory
@@ -496,7 +496,7 @@ system.cpu.int_regfile_reads                495578845                       # nu
 system.cpu.int_regfile_writes               120555497                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       176                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                      427                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               181219036                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                29099412                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  11608                       # number of misc regfile writes
 system.cpu.icache.replacements                      4                       # number of replacements
 system.cpu.icache.tagsinuse                632.599736                       # Cycle average of tags in use
@@ -582,6 +582,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 943495                       # number of replacements
+system.cpu.dcache.tagsinuse               3673.924289                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 28145440                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 947591                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  29.702097                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             7941416000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3673.924289                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.896954                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.896954                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     23596473                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23596473                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4537302                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4537302                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5856                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5856                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         5799                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5799                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      28133775                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28133775                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28133775                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28133775                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1173127                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1173127                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       197679                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       197679                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            6                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            6                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1370806                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1370806                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1370806                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1370806                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13880183500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13880183500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5370097404                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5370097404                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       191000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       191000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  19250280904                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  19250280904                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  19250280904                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  19250280904                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24769600                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24769600                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5862                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5862                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         5799                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5799                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     29504581                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     29504581                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     29504581                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     29504581                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047362                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.047362                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.041749                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.041749                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001024                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001024                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.046461                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.046461                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.046461                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.046461                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14043.038113                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14043.038113                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       152379                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             23821                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.396835                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       942892                       # number of writebacks
+system.cpu.dcache.writebacks::total            942892                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       269039                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       269039                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       154172                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       154172                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            6                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            6                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       423211                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       423211                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       423211                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       423211                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       904088                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       904088                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43507                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        43507                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       947595                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       947595                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       947595                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       947595                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9989577500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9989577500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    957542952                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    957542952                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10947120452                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10947120452                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10947120452                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10947120452                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036500                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036500                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009188                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009188                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032117                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.032117                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032117                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032117                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse             10757.788342                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 1831577                       # Total number of references to valid blocks.
@@ -743,131 +869,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 943495                       # number of replacements
-system.cpu.dcache.tagsinuse               3673.924289                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 28145440                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 947591                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  29.702097                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             7941416000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3673.924289                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.896954                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.896954                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     23596473                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23596473                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4537302                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4537302                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         5856                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         5856                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         5799                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         5799                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      28133775                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28133775                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28133775                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28133775                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1173127                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1173127                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       197679                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       197679                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            6                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            6                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1370806                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1370806                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1370806                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1370806                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13880183500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13880183500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   5370097404                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   5370097404                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       191000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       191000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  19250280904                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  19250280904                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  19250280904                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  19250280904                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24769600                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24769600                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5862                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         5862                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         5799                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         5799                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     29504581                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     29504581                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     29504581                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     29504581                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047362                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.047362                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.041749                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.041749                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001024                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001024                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.046461                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.046461                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.046461                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.046461                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14043.038113                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14043.038113                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       152379                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             23821                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.396835                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       942892                       # number of writebacks
-system.cpu.dcache.writebacks::total            942892                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       269039                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       269039                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       154172                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       154172                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            6                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            6                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       423211                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       423211                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       423211                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       423211                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       904088                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       904088                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43507                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        43507                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       947595                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       947595                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       947595                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       947595                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9989577500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9989577500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    957542952                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    957542952                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10947120452                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10947120452                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10947120452                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10947120452                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036500                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036500                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009188                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009188                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032117                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.032117                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032117                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032117                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------