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authorCurtis Dunham <Curtis.Dunham@arm.com>2016-08-02 11:34:32 +0100
committerCurtis Dunham <Curtis.Dunham@arm.com>2016-08-02 11:34:32 +0100
commitae445c034880aea5700e7a9a1a69e5920413bb37 (patch)
tree22d047da31ccb1430831f2c51fcdb118dd12925f /tests/long/se/10.mcf
parent8b3434a4f2090961dc5b3da7bc48b8b636b9f1e3 (diff)
downloadgem5-ae445c034880aea5700e7a9a1a69e5920413bb37.tar.xz
stats: update references
Diffstat (limited to 'tests/long/se/10.mcf')
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini2
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt12
3 files changed, 10 insertions, 10 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 763fea8df..9dfbe1ac3 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -594,7 +594,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 67b5f0b3c..e215a7e6c 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:07:19
-gem5 executing on e108600-lin, pid 24393
+gem5 compiled Aug 1 2016 17:10:05
+gem5 started Aug 1 2016 17:10:34
+gem5 executing on e108600-lin, pid 12217
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 5f4859c30..0313fa682 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.058199 # Nu
sim_ticks 58199030500 # Number of ticks simulated
final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123305 # Simulator instruction rate (inst/s)
-host_op_rate 123919 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 79216719 # Simulator tick rate (ticks/s)
-host_mem_usage 487100 # Number of bytes of host memory used
-host_seconds 734.68 # Real time elapsed on the host
+host_inst_rate 122100 # Simulator instruction rate (inst/s)
+host_op_rate 122709 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 78442850 # Simulator tick rate (ticks/s)
+host_mem_usage 487108 # Number of bytes of host memory used
+host_seconds 741.93 # Real time elapsed on the host
sim_insts 90589799 # Number of instructions simulated
sim_ops 91041030 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -698,7 +698,7 @@ system.cpu.fp_regfile_reads 59 # nu
system.cpu.fp_regfile_writes 96 # number of floating regfile writes
system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads
system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes
-system.cpu.misc_regfile_reads 28410103 # number of misc regfile reads
+system.cpu.misc_regfile_reads 28410105 # number of misc regfile reads
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 5470634 # number of replacements