diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-29 03:27:15 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-29 03:27:15 -0800 |
| commit | 39f314cc151b0a05ee0e654d52bad1c906fac668 (patch) | |
| tree | 61feb0d0fa2fa1e1f48c698c6a242a0b21013120 /tests/long/se/10.mcf | |
| parent | dc0e629ea1f074691d307cde3ab7dd51a5e2102f (diff) | |
| parent | ce336fae6a2c89310038d6fdd80902b771cf7ffa (diff) | |
| download | gem5-39f314cc151b0a05ee0e654d52bad1c906fac668.tar.xz | |
Yet another merge with the main repository.
--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
Diffstat (limited to 'tests/long/se/10.mcf')
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini | 5 | ||||
| -rwxr-xr-x | tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 696 |
3 files changed, 357 insertions, 354 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index cfda7ba22..c0a21768c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -80,6 +80,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=true numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -502,9 +503,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 426afea0c..7ce56ed7f 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:45:46 -gem5 executing on zizzer +gem5 compiled Jan 28 2012 12:11:40 +gem5 started Jan 28 2012 12:12:43 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 70312944500 because target called exit() +Exiting @ tick 70097938500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index f9c970889..741105f40 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070313 # Number of seconds simulated -sim_ticks 70312944500 # Number of ticks simulated -final_tick 70312944500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.070098 # Number of seconds simulated +sim_ticks 70097938500 # Number of ticks simulated +final_tick 70097938500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168126 # Simulator instruction rate (inst/s) -host_tick_rate 42493747 # Simulator tick rate (ticks/s) -host_mem_usage 349904 # Number of bytes of host memory used -host_seconds 1654.67 # Real time elapsed on the host +host_inst_rate 110386 # Simulator instruction rate (inst/s) +host_tick_rate 27814669 # Simulator tick rate (ticks/s) +host_mem_usage 379416 # Number of bytes of host memory used +host_seconds 2520.18 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated -system.physmem.bytes_read 4896576 # Number of bytes read from this memory -system.physmem.bytes_inst_read 65344 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1867840 # Number of bytes written to this memory -system.physmem.num_reads 76509 # Number of read requests responded to by this memory -system.physmem.num_writes 29185 # Number of write requests responded to by this memory +system.physmem.bytes_read 3896128 # Number of bytes read from this memory +system.physmem.bytes_inst_read 65152 # Number of instructions bytes read from this memory +system.physmem.bytes_written 892416 # Number of bytes written to this memory +system.physmem.num_reads 60877 # Number of read requests responded to by this memory +system.physmem.num_writes 13944 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 69639752 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 929331 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26564668 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 96204419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 55581207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 929442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 12730988 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 68312194 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 140625890 # number of cpu cycles simulated +system.cpu.numCycles 140195878 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37833804 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 37833804 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1322933 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 33591925 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 33081589 # Number of BTB hits +system.cpu.BPredUnit.lookups 37928407 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 37928407 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1334678 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 33548417 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 33040245 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29087381 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 203627812 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37833804 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33081589 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 63297987 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10276298 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38195582 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 95 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28266291 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 204981 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139497150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.574262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.291399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29060209 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 203598338 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37928407 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33040245 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 63274026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10249926 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38189577 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 77 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28245503 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 214193 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139407654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.577879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.292775 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78673130 56.40% 56.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3606277 2.59% 58.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2810090 2.01% 61.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4532102 3.25% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6824412 4.89% 69.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5279008 3.78% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7637539 5.48% 78.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4315201 3.09% 81.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25819391 18.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78584615 56.37% 56.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3556242 2.55% 58.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2802198 2.01% 60.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4529245 3.25% 64.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6913485 4.96% 69.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5169478 3.71% 72.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7697084 5.52% 78.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4298531 3.08% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25856776 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139497150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.269039 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.448011 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 41917744 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 28560060 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 52643719 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7459543 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8916084 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 354657218 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8916084 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48823983 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4469241 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6888 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 53004642 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24276312 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350176569 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 101342 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20289844 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 314446851 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 861231533 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 861227904 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3629 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139407654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.270539 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.452242 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 41988791 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 28417024 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 52030953 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8087139 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8883747 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 355040007 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8883747 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48483810 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4810408 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9079 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 52929871 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24290739 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350051728 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 103496 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20366187 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 314282471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 860902327 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 860897388 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4939 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66102659 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 479 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 65938279 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 478 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 56104077 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112666461 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37647255 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 48253520 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8188094 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343455788 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 316242386 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89834 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65098177 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 92870721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1849 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139497150 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.267017 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.750973 # Number of insts issued each cycle +system.cpu.rename.skidInsts 57634584 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112617334 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37601195 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 47838969 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8379867 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343415839 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2328 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 316096096 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78808 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65029362 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 92942153 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1882 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139407654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.267423 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.745481 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 31795649 22.79% 22.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18418675 13.20% 36.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25717845 18.44% 54.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 29872112 21.41% 75.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18507796 13.27% 89.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 10200782 7.31% 96.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3199934 2.29% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1737869 1.25% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 46488 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32098361 23.02% 23.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17868067 12.82% 35.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24417482 17.52% 53.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 32093883 23.02% 76.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18421218 13.21% 89.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9527374 6.83% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3128162 2.24% 98.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1804154 1.29% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 48953 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139497150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139407654 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 25785 1.36% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1795857 94.47% 95.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79349 4.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 25731 1.31% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1863505 95.00% 96.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 72393 3.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 180262574 57.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 180196286 57.01% 57.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 195 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 342 0.00% 57.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued @@ -178,85 +178,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101451147 32.08% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34511759 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101438567 32.09% 89.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34444190 10.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 316242386 # Type of FU issued -system.cpu.iq.rate 2.248821 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1900991 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006011 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 773971833 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 408587092 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 312537049 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 914 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2332 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 382 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 318126211 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 455 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 45906656 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 316096096 # Type of FU issued +system.cpu.iq.rate 2.254675 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1961629 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006206 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 773638738 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 408477370 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 312370165 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1545 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3169 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 656 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 318040246 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 768 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52318776 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21887073 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 122159 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33758 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6207504 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21837946 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 139826 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33737 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6161444 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2763 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15488 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3258 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3821 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8916084 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 901068 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88602 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343458083 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 26305 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112666461 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37647255 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 8883747 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 984872 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88741 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343418167 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 39651 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112617334 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37601195 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1597 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 48733 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33758 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1219939 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230098 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1450037 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 314144155 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100864248 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2098231 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 1341 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 42673 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33737 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1237180 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 215729 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1452909 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 313907375 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100815222 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2188721 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134973322 # number of memory reference insts executed -system.cpu.iew.exec_branches 31810521 # Number of branches executed -system.cpu.iew.exec_stores 34109074 # Number of stores executed -system.cpu.iew.exec_rate 2.233900 # Inst execution rate -system.cpu.iew.wb_sent 313190495 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 312537431 # cumulative count of insts written-back -system.cpu.iew.wb_producers 232392592 # num instructions producing a value -system.cpu.iew.wb_consumers 318468890 # num instructions consuming a value +system.cpu.iew.exec_refs 134855811 # number of memory reference insts executed +system.cpu.iew.exec_branches 31730666 # Number of branches executed +system.cpu.iew.exec_stores 34040589 # Number of stores executed +system.cpu.iew.exec_rate 2.239063 # Inst execution rate +system.cpu.iew.wb_sent 313087219 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 312370821 # cumulative count of insts written-back +system.cpu.iew.wb_producers 231825034 # num instructions producing a value +system.cpu.iew.wb_consumers 317282535 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.222474 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.729718 # average fanout of values written-back +system.cpu.iew.wb_rate 2.228103 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.730658 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 65270328 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 65229233 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1322946 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130581066 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.130420 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.663472 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1334689 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130523907 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.131353 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.650695 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50414718 38.61% 38.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24339651 18.64% 57.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 16499074 12.64% 69.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12376450 9.48% 79.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3696747 2.83% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3466084 2.65% 84.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2761727 2.11% 86.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1175320 0.90% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15851295 12.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 49374885 37.83% 37.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24990571 19.15% 56.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17165469 13.15% 70.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12454302 9.54% 79.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3472302 2.66% 82.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3453203 2.65% 84.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2713996 2.08% 87.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1124527 0.86% 87.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15774652 12.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130581066 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 130523907 # Number of insts commited each cycle system.cpu.commit.count 278192519 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed @@ -266,49 +266,49 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15851295 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15774652 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 458192618 # The number of ROB reads -system.cpu.rob.rob_writes 695856607 # The number of ROB writes -system.cpu.timesIdled 33615 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1128740 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 458171007 # The number of ROB reads +system.cpu.rob.rob_writes 695745355 # The number of ROB writes +system.cpu.timesIdled 23904 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 788224 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.505498 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.505498 # CPI: Total CPI of All Threads -system.cpu.ipc 1.978245 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.978245 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554794614 # number of integer regfile reads -system.cpu.int_regfile_writes 279836675 # number of integer regfile writes -system.cpu.fp_regfile_reads 437 # number of floating regfile reads -system.cpu.fp_regfile_writes 335 # number of floating regfile writes -system.cpu.misc_regfile_reads 201195947 # number of misc regfile reads -system.cpu.icache.replacements 68 # number of replacements -system.cpu.icache.tagsinuse 824.679926 # Cycle average of tags in use -system.cpu.icache.total_refs 28264985 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1027 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 27521.893866 # Average number of references to valid blocks. +system.cpu.cpi 0.503953 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.503953 # CPI: Total CPI of All Threads +system.cpu.ipc 1.984313 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.984313 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554439426 # number of integer regfile reads +system.cpu.int_regfile_writes 279882097 # number of integer regfile writes +system.cpu.fp_regfile_reads 791 # number of floating regfile reads +system.cpu.fp_regfile_writes 562 # number of floating regfile writes +system.cpu.misc_regfile_reads 200975844 # number of misc regfile reads +system.cpu.icache.replacements 62 # number of replacements +system.cpu.icache.tagsinuse 823.089414 # Cycle average of tags in use +system.cpu.icache.total_refs 28244206 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1023 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 27609.194526 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 824.679926 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.402676 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28264985 # number of ReadReq hits -system.cpu.icache.demand_hits 28264985 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28264985 # number of overall hits -system.cpu.icache.ReadReq_misses 1306 # number of ReadReq misses -system.cpu.icache.demand_misses 1306 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1306 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 47073500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 47073500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 47073500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28266291 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28266291 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28266291 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 823.089414 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.401899 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28244206 # number of ReadReq hits +system.cpu.icache.demand_hits 28244206 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28244206 # number of overall hits +system.cpu.icache.ReadReq_misses 1297 # number of ReadReq misses +system.cpu.icache.demand_misses 1297 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1297 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 46884000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 46884000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 46884000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28245503 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28245503 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28245503 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36044.027565 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36044.027565 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36044.027565 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36148.033924 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36148.033924 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36148.033924 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -318,166 +318,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 278 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 278 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 278 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1028 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1028 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1028 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 273 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 273 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 273 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1024 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1024 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 36154500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 36154500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 36154500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 36044000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 36044000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 36044000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35169.747082 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35169.747082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35169.747082 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35199.218750 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35199.218750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35199.218750 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2073066 # number of replacements -system.cpu.dcache.tagsinuse 4076.005888 # Cycle average of tags in use -system.cpu.dcache.total_refs 83808707 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2077162 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40.347699 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 23845092000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.005888 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995119 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52611944 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31196754 # number of WriteReq hits -system.cpu.dcache.demand_hits 83808698 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 83808698 # number of overall hits -system.cpu.dcache.ReadReq_misses 2262875 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 242997 # number of WriteReq misses -system.cpu.dcache.demand_misses 2505872 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2505872 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14629803500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4394648436 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19024451936 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19024451936 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 54874819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072801 # number of replacements +system.cpu.dcache.tagsinuse 4073.016957 # Cycle average of tags in use +system.cpu.dcache.total_refs 77487718 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076897 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.309370 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 23652058000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4073.016957 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994389 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 46133976 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 31353733 # number of WriteReq hits +system.cpu.dcache.demand_hits 77487709 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 77487709 # number of overall hits +system.cpu.dcache.ReadReq_misses 2288597 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 86018 # number of WriteReq misses +system.cpu.dcache.demand_misses 2374615 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2374615 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 13760644500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1501321288 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 15261965788 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 15261965788 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 48422573 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 86314570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 86314570 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.041237 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.007729 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.029032 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.029032 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6465.139922 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 18085.196262 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 7591.948805 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 7591.948805 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 289000 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 79862324 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 79862324 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.047263 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.002736 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.029734 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.029734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 6012.698828 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17453.571206 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 6427.132730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 6427.132730 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3141.304348 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1447147 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 291175 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 137531 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 428706 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 428706 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1971700 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 105466 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2077166 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2077166 # number of overall MSHR misses +system.cpu.dcache.writebacks 1880524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 293812 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3902 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 297714 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 297714 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1994785 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 82116 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2076901 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2076901 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5609142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1870309936 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7479451936 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7479451936 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5560782500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1157739288 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6718521788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6718521788 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035931 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.024065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.024065 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2844.825278 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17733.771414 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3600.796439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3600.796439 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.041195 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002612 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.026006 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.026006 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2787.660074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14098.827123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3234.878209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3234.878209 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 49057 # number of replacements -system.cpu.l2cache.tagsinuse 18859.305089 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3318010 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 77063 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 43.055811 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 33248 # number of replacements +system.cpu.l2cache.tagsinuse 18948.902283 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3764067 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 61254 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 61.450142 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6747.919367 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12111.385721 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.205930 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.369610 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1938157 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1447147 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63526 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2001683 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2001683 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34474 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 6031.150094 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12917.752189 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.184056 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.394219 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1964318 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1880524 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 52728 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2017046 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2017046 # number of overall hits +system.cpu.l2cache.ReadReq_misses 31362 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 42035 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76509 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76509 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1179443000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1438838000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 2618281000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 2618281000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1972631 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1447147 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses 29515 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 60877 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 60877 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1071112000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1006258500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 2077370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 2077370500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1995680 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1880524 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 105561 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2078192 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2078192 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.017476 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses 82243 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2077923 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2077923 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.015715 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.398206 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.036815 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.036815 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34212.536984 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.523017 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34221.869323 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34221.869323 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 0.358876 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.029297 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.029297 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34153.179006 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34093.122141 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34124.061632 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34124.061632 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2678.571429 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29185 # number of writebacks +system.cpu.l2cache.writebacks 13944 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34474 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 31362 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42035 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76509 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76509 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 29515 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 60877 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 60877 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1069429500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 972890000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307209000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2376638500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2376638500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 914988000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1887878000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1887878000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.015715 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398206 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.036815 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.036815 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.334919 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.358876 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.029297 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.029297 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.299662 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.108719 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.515403 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.515403 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.779265 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.350756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.350756 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |