diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/se/10.mcf | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/se/10.mcf')
4 files changed, 916 insertions, 754 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index e070ad588..ab0c1f304 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 6e907f4cc..a6e3b7d23 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026913 # Number of seconds simulated -sim_ticks 26912680500 # Number of ticks simulated -final_tick 26912680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026911 # Number of seconds simulated +sim_ticks 26911413000 # Number of ticks simulated +final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145850 # Simulator instruction rate (inst/s) -host_op_rate 146897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43329539 # Simulator tick rate (ticks/s) -host_mem_usage 407732 # Number of bytes of host memory used -host_seconds 621.12 # Real time elapsed on the host +host_inst_rate 116759 # Simulator instruction rate (inst/s) +host_op_rate 117598 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34685583 # Simulator tick rate (ticks/s) +host_mem_usage 427272 # Number of bytes of host memory used +host_seconds 775.87 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 992896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1681289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35211951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36893241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1681289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1681289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1681289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35211951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36893241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15514 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory +system.physmem.bytes_read::total 993152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15518 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1688503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35215988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36904491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1688503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1688503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1688503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35215988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36904491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15518 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15518 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 993152 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side +system.physmem.bytesReadSys 993152 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 988 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 987 # Per bank write bursts system.physmem.perBankRdBursts::1 886 # Per bank write bursts -system.physmem.perBankRdBursts::2 943 # Per bank write bursts +system.physmem.perBankRdBursts::2 942 # Per bank write bursts system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1080 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 956 # Per bank write bursts +system.physmem.perBankRdBursts::9 959 # Per bank write bursts system.physmem.perBankRdBursts::10 938 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts @@ -73,14 +73,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26912480500 # Total gap between requests +system.physmem.totGap 26911220500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15514 # Read request sizes (log2) +system.physmem.readPktSize::6 15518 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -88,9 +88,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -152,125 +152,126 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1603.423015 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 482.832317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2202.245443 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 156 25.28% 25.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 69 11.18% 36.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 40 6.48% 42.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 21 3.40% 46.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 12 1.94% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 0.97% 49.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 26 4.21% 53.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 13 2.11% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.81% 56.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 9 1.46% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.65% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.65% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.81% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.30% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.49% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.49% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.49% 64.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 19 3.08% 69.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.49% 71.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.49% 72.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.49% 75.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.49% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.49% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.49% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.49% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.16% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.49% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.32% 83.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 3 0.49% 84.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.49% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.81% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.49% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 7 1.13% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.32% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.49% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.49% 94.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.49% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.32% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1598.759289 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 481.680955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2200.761860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 153 24.72% 24.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 75 12.12% 36.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 40 6.46% 43.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 20 3.23% 46.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 12 1.94% 48.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 0.97% 49.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 27 4.36% 53.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 12 1.94% 55.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.81% 56.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 10 1.62% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.48% 58.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.65% 59.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.81% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.29% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.48% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 19 3.07% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.48% 71.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.81% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 6 0.97% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 617 # Bytes accessed per row activation -system.physmem.totQLat 103133500 # Total ticks spent queuing -system.physmem.totMemAccLat 356414750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers -system.physmem.totBankLat 175711250 # Total ticks spent accessing banks -system.physmem.avgQLat 6647.77 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11325.98 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 619 # Bytes accessed per row activation +system.physmem.totQLat 103760250 # Total ticks spent queuing +system.physmem.totMemAccLat 357130250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77590000 # Total ticks spent in databus transfers +system.physmem.totBankLat 175780000 # Total ticks spent accessing banks +system.physmem.avgQLat 6686.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11327.49 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22973.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23013.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage @@ -278,37 +279,39 @@ system.physmem.busUtilRead 0.29 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14897 # Number of row buffer hits during reads +system.physmem.readRowHits 14899 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 96.01 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734722.22 # Average gap between requests -system.physmem.pageHitRate 96.02 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.95 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 36893241 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 976 # Transaction distribution -system.membus.trans_dist::ReadResp 976 # Transaction distribution +system.physmem.avgGap 1734193.87 # Average gap between requests +system.physmem.pageHitRate 96.01 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36904491 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 980 # Transaction distribution +system.membus.trans_dist::ReadResp 980 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31028 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992896 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31038 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 993152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 993152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19247000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19253000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145153250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.branchPred.lookups 26684421 # Number of BP lookups -system.cpu.branchPred.condPredicted 22003515 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11361703 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11279248 # Number of BTB hits +system.cpu.branchPred.lookups 26686306 # Number of BP lookups +system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11366672 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11283030 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.274273 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70578 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 175 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.264147 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70474 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 170 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -352,99 +355,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53825362 # number of cpu cycles simulated +system.cpu.numCycles 53822827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14170521 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127888749 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26684421 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11349826 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24033756 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4765472 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11324127 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 14174375 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127897951 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26686306 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11353504 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24037647 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4766390 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11312706 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 108 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13841798 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 328713 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53434811 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214791 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13845393 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329438 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53431463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410222 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29439353 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3386965 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028576 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1554110 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668608 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2917595 5.46% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1511603 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1091436 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9836565 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29432152 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389873 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028658 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1553769 2.91% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1668148 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2920061 5.47% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1509677 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090745 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9838380 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53434811 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495759 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.375994 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16934142 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9169646 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22402191 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031199 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3897633 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442994 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8719 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126071688 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42592 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3897633 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18714767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3594336 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 187938 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21550636 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5489501 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123153089 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 427273 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4600360 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1278 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143605134 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536434214 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 500014017 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 784 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53431463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495818 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.376277 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16937925 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9159010 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22405754 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1030805 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3897969 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444268 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8691 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126081524 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42632 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3897969 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18719458 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3589629 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186437 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21552986 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5484984 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123156725 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 425837 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4596994 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1284 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143603336 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536446832 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 500029218 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 672 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36190948 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4612 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4610 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12546346 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29477793 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5522687 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2151443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1269536 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118168344 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8478 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105154526 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78994 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26741749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65618769 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 260 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53434811 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908534 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36189150 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4635 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4633 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12540789 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29477429 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5520545 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2151265 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1294097 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118170448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8500 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105167442 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79307 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26742090 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65583646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53431463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968268 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908949 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15376938 28.78% 28.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11654897 21.81% 50.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8243564 15.43% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6824643 12.77% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4966766 9.30% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2946722 5.51% 93.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2453138 4.59% 98.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 526074 0.98% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442069 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15374280 28.77% 28.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11649569 21.80% 50.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8250468 15.44% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6827782 12.78% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4953380 9.27% 88.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2948609 5.52% 93.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2456731 4.60% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 528512 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442132 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53434811 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53431463 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45800 6.91% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45750 6.92% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available @@ -473,13 +476,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340417 51.39% 58.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276226 41.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340320 51.44% 58.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275443 41.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74421271 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74429619 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10979 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -501,90 +504,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 129 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 165 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25608548 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5113387 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25613153 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5113394 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105154526 # Type of FU issued -system.cpu.iq.rate 1.953624 # Inst issue rate -system.cpu.iq.fu_busy_cnt 662470 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264484578 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144923147 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102682900 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 749 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 323 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105816623 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 441366 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105167442 # Type of FU issued +system.cpu.iq.rate 1.953956 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661540 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264506537 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144925816 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102691564 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 657 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 923 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105828655 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441760 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6903827 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6492 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6312 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 777843 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6903463 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6716 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6442 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 775701 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31495 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31606 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3897633 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 959563 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126871 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118189516 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310121 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29477793 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5522687 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65719 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6709 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6312 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446751 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446217 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892968 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104180481 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25289750 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 974045 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3897969 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 957023 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126637 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118191644 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 310003 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29477429 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5520545 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4612 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6738 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6442 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447212 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446019 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 893231 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104191675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25292948 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 975767 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12694 # number of nop insts executed -system.cpu.iew.exec_refs 30346354 # number of memory reference insts executed -system.cpu.iew.exec_branches 21325110 # Number of branches executed -system.cpu.iew.exec_stores 5056604 # Number of stores executed -system.cpu.iew.exec_rate 1.935528 # Inst execution rate -system.cpu.iew.wb_sent 102961531 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102683223 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62241416 # num instructions producing a value -system.cpu.iew.wb_consumers 104299638 # num instructions consuming a value +system.cpu.iew.exec_nop 12696 # number of nop insts executed +system.cpu.iew.exec_refs 30349771 # number of memory reference insts executed +system.cpu.iew.exec_branches 21326762 # Number of branches executed +system.cpu.iew.exec_stores 5056823 # Number of stores executed +system.cpu.iew.exec_rate 1.935827 # Inst execution rate +system.cpu.iew.wb_sent 102970942 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102691851 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62249009 # num instructions producing a value +system.cpu.iew.wb_consumers 104309545 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907711 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596756 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907961 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26939491 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26941617 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834010 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49537178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842111 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540648 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834570 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49533494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842248 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540561 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20048697 40.47% 40.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13146284 26.54% 67.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4166513 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3429547 6.92% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533299 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 729419 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954733 1.93% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253168 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275518 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20042935 40.46% 40.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13146551 26.54% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4167484 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431298 6.93% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1535317 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 726626 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 954928 1.93% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253259 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275096 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49537178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49533494 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -595,218 +598,222 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275518 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275096 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162448377 # The number of ROB reads -system.cpu.rob.rob_writes 240302265 # The number of ROB writes -system.cpu.timesIdled 46020 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 390551 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162447241 # The number of ROB reads +system.cpu.rob.rob_writes 240306728 # The number of ROB writes +system.cpu.timesIdled 46009 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 391364 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.594166 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594166 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683032 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683032 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495553334 # number of integer regfile reads -system.cpu.int_regfile_writes 120547287 # number of integer regfile writes -system.cpu.fp_regfile_reads 170 # number of floating regfile reads -system.cpu.fp_regfile_writes 410 # number of floating regfile writes -system.cpu.misc_regfile_reads 29088502 # number of misc regfile reads +system.cpu.cpi 0.594138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594138 # CPI: Total CPI of All Threads +system.cpu.ipc 1.683111 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.683111 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495604527 # number of integer regfile reads +system.cpu.int_regfile_writes 120552200 # number of integer regfile writes +system.cpu.fp_regfile_reads 148 # number of floating regfile reads +system.cpu.fp_regfile_writes 360 # number of floating regfile writes +system.cpu.misc_regfile_reads 29090078 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4497529557 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43698 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838143 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888541000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4497665284 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942892 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43700 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1472 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120991360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121038400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121038400 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888506500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1222499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424134990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424110491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 633.195127 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13840808 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 732 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18908.207650 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 632.612747 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13844401 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 735 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18835.919728 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 633.195127 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.309177 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.309177 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13840808 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13840808 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13840808 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13840808 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13840808 # number of overall hits -system.cpu.icache.overall_hits::total 13840808 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 989 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 989 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 989 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 989 # number of overall misses -system.cpu.icache.overall_misses::total 989 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66791248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66791248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66791248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66791248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66791248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66791248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13841797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13841797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13841797 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13841797 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13841797 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13841797 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67534.123357 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67534.123357 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67534.123357 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67534.123357 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13844401 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13844401 # number of overall hits +system.cpu.icache.overall_hits::total 13844401 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 991 # number of overall misses +system.cpu.icache.overall_misses::total 991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67770748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67770748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67770748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67770748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67770748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67770748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13845392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13845392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13845392 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13845392 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13845392 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13845392 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68386.224016 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68386.224016 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68386.224016 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68386.224016 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 651 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 256 # number of ReadReq MSHR hits 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-system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40706750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17150500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57857250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780571000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780571000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40706750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797721500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 838428250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40706750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797721500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 838428250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332693 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332693 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57576.732673 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63756.505576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59279.969262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53691.773284 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53691.773284 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15518 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41786750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17438000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59224750 # number of ReadReq MSHR miss cycles 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+system.cpu.l2cache.overall_mshr_miss_latency::total 839278500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332677 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332677 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016363 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58854.577465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64585.185185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60433.418367 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53656.194112 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53656.194112 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943519 # number of replacements -system.cpu.dcache.tags.tagsinuse 3671.753264 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28141899 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947615 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.697608 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8006034000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.753264 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896424 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23601231 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23601231 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532867 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532867 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 943502 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.733270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28144425 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947598 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.700807 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532846 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3913 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3913 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28134098 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28134098 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28134098 # number of overall hits -system.cpu.dcache.overall_hits::total 28134098 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173780 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173780 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202114 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202114 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28136618 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28136618 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28136618 # number of overall hits +system.cpu.dcache.overall_hits::total 28136618 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173981 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173981 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202135 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202135 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1375894 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1375894 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1375894 # number of overall misses -system.cpu.dcache.overall_misses::total 1375894 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893621478 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13893621478 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458573839 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8458573839 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1376116 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1376116 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1376116 # number of overall misses +system.cpu.dcache.overall_misses::total 1376116 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13894448479 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13894448479 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458649331 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8458649331 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22352195317 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22352195317 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22352195317 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22352195317 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24775011 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24775011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 22353097810 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22353097810 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22353097810 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22353097810 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24777753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24777753 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3920 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3920 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29509992 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29509992 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29509992 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29509992 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047378 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047378 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042685 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042685 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.648672 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.648672 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41850.509312 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41850.509312 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29512734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29512734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29512734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29512734 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042690 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042690 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046628 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046628 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046628 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046628 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.326533 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.326533 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41846.534895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41846.534895 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16245.579468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16245.579468 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154256 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16243.614499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16243.614499 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154190 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23957 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.440483 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.436115 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks -system.cpu.dcache.writebacks::total 942911 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269842 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269842 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158436 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158436 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks +system.cpu.dcache.writebacks::total 942892 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270066 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 270066 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428278 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428278 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428278 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428278 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903938 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903938 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43678 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43678 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994572760 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994572760 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319332173 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319332173 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313904933 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11313904933 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313904933 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11313904933 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.701632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.701632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30205.874193 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30205.874193 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 428516 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428516 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428516 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428516 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903915 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903915 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43685 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43685 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947600 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947600 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947600 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947600 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994483010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994483010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1318924416 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1318924416 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313407426 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11313407426 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313407426 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11313407426 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009226 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009226 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.883678 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.883678 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30191.700034 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30191.700034 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 11900168b..a7b21f16f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1149689b6..999935db6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.065614 # Nu sim_ticks 65613727000 # Number of ticks simulated final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90206 # Simulator instruction rate (inst/s) -host_op_rate 158838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37463203 # Simulator tick rate (ticks/s) -host_mem_usage 416624 # Number of bytes of host memory used -host_seconds 1751.42 # Real time elapsed on the host +host_inst_rate 72100 # Simulator instruction rate (inst/s) +host_op_rate 126957 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29943715 # Simulator tick rate (ticks/s) +host_mem_usage 436724 # Number of bytes of host memory used +host_seconds 2191.24 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory @@ -296,9 +296,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1957440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu.branchPred.lookups 33859770 # Number of BP lookups system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted @@ -373,24 +373,24 @@ system.cpu.memDep0.insertedLoads 101555761 # Nu system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued +system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -427,12 +427,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued @@ -461,27 +461,27 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued +system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued system.cpu.iq.rate 2.288206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested +system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding @@ -491,35 +491,35 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed +system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed system.cpu.iew.exec_branches 30820824 # Number of branches executed -system.cpu.iew.exec_stores 32925944 # Number of stores executed +system.cpu.iew.exec_stores 32925943 # Number of stores executed system.cpu.iew.exec_rate 2.277516 # Inst execution rate -system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218260008 # num instructions producing a value -system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value +system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218260006 # num instructions producing a value +system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle @@ -551,8 +551,8 @@ system.cpu.commit.int_insts 278169481 # Nu system.cpu.commit.function_calls 4237596 # Number of function calls committed. system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415950983 # The number of ROB reads -system.cpu.rob.rob_writes 627545403 # The number of ROB writes +system.cpu.rob.rob_reads 415950981 # The number of ROB reads +system.cpu.rob.rob_writes 627545399 # The number of ROB writes system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated @@ -562,13 +562,13 @@ system.cpu.cpi 0.830614 # CP system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483744134 # number of integer regfile reads -system.cpu.int_regfile_writes 234595253 # number of integer regfile writes +system.cpu.int_regfile_reads 483744129 # number of integer regfile reads +system.cpu.int_regfile_writes 234595251 # number of integer regfile writes system.cpu.fp_regfile_reads 141 # number of floating regfile reads system.cpu.fp_regfile_writes 77 # number of floating regfile writes system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes -system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads +system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution @@ -611,12 +611,12 @@ system.cpu.icache.demand_misses::cpu.inst 1305 # n system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses system.cpu.icache.overall_misses::total 1305 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses @@ -629,12 +629,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67940.036782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67940.036782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -655,24 +655,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1011 system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 69226501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69226501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69226501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 479 # number of replacements system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use @@ -711,17 +711,17 @@ system.cpu.l2cache.demand_misses::total 30419 # nu system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses system.cpu.l2cache.overall_misses::total 30419 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68041000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98030500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 68041000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 1974833000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 68041000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1974833000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses) @@ -746,17 +746,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014641 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.710262 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.579096 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 64921.036194 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 64921.036194 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -814,21 +814,21 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 2072514 # number of replacements system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 71413623 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits -system.cpu.dcache.overall_hits::total 71413624 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71413623 # number of overall hits +system.cpu.dcache.overall_hits::total 71413623 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses @@ -845,14 +845,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 42697676 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42697676 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses |