diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/se/10.mcf | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/se/10.mcf')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1118 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt | 182 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 198 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1014 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | 212 |
5 files changed, 1360 insertions, 1364 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 1a08f1a5c..b0555a54b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.028506 # Number of seconds simulated -sim_ticks 28505597000 # Number of ticks simulated -final_tick 28505597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025432 # Number of seconds simulated +sim_ticks 25432499000 # Number of ticks simulated +final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145688 # Simulator instruction rate (inst/s) -host_op_rate 146734 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45838175 # Simulator tick rate (ticks/s) -host_mem_usage 362080 # Number of bytes of host memory used -host_seconds 621.87 # Real time elapsed on the host -sim_insts 90599368 # Number of instructions simulated -sim_ops 91249921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 993216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 712 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15519 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1598563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33244278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34842842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1598563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1598563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1598563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33244278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 34842842 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 141358 # Simulator instruction rate (inst/s) +host_op_rate 142373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39681246 # Simulator tick rate (ticks/s) +host_mem_usage 367916 # Number of bytes of host memory used +host_seconds 640.92 # Real time elapsed on the host +sim_insts 90599358 # Number of instructions simulated +sim_ops 91249911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory +system.physmem.bytes_read::total 992960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1786690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37256268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39042958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1786690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1786690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1786690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37256268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 39042958 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,320 +70,318 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 57011195 # number of cpu cycles simulated +system.cpu.numCycles 50864999 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27014403 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22277078 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 889929 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11548760 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11430884 # Number of BTB hits +system.cpu.BPredUnit.lookups 26815832 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22064400 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 887268 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11482840 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11353380 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 73122 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 372 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14508892 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 129672886 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27014403 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11504006 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24367767 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4991272 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14021743 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 72941 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 493 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14339573 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128641990 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26815832 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11426321 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24202315 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4802086 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8372764 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14122126 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 347107 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 56945823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.293943 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.179113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14019260 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 376949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 50826068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.549806 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252225 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 32616008 57.28% 57.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3437208 6.04% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033940 3.57% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1577922 2.77% 69.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1684600 2.96% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3016320 5.30% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1478308 2.60% 80.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1110359 1.95% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9991158 17.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 26661639 52.46% 52.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3429294 6.75% 59.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2034587 4.00% 63.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1568872 3.09% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1675049 3.30% 69.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2962794 5.83% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1484032 2.92% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1105241 2.17% 80.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9904560 19.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 56945823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.473844 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.274516 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17727827 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11442534 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22314035 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1422886 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4038541 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4486849 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8989 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 127753929 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42812 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4038541 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19463622 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5507295 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 178125 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21532560 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6225680 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124585344 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 540744 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4833961 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11275 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145162652 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 542774349 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 542766580 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37733154 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6541 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6539 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14204519 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29836795 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5560829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2097523 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1243222 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119152184 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10385 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105702713 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27697349 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68611569 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 56945823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.856198 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.856170 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 50826068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.527196 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.529087 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16897392 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6458273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22716084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 851770 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3902549 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4473858 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8976 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126855886 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42929 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3902549 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18614164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1601921 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 162955 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21830794 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4713685 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123685119 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 281691 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3991082 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 144136379 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 538783715 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 538776344 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7371 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36706897 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6470 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6468 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 10859255 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29577544 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5541374 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2075747 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1267218 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118433426 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10344 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105554764 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 73541 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26995758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 66330940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 50826068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.076784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.959181 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17311609 30.40% 30.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13029602 22.88% 53.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8527913 14.98% 68.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6948954 12.20% 80.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5271164 9.26% 89.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2793517 4.91% 94.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2152448 3.78% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 481434 0.85% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 429182 0.75% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13833219 27.22% 27.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10749724 21.15% 48.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7931783 15.61% 63.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6457025 12.70% 76.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4857915 9.56% 86.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3493885 6.87% 93.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2371067 4.67% 97.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 608688 1.20% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 522762 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 56945823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 50826068 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 40477 6.05% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 349114 52.21% 58.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 279085 41.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 142420 18.36% 18.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 354766 45.74% 64.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 278332 35.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74715129 70.68% 70.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10969 0.01% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 226 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 287 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25832645 24.44% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5143450 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74645911 70.72% 70.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10962 0.01% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 239 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 298 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25762945 24.41% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5134404 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105702713 # Type of FU issued -system.cpu.iq.rate 1.854069 # Inst issue rate -system.cpu.iq.fu_busy_cnt 668703 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006326 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 269098152 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146861999 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102960296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1111 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1652 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 475 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106370866 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 550 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 430808 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105554764 # Type of FU issued +system.cpu.iq.rate 2.075194 # Inst issue rate +system.cpu.iq.fu_busy_cnt 775545 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262783539 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 145440732 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102807034 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1143 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1553 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 495 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106329739 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 570 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 435536 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7260915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7599 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4486 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 814071 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7001666 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7849 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3639 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 794618 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 165011 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 13641 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4038541 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 891747 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 116973 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119175285 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342275 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29836795 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5560829 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6480 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49074 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15714 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4486 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 478618 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 473981 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 952599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104642381 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25500898 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1060332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3902549 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 96175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18780 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118456487 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 345131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29577544 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5541374 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6439 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4987 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4015 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3639 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 474441 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 478533 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 952974 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104393226 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25307547 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1161538 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12716 # number of nop insts executed -system.cpu.iew.exec_refs 30579562 # number of memory reference insts executed -system.cpu.iew.exec_branches 21366362 # Number of branches executed -system.cpu.iew.exec_stores 5078664 # Number of stores executed -system.cpu.iew.exec_rate 1.835471 # Inst execution rate -system.cpu.iew.wb_sent 103249709 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102960771 # cumulative count of insts written-back -system.cpu.iew.wb_producers 61941288 # num instructions producing a value -system.cpu.iew.wb_consumers 102916553 # num instructions consuming a value +system.cpu.iew.exec_nop 12717 # number of nop insts executed +system.cpu.iew.exec_refs 30377969 # number of memory reference insts executed +system.cpu.iew.exec_branches 21353332 # Number of branches executed +system.cpu.iew.exec_stores 5070422 # Number of stores executed +system.cpu.iew.exec_rate 2.052359 # Inst execution rate +system.cpu.iew.wb_sent 103118433 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102807529 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62180383 # num instructions producing a value +system.cpu.iew.wb_consumers 104132992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.805975 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601859 # average fanout of values written-back +system.cpu.iew.wb_rate 2.021184 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.597125 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27915285 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 881077 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52907283 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.724952 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.476924 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 27194508 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 878429 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 46923520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.944921 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.520501 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22917585 43.32% 43.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13525297 25.56% 68.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4253401 8.04% 76.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3602316 6.81% 83.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1554565 2.94% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 724715 1.37% 88.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 894547 1.69% 89.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 264490 0.50% 90.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5170367 9.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16620645 35.42% 35.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13501207 28.77% 64.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4487454 9.56% 73.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3864489 8.24% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1521327 3.24% 85.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 782022 1.67% 86.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 855558 1.82% 88.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 262372 0.56% 89.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5028446 10.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52907283 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611977 # Number of instructions committed -system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 46923520 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611967 # Number of instructions committed +system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322638 # Number of memory references committed -system.cpu.commit.loads 22575880 # Number of loads committed +system.cpu.commit.refs 27322634 # Number of memory references committed +system.cpu.commit.loads 22575878 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18734218 # Number of branches committed +system.cpu.commit.branches 18734216 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533330 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5170367 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5028446 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 166908997 # The number of ROB reads -system.cpu.rob.rob_writes 242415249 # The number of ROB writes -system.cpu.timesIdled 17140 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65372 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599368 # Number of Instructions Simulated -system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated -system.cpu.cpi 0.629267 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.629267 # CPI: Total CPI of All Threads -system.cpu.ipc 1.589150 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.589150 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497539806 # number of integer regfile reads -system.cpu.int_regfile_writes 120848373 # number of integer regfile writes -system.cpu.fp_regfile_reads 239 # number of floating regfile reads -system.cpu.fp_regfile_writes 624 # number of floating regfile writes -system.cpu.misc_regfile_reads 183493284 # number of misc regfile reads -system.cpu.misc_regfile_writes 11612 # number of misc regfile writes +system.cpu.rob.rob_reads 160346368 # The number of ROB reads +system.cpu.rob.rob_writes 240838970 # The number of ROB writes +system.cpu.timesIdled 1282 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38931 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599358 # Number of Instructions Simulated +system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated +system.cpu.cpi 0.561428 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561428 # CPI: Total CPI of All Threads +system.cpu.ipc 1.781173 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.781173 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496237676 # number of integer regfile reads +system.cpu.int_regfile_writes 120715642 # number of integer regfile writes +system.cpu.fp_regfile_reads 235 # number of floating regfile reads +system.cpu.fp_regfile_writes 643 # number of floating regfile writes +system.cpu.misc_regfile_reads 182128613 # number of misc regfile reads +system.cpu.misc_regfile_writes 11608 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 636.231301 # Cycle average of tags in use -system.cpu.icache.total_refs 14121140 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 635.871073 # Cycle average of tags in use +system.cpu.icache.total_refs 14018279 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 738 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19134.336043 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18994.957995 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 636.231301 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310660 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310660 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14121140 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14121140 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14121140 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14121140 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14121140 # number of overall hits -system.cpu.icache.overall_hits::total 14121140 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 986 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 986 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 986 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 986 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 986 # number of overall misses -system.cpu.icache.overall_misses::total 986 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35670500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35670500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35670500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35670500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35670500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35670500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14122126 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14122126 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14122126 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14122126 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14122126 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14122126 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 635.871073 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310484 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310484 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14018279 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14018279 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14018279 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14018279 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14018279 # number of overall hits +system.cpu.icache.overall_hits::total 14018279 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 981 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 981 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 981 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 981 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 981 # number of overall misses +system.cpu.icache.overall_misses::total 981 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34205000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34205000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34205000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34205000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34205000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34205000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14019260 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14019260 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14019260 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14019260 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14019260 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14019260 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36176.977688 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36176.977688 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36176.977688 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36176.977688 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34867.482161 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34867.482161 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34867.482161 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34867.482161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34867.482161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34867.482161 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,246 +390,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 738 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 738 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 738 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 738 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26658000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26658000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26658000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26658000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26658000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26658000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36121.951220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36121.951220 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26308000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26308000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35647.696477 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35647.696477 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35647.696477 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35647.696477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35647.696477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35647.696477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943542 # number of replacements -system.cpu.dcache.tagsinuse 3691.655008 # Cycle average of tags in use -system.cpu.dcache.total_refs 28378395 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947638 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.946451 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8118725000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3691.655008 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.901283 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.901283 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23798260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23798260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4568472 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4568472 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5862 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5862 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28366732 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28366732 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28366732 # number of overall hits -system.cpu.dcache.overall_hits::total 28366732 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1060889 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1060889 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 166509 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 166509 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1227398 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1227398 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1227398 # number of overall misses -system.cpu.dcache.overall_misses::total 1227398 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21973475500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21973475500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6211010261 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6211010261 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 161000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 161000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28184485761 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28184485761 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28184485761 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28184485761 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24859149 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24859149 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943636 # number of replacements +system.cpu.dcache.tagsinuse 3643.742201 # Cycle average of tags in use +system.cpu.dcache.total_refs 28404607 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947732 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.971138 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8103531000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3643.742201 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.889585 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.889585 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23813813 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23813813 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4579150 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4579150 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5845 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5845 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28392963 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28392963 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28392963 # number of overall hits +system.cpu.dcache.overall_hits::total 28392963 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 995922 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 995922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 155831 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 155831 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1151753 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1151753 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1151753 # number of overall misses +system.cpu.dcache.overall_misses::total 1151753 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4102006500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4102006500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4011864060 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4011864060 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 120000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8113870560 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8113870560 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8113870560 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8113870560 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24809735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24809735 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5870 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5870 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29594130 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29594130 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29594130 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29594130 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042676 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.042676 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.035166 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001363 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001363 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20712.322873 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20712.322873 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37301.348642 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37301.348642 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22962.792640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22962.792640 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78891432 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5852 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5852 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29544716 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29544716 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29544716 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29544716 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040142 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040142 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032911 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001196 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001196 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038983 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038983 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038983 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038983 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4118.802979 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 4118.802979 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25744.967689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25744.967689 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7044.800890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7044.800890 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8960217 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9153 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8619.188463 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1374.477220 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942894 # number of writebacks -system.cpu.dcache.writebacks::total 942894 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148366 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 148366 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131394 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 131394 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 279760 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 279760 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 279760 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 279760 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912523 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 912523 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35115 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 35115 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16758552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16758552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1752488893 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1752488893 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18511040893 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18511040893 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18511040893 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18511040893 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036708 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036708 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007416 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007416 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18365.073538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18365.073538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49907.130656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49907.130656 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 943006 # number of writebacks +system.cpu.dcache.writebacks::total 943006 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82809 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82809 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 121212 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 121212 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 204021 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 204021 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 204021 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 204021 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 913113 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 913113 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 34619 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 34619 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947732 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947732 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036805 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036805 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007311 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007311 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2059.137807 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2059.137807 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20278.474508 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20278.474508 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2724.658457 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 2724.658457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2724.658457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 2724.658457 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10969.237336 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1839897 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15502 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.687718 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10473.281508 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1840746 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15498 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.773132 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10112.492667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 621.566782 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 235.177887 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.308609 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018969 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007177 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.334755 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 509520000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 535050000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 738 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 912378 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 913116 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942894 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942894 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 35260 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 35260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 913112 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 913850 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 943006 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 943006 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 34620 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 34620 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 738 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947638 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948376 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947732 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948470 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 738 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947638 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948376 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967480 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412223 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.412223 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967480 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016376 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967480 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016376 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35759.103641 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36787.234043 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36050.200803 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34385.173719 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34385.173719 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34491.951581 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34491.951581 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 947732 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948470 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964770 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000303 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001082 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419931 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.419931 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964770 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015632 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016371 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964770 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015632 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016371 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35856.741573 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36972.924188 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36169.362993 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34342.997661 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34342.997661 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35856.741573 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34392.170098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34459.328911 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35856.741573 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34392.170098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34459.328911 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,50 +647,50 @@ system.cpu.l2cache.demand_mshr_hits::total 12 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14535 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14535 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 712 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15519 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 712 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9198500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32438500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 453435000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 453435000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 485873500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462633500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 485873500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001078 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412223 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412223 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.449438 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33818.014706 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32965.955285 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.078431 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.078431 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 710 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 977 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15515 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23238000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9078500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32316500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451969500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451969500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23238000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 461048000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 484286000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23238000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 461048000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 484286000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001069 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32729.577465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34001.872659 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33077.277380 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31088.836154 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31088.836154 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32729.577465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31214.050918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32729.577465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31214.050918 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 3cd60c7e5..9850fa37f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148268 # Number of seconds simulated -sim_ticks 148267705000 # Number of ticks simulated -final_tick 148267705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.147136 # Number of seconds simulated +sim_ticks 147135976000 # Number of ticks simulated +final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1153616 # Simulator instruction rate (inst/s) -host_op_rate 1161887 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1888384270 # Simulator tick rate (ticks/s) -host_mem_usage 360564 # Number of bytes of host memory used -host_seconds 78.52 # Real time elapsed on the host +host_inst_rate 1039833 # Simulator instruction rate (inst/s) +host_op_rate 1047288 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1689137215 # Simulator tick rate (ticks/s) +host_mem_usage 366884 # Number of bytes of host memory used +host_seconds 87.11 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 36992 # Nu system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 249495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6372042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6621536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 249495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 249495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 249495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6372042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6621536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 251414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6421054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6672467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 251414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 251414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 296535410 # number of cpu cycles simulated +system.cpu.numCycles 294271952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576861 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 27318810 # nu system.cpu.num_load_insts 22573966 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 296535410 # Number of busy cycles +system.cpu.num_busy_cycles 294271952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 510.369252 # Cycle average of tags in use +system.cpu.icache.tagsinuse 510.071144 # Cycle average of tags in use system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.369252 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.249204 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.249204 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.249058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32709000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32709000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32709000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32709000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32709000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32709000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32063000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32063000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32063000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32063000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32063000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32063000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54606.010017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54606.010017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54606.010017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54606.010017 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53527.545910 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53527.545910 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53527.545910 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53527.545910 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30912000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30912000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30912000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30912000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30912000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30912000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51606.010017 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51606.010017 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements -system.cpu.dcache.tagsinuse 3568.972050 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54491057000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3568.972050 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.871331 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.871331 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses system.cpu.dcache.overall_misses::total 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12648933000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12648933000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1288595000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1288595000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13937528000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13937528000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13937528000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13937528000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14051.419202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14051.419202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27646.913686 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27646.913686 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14720.698607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14720.698607 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798 system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9948366000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9948366000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148768000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148768000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11097134000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11097134000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11097134000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11097134000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11051.419202 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11051.419202 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24646.913686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24646.913686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9602.986186 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8914.312589 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 495.421771 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 193.251826 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.272043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.015119 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.293060 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.291909 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 44702e46f..e3f69f56e 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.362482 # Number of seconds simulated -sim_ticks 362481563000 # Number of ticks simulated -final_tick 362481563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361489 # Number of seconds simulated +sim_ticks 361488530000 # Number of ticks simulated +final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1415125 # Simulator instruction rate (inst/s) -host_op_rate 1415183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2103788292 # Simulator tick rate (ticks/s) -host_mem_usage 363728 # Number of bytes of host memory used -host_seconds 172.30 # Real time elapsed on the host +host_inst_rate 1171246 # Simulator instruction rate (inst/s) +host_op_rate 1171295 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1736457304 # Simulator tick rate (ticks/s) +host_mem_usage 354676 # Number of bytes of host memory used +host_seconds 208.18 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 56256 # Nu system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 724963126 # number of cpu cycles simulated +system.cpu.numCycles 722977060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 724963126 # Number of busy cycles +system.cpu.num_busy_cycles 722977060 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 725.564713 # Cycle average of tags in use +system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 725.564713 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55933.106576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55933.106576 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46687000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46687000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3563.804941 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134384267000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3563.804941 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12510586000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12510586000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14664.344320 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14664.344320 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9832015000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9832015000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1127418000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1127418000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 89000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 89000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10959433000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10959433000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10959433000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10959433000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -237,30 +237,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9744.633464 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8861.505031 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 738.799835 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 144.328599 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.297383 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 516126aba..cad348d1e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,174 +1,174 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064346 # Number of seconds simulated -sim_ticks 64346040000 # Number of ticks simulated -final_tick 64346040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061487 # Number of seconds simulated +sim_ticks 61487437500 # Number of ticks simulated +final_tick 61487437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132449 # Simulator instruction rate (inst/s) -host_op_rate 233222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53944275 # Simulator tick rate (ticks/s) -host_mem_usage 365660 # Number of bytes of host memory used -host_seconds 1192.82 # Real time elapsed on the host +host_inst_rate 86290 # Simulator instruction rate (inst/s) +host_op_rate 151942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33582980 # Simulator tick rate (ticks/s) +host_mem_usage 365956 # Number of bytes of host memory used +host_seconds 1830.91 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1893376 # Number of bytes read from this memory -system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1893056 # Number of bytes read from this memory +system.physmem.bytes_read::total 1961408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20416 # Number of bytes written to this memory -system.physmem.bytes_written::total 20416 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory +system.physmem.bytes_written::total 20288 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29584 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory -system.physmem.num_writes::total 319 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 29424903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 317284 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 29424903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30804444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 29579 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30647 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory +system.physmem.num_writes::total 317 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1111642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30787687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31899329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1111642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1111642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 329954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 329954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 329954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1111642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30787687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32229283 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 128692081 # number of cpu cycles simulated +system.cpu.numCycles 122974876 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 35576702 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1085312 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25399500 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25270525 # Number of BTB hits +system.cpu.BPredUnit.lookups 35563581 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 35563581 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1083908 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25421016 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25287599 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27884150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 193525000 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35576702 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25270525 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 58636506 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7358089 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35916291 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27160167 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 295674 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128658357 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.644591 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27814300 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 193613700 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35563581 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25287599 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 58598336 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7345607 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 30298263 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 223 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27172491 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 322176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 122946211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.768410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.402032 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 72765830 56.56% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2056683 1.60% 58.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3006413 2.34% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4027268 3.13% 63.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8003806 6.22% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5026752 3.91% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2893556 2.25% 76.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1437345 1.12% 77.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29440704 22.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67085101 54.56% 54.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2067083 1.68% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2985500 2.43% 58.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3997651 3.25% 61.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7978379 6.49% 68.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5028202 4.09% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2861375 2.33% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1431598 1.16% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29511322 24.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128658357 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.276448 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.503783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 39452105 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 27727798 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46961382 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8295915 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6221157 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336436945 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 6221157 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44164076 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5970160 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9070 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50268632 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22025262 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 331751360 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 262 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6842 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20121054 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 216 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 334012838 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 880453680 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 880451759 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1921 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 122946211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289194 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.574417 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38912587 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 22600530 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 48050125 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7147919 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6235050 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336030812 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 6235050 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43304200 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3170225 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8978 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50645325 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19582433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 332156996 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3311 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 17907327 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 182 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 334503257 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 881229115 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 881227036 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2079 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 54800094 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 485 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 50437110 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104594760 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36334761 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 41480583 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6245732 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 323452648 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 55290513 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 484 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 44388140 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104937995 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36474446 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 41500364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5836392 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 323873529 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307818254 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198387 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 45033296 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65280307 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 307729409 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 216713 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 45479887 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 66424397 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128658357 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.392524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.788521 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 122946211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.502960 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.799833 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25721748 19.99% 19.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18649480 14.50% 34.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 23014823 17.89% 52.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 27362657 21.27% 73.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 17010472 13.22% 86.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9600725 7.46% 94.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6243189 4.85% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 895594 0.70% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 159669 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21631935 17.59% 17.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17051158 13.87% 31.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24526773 19.95% 51.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 23966381 19.49% 70.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19143829 15.57% 86.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9189049 7.47% 93.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5012385 4.08% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2266917 1.84% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 157784 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128658357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 122946211 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35279 1.70% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1868126 90.18% 91.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 168108 8.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 50945 1.97% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1871750 72.23% 74.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 668572 25.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 29245 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174946374 56.83% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33168 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174887442 56.83% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 52 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued @@ -194,84 +194,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99043059 32.18% 89.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33799538 10.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98817076 32.11% 88.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33991671 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307818254 # Type of FU issued -system.cpu.iq.rate 2.391897 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2071513 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006730 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 746564211 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 368519272 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304587112 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 554 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 943 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 186 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 309860246 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 276 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52574701 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307729409 # Type of FU issued +system.cpu.iq.rate 2.502376 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2591267 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008421 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 741212334 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 369384855 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 304533759 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 675 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 209 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 310287186 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 322 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52324197 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13815376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 44181 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33341 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4895010 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14158611 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 53020 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 31592 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5034695 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 36659 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3174 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6221157 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 782061 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 89817 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 323454406 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 362446 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104594760 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36334761 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 480 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 611 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 22270 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33341 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 595275 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 582931 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1178206 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 305708901 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98426933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2109353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6235050 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 247932 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19449 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 323875287 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 344865 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104937995 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36474446 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 247 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 894 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31592 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 595265 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 583416 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1178681 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 305536893 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98199399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2192516 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131805652 # number of memory reference insts executed -system.cpu.iew.exec_branches 31122940 # Number of branches executed -system.cpu.iew.exec_stores 33378719 # Number of stores executed -system.cpu.iew.exec_rate 2.375507 # Inst execution rate -system.cpu.iew.wb_sent 305078305 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304587298 # cumulative count of insts written-back -system.cpu.iew.wb_producers 225979119 # num instructions producing a value -system.cpu.iew.wb_consumers 311384301 # num instructions consuming a value +system.cpu.iew.exec_refs 131640830 # number of memory reference insts executed +system.cpu.iew.exec_branches 31219911 # Number of branches executed +system.cpu.iew.exec_stores 33441431 # Number of stores executed +system.cpu.iew.exec_rate 2.484547 # Inst execution rate +system.cpu.iew.wb_sent 304949933 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304533968 # cumulative count of insts written-back +system.cpu.iew.wb_producers 225863686 # num instructions producing a value +system.cpu.iew.wb_consumers 311805704 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.366791 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.725724 # average fanout of values written-back +system.cpu.iew.wb_rate 2.476392 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724373 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 45269554 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 45684582 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1085338 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122437200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.272124 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.827291 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1083935 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 116711161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.383598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.781080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 46942462 38.34% 38.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 21185475 17.30% 55.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15973782 13.05% 68.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12948459 10.58% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1961875 1.60% 80.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1887285 1.54% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1388960 1.13% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 594855 0.49% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 19554047 15.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38716768 33.17% 33.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22386952 19.18% 52.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17053265 14.61% 66.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13105313 11.23% 78.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2048873 1.76% 79.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3220721 2.76% 82.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1361336 1.17% 83.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 627536 0.54% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18190397 15.59% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122437200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 116711161 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -282,69 +282,69 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 19554047 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18190397 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 426345169 # The number of ROB reads -system.cpu.rob.rob_writes 653150724 # The number of ROB writes -system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33724 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 422397808 # The number of ROB reads +system.cpu.rob.rob_writes 653994696 # The number of ROB writes +system.cpu.timesIdled 646 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28665 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.814566 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.814566 # CPI: Total CPI of All Threads -system.cpu.ipc 1.227648 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.227648 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 598601369 # number of integer regfile reads -system.cpu.int_regfile_writes 305356910 # number of integer regfile writes -system.cpu.fp_regfile_reads 165 # number of floating regfile reads -system.cpu.fp_regfile_writes 88 # number of floating regfile writes -system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads -system.cpu.icache.replacements 92 # number of replacements -system.cpu.icache.tagsinuse 843.498155 # Cycle average of tags in use -system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. +system.cpu.cpi 0.778378 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.778378 # CPI: Total CPI of All Threads +system.cpu.ipc 1.284722 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.284722 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 598611638 # number of integer regfile reads +system.cpu.int_regfile_writes 305159096 # number of integer regfile writes +system.cpu.fp_regfile_reads 198 # number of floating regfile reads +system.cpu.fp_regfile_writes 109 # number of floating regfile writes +system.cpu.misc_regfile_reads 195504004 # number of misc regfile reads +system.cpu.icache.replacements 86 # number of replacements +system.cpu.icache.tagsinuse 846.025687 # Cycle average of tags in use +system.cpu.icache.total_refs 27171094 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1075 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25275.436279 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 843.498155 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27158782 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27158782 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27158782 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27158782 # number of overall hits -system.cpu.icache.overall_hits::total 27158782 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses -system.cpu.icache.overall_misses::total 1385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51455500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51455500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51455500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51455500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51455500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51455500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27160167 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27160167 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27160167 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 846.025687 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.413098 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.413098 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27171094 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27171094 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27171094 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27171094 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27171094 # number of overall hits +system.cpu.icache.overall_hits::total 27171094 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1397 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1397 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1397 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1397 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1397 # number of overall misses +system.cpu.icache.overall_misses::total 1397 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49824500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49824500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49824500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49824500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49824500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49824500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27172491 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27172491 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27172491 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27172491 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27172491 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27172491 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076044 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076044 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4061724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4061724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125939500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125939500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5187664000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5187664000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5187664000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5187664000 # 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16021.590757 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026866 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026866 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026866 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026866 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2036.990536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2036.990536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13720.762603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13720.762603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2498.821798 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 2498.821798 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2498.821798 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 2498.821798 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1466 # number of replacements -system.cpu.l2cache.tagsinuse 19909.538394 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4027133 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82155 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076246 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077322 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076246 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077322 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000830 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35535.326087 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34181.423724 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34181.423724 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82138 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82138 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076042 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077117 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076042 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077117 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993488 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000294 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000829 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352979 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352979 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993488 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014248 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993488 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014248 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35642.790262 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35973.549488 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35759.975816 # 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number of cycles access was blocked @@ -591,60 +589,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 319 # number of writebacks -system.cpu.l2cache.writebacks::total 319 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks +system.cpu.l2cache.writebacks::total 317 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1656 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 586 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1654 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29584 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29579 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30647 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34498500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 952810000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34498500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 952810000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32301.966292 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.952381 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32374.396135 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 29579 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30647 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34670500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19225500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53896000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34670500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918354000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 953024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34670500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918354000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 953024500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352979 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352979 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32463.014981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32808.020478 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32585.247884 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.916670 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.916670 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 197e85700..0458ec538 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.368209 # Number of seconds simulated -sim_ticks 368209206000 # Number of ticks simulated -final_tick 368209206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365994 # Number of seconds simulated +sim_ticks 365994481000 # Number of ticks simulated +final_tick 365994481000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 501886 # Simulator instruction rate (inst/s) -host_op_rate 883741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1169699500 # Simulator tick rate (ticks/s) -host_mem_usage 408944 # Number of bytes of host memory used -host_seconds 314.79 # Real time elapsed on the host +host_inst_rate 452383 # Simulator instruction rate (inst/s) +host_op_rate 796575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1047986231 # Simulator tick rate (ticks/s) +host_mem_usage 363904 # Number of bytes of host memory used +host_seconds 349.24 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 29370 # Nu system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory system.physmem.num_writes::total 227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5104924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5245366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5104924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5284822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 141292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5135815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5277107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 141292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 39695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 39695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 141292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5135815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5316801 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 736418412 # number of cpu cycles simulated +system.cpu.numCycles 731988962 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 122219135 # nu system.cpu.num_load_insts 90779384 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 736418412 # Number of busy cycles +system.cpu.num_busy_cycles 731988962 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.897748 # Cycle average of tags in use +system.cpu.icache.tagsinuse 665.633473 # Cycle average of tags in use system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.897748 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 665.633473 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45336000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45336000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45336000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44440000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44440000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44440000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44440000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44440000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44440000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56108.910891 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56108.910891 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56108.910891 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56108.910891 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42912000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42912000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42912000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42912000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42912000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42912000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53108.910891 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53108.910891 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.463619 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.488929 # Cycle average of tags in use system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126234066000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.463619 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995230 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995230 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.488929 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995237 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995237 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27487330000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27487330000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2708348000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2708348000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30195678000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25503766000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25503766000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598582000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598582000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28102348000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28102348000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28102348000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28102348000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14018.998123 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14018.998123 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25524.206241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25524.206241 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14609.664370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14609.664370 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.347301 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.347301 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24489.741681 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24489.741681 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13596.842313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13596.842313 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21605170000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21605170000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2390019500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2390019500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23995189500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23995189500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23995189500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23995189500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386364000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386364000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968690000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23968690000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968690000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23968690000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11018.998123 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11018.998123 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22524.192104 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22524.192104 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.741681 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.741681 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 19722.099231 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19679.255550 # Cycle average of tags in use system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19370.045173 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 209.723718 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 142.330341 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.591127 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006400 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.601871 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 19326.193704 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 210.694953 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 142.366893 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.589789 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.006430 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004345 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.600563 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits @@ -272,14 +272,14 @@ system.cpu.l2cache.overall_misses::total 30178 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509433500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1509433500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509435000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1509435000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1527269500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1569285500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1527271000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1569287000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1527269500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1569285500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1527271000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1569287000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) @@ -307,14 +307,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.014595 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.016295 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.016295 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.067971 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.067971 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.977533 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52001.027238 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.977533 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52001.027238 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |