tests: Final reclassification of quick regressions

A few regressions were still considered long, but finished well within
the 180 seconds. They are only a handful (mostly mcf in atomic).

--HG--
rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
rename : tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal
rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/se/10.mcf/test.py => tests/quick/se/10.mcf/test.py
rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/se/30.eon/test.py => tests/quick/se/30.eon/test.py

22 files changed, 0 insertions, 6277 deletions

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
deleted file mode 100644
index 9ac19076f..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
+++ /dev/null
@@ -1,4 +0,0 @@
-P6
-15 15
-255
-


			   !!!   !!!$$$&&&'''&&&%%%


!!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))'''   """%%%&&&'''&&&%%%%%%      !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
deleted file mode 100644
index 392920ac8..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,270 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[6]
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[5]
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
-gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
-500
-()
-499
-()
-498
-()
-496
-()
-495
-()
-494
-()
-493
-()
-492
-()
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-490
-()
-489
-()
-488
-()
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-()
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-()
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-()
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-()
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-480
-()
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-()
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-()
-472
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-469
-()
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-433
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-431
-()
-428
-()
-427
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-()
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-420
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-419
-()
-416
-()
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-()
-407
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-***
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-()
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-()
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-***
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-()
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-()
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-***
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-()
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-***
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-()
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-***
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-()
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-***
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-()
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-()
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-***
-485
-()
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-***
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-()
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-***
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-()
-292
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-()
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-110
-***
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-()
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-()
-108
-***
-281
-()
-107
-***
-144
-***
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-()
-106
-***
-275
-()
-105
-***
-196
-***
-254
-()
-104
-***
-138
-***
-161
-()
-103
-***
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-()
-102
-***
-223
-***
-252
-()
-80
-()
-70
-()
-69
-()
-68
-()
-66
-()
-64
-()
-62
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-256
-()
-61
-***
-93
-()
-59
-***
-120
-()
-58
-()
-57
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-183
-()
-55
-()
-54
-()
-52
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-147
-()
-51
-***
-118
-()
-50
-***
-83
-()
-49
-***
-98
-()
-48
-***
-99
-()
-47
-()
-46
-***
-184
-()
-45
-***
-121
-()
-44
-()
-43
-***
-88
-()
-42
-***
-122
-()
-41
-***
-91
-()
-40
-***
-96
-()
-38
-***
-100
-()
-37
-***
-149
-()
-36
-***
-74
-()
-35
-***
-258
-()
-34
-***
-151
-()
-33
-***
-85
-()
-32
-()
-31
-***
-94
-()
-30
-***
-97
-()
-29
-***
-90
-()
-28
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-89
-()
-27
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-92
-()
-26
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-72
-***
-247
-()
-25
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-86
-()
-24
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-82
-()
-23
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-***
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-()
-22
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-76
-***
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-()
-21
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-()
-20
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-()
-19
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-73
-()
-18
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-81
-()
-17
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-65
-()
-16
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-63
-***
-101
-()
-15
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-71
-()
-14
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-()
-13
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-322
-()
-12
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-()
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-()
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-79
-()
-9
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-150
-()
-8
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-67
-()
-7
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-60
-***
-231
-()
-6
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-56
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-234
-()
-5
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-164
-***
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-()
-4
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-53
-()
-3
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diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
deleted file mode 100755
index 1a4f96712..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
+++ /dev/null
@@ -1 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
deleted file mode 100755
index c759bbe65..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ /dev/null
@@ -1,27 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:11:38
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x63b66c0
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 54240661000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
deleted file mode 100644
index b143a6790..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,245 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.054141                       # Number of seconds simulated
-sim_ticks                                 54141000000                       # Number of ticks simulated
-final_tick                                54141000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1893120                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1902548                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1131265211                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 433636                       # Number of bytes of host memory used
-host_seconds                                    47.86                       # Real time elapsed on the host
-sim_insts                                    90602407                       # Number of instructions simulated
-sim_ops                                      91053638                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         431323080                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          90016598                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            521339678                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    431323080                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       431323080                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       18908138                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18908138                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          107830770                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           22461532                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             130292302                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data           4738868                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              4738868                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7966662603                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1662632718                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9629295321                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7966662603                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7966662603                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           349238802                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              349238802                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7966662603                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2011871521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             9978534124                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        108282001                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    90602407                       # Number of instructions committed
-system.cpu.committedOps                      91053638                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              72326352                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                      112245                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     72326352                       # number of integer instructions
-system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           124257699                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            271814240                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            53956115                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      27220755                       # number of memory refs
-system.cpu.num_load_insts                    22475911                       # Number of load instructions
-system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               108282000.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          18732304                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  63822828     70.09%     70.09% # Class of executed instruction
-system.cpu.op_class::IntMult                    10474      0.01%     70.10% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::MemRead                 22475911     24.68%     94.79% # Class of executed instruction
-system.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   91054080                       # Class of executed instruction
-system.membus.trans_dist::ReadReq           130287905                       # Transaction distribution
-system.membus.trans_dist::ReadResp          130291792                       # Transaction distribution
-system.membus.trans_dist::WriteReq            4734981                       # Transaction distribution
-system.membus.trans_dist::WriteResp           4734981                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq               510                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp              510                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq          3887                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq           3887                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp          3887                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    215661540                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     54400800                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              270062340                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    431323080                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    108924736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               540247816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         135031170                       # Request fanout histogram
-system.membus.snoop_fanout::mean             2.798562                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.401074                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                27200400     20.14%     20.14% # Request fanout histogram
-system.membus.snoop_fanout::3               107830770     79.86%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               3                       # Request fanout histogram
-system.membus.snoop_fanout::total           135031170                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
deleted file mode 100644
index 9ac19076f..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
+++ /dev/null
@@ -1,4 +0,0 @@
-P6
-15 15
-255
-


			   !!!   !!!$$$&&&'''&&&%%%


!!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))'''   """%%%&&&'''&&&%%%%%%      !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
deleted file mode 100644
index e662df1f5..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ /dev/null
@@ -1,383 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[5]
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[4]
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
-gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
-500
-()
-499
-()
-498
-()
-496
-()
-495
-()
-494
-()
-493
-()
-492
-()
-491
-()
-490
-()
-489
-()
-488
-()
-487
-()
-486
-()
-484
-()
-482
-()
-481
-()
-480
-()
-479
-()
-478
-()
-477
-()
-476
-()
-475
-()
-474
-()
-473
-()
-472
-()
-471
-()
-469
-()
-468
-()
-467
-()
-466
-()
-465
-()
-464
-()
-463
-()
-462
-()
-461
-()
-460
-()
-459
-()
-458
-()
-457
-()
-455
-()
-454
-()
-452
-()
-451
-()
-450
-()
-449
-()
-448
-()
-446
-()
-445
-()
-444
-()
-443
-()
-442
-()
-440
-()
-439
-()
-438
-()
-436
-()
-435
-()
-433
-()
-432
-()
-431
-()
-428
-()
-427
-()
-425
-()
-424
-()
-423
-()
-420
-()
-419
-()
-416
-()
-414
-()
-413
-()
-412
-()
-407
-()
-406
-()
-405
-()
-404
-()
-403
-()
-402
-()
-401
-()
-400
-()
-399
-()
-398
-()
-396
-()
-395
-()
-393
-()
-392
-()
-390
-()
-389
-()
-388
-()
-387
-()
-386
-()
-385
-()
-384
-()
-383
-()
-382
-()
-381
-()
-380
-()
-379
-()
-377
-()
-375
-()
-374
-()
-373
-()
-372
-()
-371
-()
-370
-()
-369
-()
-368
-()
-366
-()
-365
-()
-364
-()
-362
-()
-361
-()
-360
-()
-359
-()
-358
-()
-357
-()
-356
-()
-355
-()
-354
-()
-352
-()
-350
-()
-347
-()
-344
-()
-342
-()
-341
-()
-340
-()
-339
-()
-338
-()
-332
-()
-325
-()
-320
-***
-345
-()
-319
-***
-497
-()
-318
-***
-349
-()
-317
-***
-408
-()
-316
-***
-324
-()
-315
-***
-328
-()
-314
-***
-335
-()
-313
-***
-378
-()
-312
-***
-426
-()
-311
-***
-411
-()
-304
-***
-343
-()
-303
-***
-417
-()
-302
-***
-485
-()
-301
-***
-363
-()
-300
-***
-376
-()
-299
-***
-333
-()
-292
-***
-337
-()
-291
-***
-409
-()
-290
-***
-421
-()
-289
-***
-437
-()
-288
-***
-430
-()
-287
-***
-348
-()
-286
-***
-326
-()
-284
-()
-282
-***
-308
-()
-279
-***
-297
-***
-305
-()
-278
-()
-277
-***
-307
-()
-276
-***
-296
-()
-273
-()
-271
-()
-265
-()
-246
-***
-267
-()
-245
-***
-280
-()
-244
-***
-391
-()
-243
-***
-330
-()
-242
-***
-456
-()
-241
-***
-346
-()
-240
-***
-483
-()
-239
-***
-260
-()
-238
-***
-261
-()
-237
-***
-262
-***
-294
-()
-236
-***
-253
-()
-229
-***
-397
-()
-228
-***
-298
-()
-227
-***
-415
-()
-226
-***
-264
-()
-224
-***
-232
-()
-222
-***
-233
-()
-217
-***
-250
-()
-211
-***
-331
-()
-210
-***
-394
-()
-209
-***
-410
-()
-208
-***
-321
-()
-207
-***
-327
-()
-206
-***
-309
-()
-199
-***
-259
-()
-198
-***
-219
-()
-197
-***
-220
-()
-195
-***
-429
-()
-194
-***
-470
-()
-193
-***
-274
-()
-191
-***
-203
-()
-190
-***
-263
-()
-189
-215
-***
-230
-()
-188
-***
-266
-***
-295
-()
-182
-***
-329
-()
-181
-***
-351
-()
-180
-***
-441
-()
-179
-***
-453
-()
-178
-***
-418
-()
-177
-***
-353
-()
-176
-***
-422
-()
-175
-***
-225
-***
-255
-()
-174
-***
-269
-()
-173
-***
-214
-()
-172
-***
-186
-()
-171
-***
-447
-()
-170
-***
-270
-***
-306
-()
-169
-***
-336
-()
-168
-***
-285
-()
-165
-***
-249
-()
-146
-***
-154
-()
-143
-***
-334
-()
-142
-***
-216
-***
-257
-()
-141
-***
-167
-***
-251
-()
-140
-***
-162
-***
-293
-()
-139
-***
-158
-()
-137
-***
-166
-***
-201
-()
-136
-***
-160
-()
-134
-***
-221
-()
-132
-***
-213
-()
-131
-***
-187
-()
-129
-***
-235
-()
-128
-***
-153
-()
-127
-***
-156
-()
-126
-***
-159
-***
-218
-()
-125
-***
-155
-()
-124
-***
-157
-()
-123
-***
-152
-()
-116
-***
-135
-***
-163
-()
-115
-***
-133
-***
-204
-***
-248
-()
-114
-***
-192
-***
-212
-()
-113
-***
-268
-()
-112
-***
-367
-()
-111
-***
-272
-()
-110
-***
-434
-()
-109
-***
-323
-()
-108
-***
-281
-()
-107
-***
-144
-***
-148
-()
-106
-***
-275
-()
-105
-***
-196
-***
-254
-()
-104
-***
-138
-***
-161
-()
-103
-***
-310
-()
-102
-***
-223
-***
-252
-()
-80
-()
-70
-()
-69
-()
-68
-()
-66
-()
-64
-()
-62
-***
-256
-()
-61
-***
-93
-()
-59
-***
-120
-()
-58
-()
-57
-***
-183
-()
-55
-()
-54
-()
-52
-***
-147
-()
-51
-***
-118
-()
-50
-***
-83
-()
-49
-***
-98
-()
-48
-***
-99
-()
-47
-()
-46
-***
-184
-()
-45
-***
-121
-()
-44
-()
-43
-***
-88
-()
-42
-***
-122
-()
-41
-***
-91
-()
-40
-***
-96
-()
-38
-***
-100
-()
-37
-***
-149
-()
-36
-***
-74
-()
-35
-***
-258
-()
-34
-***
-151
-()
-33
-***
-85
-()
-32
-()
-31
-***
-94
-()
-30
-***
-97
-()
-29
-***
-90
-()
-28
-***
-89
-()
-27
-***
-92
-()
-26
-***
-72
-***
-247
-()
-25
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-86
-()
-24
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-82
-()
-23
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-87
-***
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-()
-22
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-76
-***
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-()
-21
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-84
-()
-20
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-78
-()
-19
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-73
-()
-18
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-81
-()
-17
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-65
-()
-16
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-63
-***
-101
-()
-15
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-71
-()
-14
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-75
-()
-13
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-322
-()
-12
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-77
-()
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-283
-()
-10
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-79
-()
-9
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-145
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-150
-()
-8
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-67
-()
-7
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-60
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-231
-()
-6
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-56
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-234
-()
-5
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-164
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-202
-()
-4
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-()
-3
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diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
deleted file mode 100755
index 1a4f96712..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
+++ /dev/null
@@ -1 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
deleted file mode 100755
index ea901fcca..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ /dev/null
@@ -1,27 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:12:31
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x5565040
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 147135976000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
deleted file mode 100644
index 7176a8af9..000000000
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ /dev/null
@@ -1,634 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.147041                       # Number of seconds simulated
-sim_ticks                                147041218500                       # Number of ticks simulated
-final_tick                               147041218500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 937429                       # Simulator instruction rate (inst/s)
-host_op_rate                                   942087                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1521808702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 442868                       # Number of bytes of host memory used
-host_seconds                                    96.62                       # Real time elapsed on the host
-sim_insts                                    90576861                       # Number of instructions simulated
-sim_ops                                      91026990                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             36992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            944768                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               981760                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        36992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           36992                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                578                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              14762                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15340                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               251576                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6425192                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6676767                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          251576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             251576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              251576                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6425192                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6676767                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                         0                       # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        294082437                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    90576861                       # Number of instructions committed
-system.cpu.committedOps                      91026990                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              72326352                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                      112245                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     72326352                       # number of integer instructions
-system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           124237033                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            339191618                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            53956115                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      27220755                       # number of memory refs
-system.cpu.num_load_insts                    22475911                       # Number of load instructions
-system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               294082436.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          18732304                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  63822828     70.09%     70.09% # Class of executed instruction
-system.cpu.op_class::IntMult                    10474      0.01%     70.10% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   6      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                 15      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               2      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.10% # Class of executed instruction
-system.cpu.op_class::MemRead                 22475911     24.68%     94.79% # Class of executed instruction
-system.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   91054080                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            942702                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3565.593939                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26253601                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            946798                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.728830                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       54410414000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3565.593939                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.870506                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.870506                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1355                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2550                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55347598                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55347598                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21556948                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21556948                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4688372                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          507                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           507                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26245320                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26245320                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26245827                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26245827                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       900187                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        900187                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        46609                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        46609                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       946796                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         946796                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       946799                       # number of overall misses
-system.cpu.dcache.overall_misses::total        946799                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11711364000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11711364000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1217183500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1217183500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  12928547500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  12928547500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  12928547500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  12928547500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22457135                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22457135                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          510                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          510                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27192116                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27192116                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27192626                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27192626                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040085                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040085                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005882                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.005882                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.034819                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.034819                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.034818                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.034818                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13655.050824                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13655.007557                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       942334                       # number of writebacks
-system.cpu.dcache.writebacks::total            942334                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900186                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       900186                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       946795                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       946795                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10361045000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10361045000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1147270000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1147270000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       118500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       118500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11508315000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11508315000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11508433500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11508433500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040085                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040085                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005882                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005882                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034819                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034819                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034818                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034818                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        39500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        39500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                 2                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.120572                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           107830172                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               599                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          180016.981636                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.120572                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.249082                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.249082                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          597                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          552                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.291504                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         215662141                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        215662141                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    107830172                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       107830172                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     107830172                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        107830172                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    107830172                       # number of overall hits
-system.cpu.icache.overall_hits::total       107830172                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          599                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           599                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          599                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            599                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          599                       # number of overall misses
-system.cpu.icache.overall_misses::total           599                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     32074000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     32074000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     32074000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     32074000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     32074000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     32074000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    107830771                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    107830771                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    107830771                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    107830771                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    107830771                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    107830771                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000006                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000006                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000006                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53545.909850                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53545.909850                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          599                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          599                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          599                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          599                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     31175500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     31175500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     31175500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     31175500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     31175500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     31175500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000006                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52045.909850                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         9567.852421                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1827177                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15323                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           119.244078                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8879.446344                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   495.172977                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   193.233100                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.270979                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.015111                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.005897                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.291988                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15323                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1468                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13704                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.467621                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15179780                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15179780                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           21                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       899975                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         899996                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       942334                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       942334                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        32061                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        32061                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           21                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       932036                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          932057                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           21                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       932036                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         932057                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          578                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          214                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          792                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        14548                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        14548                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          578                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        14762                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         15340                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          578                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        14762                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        15340                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     30356000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     11237000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     41593000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    764020500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    764020500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     30356000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    775257500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    805613500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     30356000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    775257500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    805613500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          599                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       900189                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       900788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       942334                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       942334                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        46609                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        46609                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          599                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       946798                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       947397                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          599                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       946798                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       947397                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.964942                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000238                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000879                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.312129                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.312129                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.964942                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.015591                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.016192                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.964942                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.015591                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.016192                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          578                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          214                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          792                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          578                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        14762                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15340                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          578                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        14762                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15340                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23409000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      8667000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     32076000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    589194000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    589194000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23409000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    597861000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    621270000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23409000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    597861000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    621270000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000238                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000879                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.312129                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.312129                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015591                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016192                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015591                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016192                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         900788                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        900788                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       942334                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        46609                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        46609                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1198                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2835930                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2837128                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        38336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120904448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          120942784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1889731                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            1889731    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1889731                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1887199500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        898500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1420197000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 792                       # Transaction distribution
-system.membus.trans_dist::ReadResp                792                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             14548                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            14548                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        30680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  30680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       981760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  981760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             15340                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   15340    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               15340                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            15603500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           76963500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
deleted file mode 100644
index 5a8877655..000000000
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,171 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
-gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
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diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
deleted file mode 100755
index 1a4f96712..000000000
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
+++ /dev/null
@@ -1 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
deleted file mode 100755
index a8897be0c..000000000
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 19:41:52
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 122215823500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
deleted file mode 100644
index c1c851704..000000000
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,124 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.122216                       # Number of seconds simulated
-sim_ticks                                122215823500                       # Number of ticks simulated
-final_tick                               122215823500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2069444                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2069529                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1037295392                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 412436                       # Number of bytes of host memory used
-host_seconds                                   117.82                       # Real time elapsed on the host
-sim_insts                                   243825150                       # Number of instructions simulated
-sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         977685992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         328674008                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1306360000                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    977685992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       977685992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data       91606089                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          91606089                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          244421498                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           82220433                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             326641931                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          22901951                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             22901951                       # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data               3886                       # Number of other requests responded to by this memory
-system.physmem.num_other::total                  3886                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7999667834                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2689291768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10688959601                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7999667834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7999667834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           749543606                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              749543606                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7999667834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3438835373                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11438503207                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq           326641931                       # Transaction distribution
-system.membus.trans_dist::ReadResp          326641931                       # Transaction distribution
-system.membus.trans_dist::WriteReq           22901951                       # Transaction distribution
-system.membus.trans_dist::WriteResp          22901951                       # Transaction distribution
-system.membus.trans_dist::SwapReq                3886                       # Transaction distribution
-system.membus.trans_dist::SwapResp               3886                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    488842996                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    210252540                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              699095536                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    977685992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    420311185                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              1397997177                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         349547768                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.699251                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.458584                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0               105126270     30.07%     30.07% # Request fanout histogram
-system.membus.snoop_fanout::1               244421498     69.93%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total           349547768                       # Request fanout histogram
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        244431648                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   243825150                       # Number of instructions committed
-system.cpu.committedOps                     243835265                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             194726494                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
-system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18619959                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    194726494                       # number of integer instructions
-system.cpu.num_fp_insts                         11630                       # number of float instructions
-system.cpu.num_int_register_reads           456818988                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          215451554                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     105711441                       # number of memory refs
-system.cpu.num_load_insts                    82803521                       # Number of load instructions
-system.cpu.num_store_insts                   22907920                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               244431647.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          29302884                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              28877736     11.81%     11.81% # Class of executed instruction
-system.cpu.op_class::IntAlu                 109842388     44.94%     56.75% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatAdd                      42      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     56.75% # Class of executed instruction
-system.cpu.op_class::MemRead                 82803527     33.88%     90.63% # Class of executed instruction
-system.cpu.op_class::MemWrite                22907920      9.37%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  244431613                       # Class of executed instruction
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
deleted file mode 100644
index 519142696..000000000
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,207 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=apic_clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.membus.slave[5]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
-gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
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-116
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-114
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-196
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-70
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-69
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-120
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-55
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-54
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-52
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-26
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-25
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-23
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-22
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-21
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-16
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-7
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-164
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-4
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-3
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diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
deleted file mode 100755
index 1a4f96712..000000000
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ /dev/null
@@ -1 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
deleted file mode 100755
index ea41249d4..000000000
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 20:16:46
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 168950040000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
deleted file mode 100644
index 844bb352a..000000000
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,129 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.168950                       # Number of seconds simulated
-sim_ticks                                168950040000                       # Number of ticks simulated
-final_tick                               168950040000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1180838                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2079266                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1262766288                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 436624                       # Number of bytes of host memory used
-host_seconds                                   133.79                       # Real time elapsed on the host
-sim_insts                                   157988548                       # Number of instructions simulated
-sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst        1741569312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         717246013                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           2458815325                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   1741569312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1741569312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data      243173117                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         243173117                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          217696164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           90779447                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             308475611                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data          31439752                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             31439752                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst          10308191179                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           4245314254                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             14553505433                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst     10308191179                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total        10308191179                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1439319677                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1439319677                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst         10308191179                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          5684633931                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            15992825110                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq           308475611                       # Transaction distribution
-system.membus.trans_dist::ReadResp          308475611                       # Transaction distribution
-system.membus.trans_dist::WriteReq           31439752                       # Transaction distribution
-system.membus.trans_dist::WriteResp          31439752                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    435392328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total    435392328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    244438398                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total    244438398                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              679830726                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1741569312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total   1741569312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    960419130                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total    960419130                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              2701988442                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         339915363                       # Request fanout histogram
-system.membus.snoop_fanout::mean             2.640442                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.479871                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2               122219199     35.96%     35.96% # Request fanout histogram
-system.membus.snoop_fanout::3               217696164     64.04%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               3                       # Request fanout histogram
-system.membus.snoop_fanout::total           339915363                       # Request fanout histogram
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        337900081                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   157988548                       # Number of instructions committed
-system.cpu.committedOps                     278192465                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             278169482                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
-system.cpu.num_func_calls                     8475189                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18628007                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    278169482                       # number of integer instructions
-system.cpu.num_fp_insts                            40                       # number of float instructions
-system.cpu.num_int_register_reads           635379407                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          217447860                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            104140596                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            61764861                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     122219137                       # number of memory refs
-system.cpu.num_load_insts                    90779385                       # Number of load instructions
-system.cpu.num_store_insts                   31439752                       # Number of store instructions
-system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               337900080.998000                       # Number of busy cycles
-system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
-system.cpu.Branches                          29309705                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                 16695      0.01%      0.01% # Class of executed instruction
-system.cpu.op_class::IntAlu                 155945354     56.06%     56.06% # Class of executed instruction
-system.cpu.op_class::IntMult                    10938      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::IntDiv                       329      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd                      12      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     56.07% # Class of executed instruction
-system.cpu.op_class::MemRead                 90779385     32.63%     88.70% # Class of executed instruction
-system.cpu.op_class::MemWrite                31439752     11.30%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  278192465                       # Class of executed instruction
-
----------- End Simulation Statistics   ----------