diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
| commit | 73e9e923d00c6f5df9e79a6c40ecc159894d2bc5 (patch) | |
| tree | f84188c6697fe79f0521b73d9d38855ce7e04d29 /tests/long/se/10.mcf | |
| parent | dd1b346584e520ba970e62aa3bcc7d32828cdeba (diff) | |
| download | gem5-73e9e923d00c6f5df9e79a6c40ecc159894d2bc5.tar.xz | |
stats: Update stats for syscall emulation Linux kernel changes.
Diffstat (limited to 'tests/long/se/10.mcf')
15 files changed, 719 insertions, 723 deletions
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index a0039b696..771a85baa 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -99,8 +99,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout index c071d26fa..fddfdedb3 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:53:37 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:50 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 122215830000 because target called exit() +Exiting @ tick 122215823500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 804f585d6..7dd162db7 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.122216 # Number of seconds simulated -sim_ticks 122215830000 # Number of ticks simulated -final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 122215823500 # Number of ticks simulated +final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2951739 # Simulator instruction rate (inst/s) -host_op_rate 2951861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1479540198 # Simulator tick rate (ticks/s) -host_mem_usage 346528 # Number of bytes of host memory used -host_seconds 82.60 # Real time elapsed on the host -sim_insts 243825163 # Number of instructions simulated -sim_ops 243835278 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 977686044 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 328674009 # Number of bytes read from this memory -system.physmem.bytes_read::total 1306360053 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 977686044 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977686044 # Number of instructions bytes read from this memory +host_inst_rate 2900370 # Simulator instruction rate (inst/s) +host_op_rate 2900489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1453791405 # Simulator tick rate (ticks/s) +host_mem_usage 355144 # Number of bytes of host memory used +host_seconds 84.07 # Real time elapsed on the host +sim_insts 243825150 # Number of instructions simulated +sim_ops 243835265 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory +system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 244421511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82220434 # Number of read requests responded to by this memory -system.physmem.num_reads::total 326641945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory +system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory system.physmem.num_other::total 3886 # Number of other requests responded to by this memory system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2689291633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10688959466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 749543566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 749543566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3438835198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11438503032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 244431661 # number of cpu cycles simulated +system.cpu.numCycles 244431648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825163 # Number of instructions committed -system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses +system.cpu.committedInsts 243825150 # Number of instructions committed +system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726506 # number of integer instructions +system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls +system.cpu.num_int_insts 194726494 # number of integer instructions system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451567 # number of times the integer registers were written +system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711442 # number of memory refs -system.cpu.num_load_insts 82803522 # Number of load instructions +system.cpu.num_mem_refs 105711441 # number of memory refs +system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 244431661 # Number of busy cycles +system.cpu.num_busy_cycles 244431648 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index 2ba8ced6e..22dd9c24e 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index f34d81d26..869cdf524 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 12:31:43 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:15:25 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 362481577000 because target called exit() +Exiting @ tick 362481563000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 5f77178bc..44702e46f 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.362482 # Number of seconds simulated -sim_ticks 362481577000 # Number of ticks simulated -final_tick 362481577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 362481563000 # Number of ticks simulated +final_tick 362481563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1217197 # Simulator instruction rate (inst/s) -host_op_rate 1217247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1809539933 # Simulator tick rate (ticks/s) -host_mem_usage 354248 # Number of bytes of host memory used -host_seconds 200.32 # Real time elapsed on the host -sim_insts 243825163 # Number of instructions simulated -sim_ops 243835278 # Number of ops (including micro ops) simulated +host_inst_rate 1415125 # Simulator instruction rate (inst/s) +host_op_rate 1415183 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2103788292 # Simulator tick rate (ticks/s) +host_mem_usage 363728 # Number of bytes of host memory used +host_seconds 172.30 # Real time elapsed on the host +sim_insts 243825150 # Number of instructions simulated +sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory system.physmem.bytes_read::total 998592 # Number of bytes read from this memory @@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst 155197 # To system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 724963154 # number of cpu cycles simulated +system.cpu.numCycles 724963126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825163 # Number of instructions committed -system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses +system.cpu.committedInsts 243825150 # Number of instructions committed +system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726506 # number of integer instructions +system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls +system.cpu.num_int_insts 194726494 # number of integer instructions system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written +system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711442 # number of memory refs -system.cpu.num_load_insts 82803522 # Number of load instructions +system.cpu.num_mem_refs 105711441 # number of memory refs +system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 724963154 # Number of busy cycles +system.cpu.num_busy_cycles 724963126 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 725.564686 # Cycle average of tags in use -system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 725.564713 # Cycle average of tags in use +system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 725.564686 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 725.564713 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits -system.cpu.icache.overall_hits::total 244420630 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits +system.cpu.icache.overall_hits::total 244420617 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses @@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 49333000 system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses @@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3563.804804 # Cycle average of tags in use -system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3563.804941 # Cycle average of tags in use +system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134384281000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3563.804804 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 134384267000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3563.804941 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits -system.cpu.dcache.overall_hits::total 104182818 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits +system.cpu.dcache.overall_hits::total 104182817 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses @@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses @@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9744.633089 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 9744.633464 # Cycle average of tags in use system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8861.504688 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 738.799807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 144.328594 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 8861.505031 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 738.799835 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 144.328599 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 02825e2f4..c43765666 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr @@ -533,7 +533,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index dec2c9148..29d21ef45 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 13:12:36 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:35:52 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,6 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -info: Increasing stack size by one page. -info: Increasing stack size by one page. -Exiting @ tick 68340167000 because target called exit() +Exiting @ tick 68408131000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 4e7a26f12..740e607ea 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068340 # Number of seconds simulated -sim_ticks 68340167000 # Number of ticks simulated -final_tick 68340167000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068408 # Number of seconds simulated +sim_ticks 68408131000 # Number of ticks simulated +final_tick 68408131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107513 # Simulator instruction rate (inst/s) -host_op_rate 189313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46506224 # Simulator tick rate (ticks/s) -host_mem_usage 365660 # Number of bytes of host memory used -host_seconds 1469.48 # Real time elapsed on the host -sim_insts 157988582 # Number of instructions simulated -sim_ops 278192519 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 68608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1893120 # Number of bytes read from this memory -system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 68608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 68608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory -system.physmem.bytes_written::total 20288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1072 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29580 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory -system.physmem.num_writes::total 317 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1003919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 27701425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 28705344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1003919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1003919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 296868 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 296868 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 296868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1003919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 27701425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29002212 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 92617 # Simulator instruction rate (inst/s) +host_op_rate 163083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40102422 # Simulator tick rate (ticks/s) +host_mem_usage 370556 # Number of bytes of host memory used +host_seconds 1705.84 # Real time elapsed on the host +sim_insts 157988547 # Number of instructions simulated +sim_ops 278192462 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1892736 # Number of bytes read from this memory +system.physmem.bytes_read::total 1961088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20352 # Number of bytes written to this memory +system.physmem.bytes_written::total 20352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29574 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30642 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 318 # Number of write requests responded to by this memory +system.physmem.num_writes::total 318 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 999179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 27668290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 28667469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 999179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 999179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 297508 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 297508 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 297508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 999179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 27668290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 28964978 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 136680335 # number of cpu cycles simulated +system.cpu.numCycles 136816263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 36129289 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 36129289 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1086629 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25668657 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25566381 # Number of BTB hits +system.cpu.BPredUnit.lookups 36128371 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 36128371 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1086051 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25676514 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25568930 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28038648 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 196448149 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36129289 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25566381 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59446336 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8437809 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 41835148 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 182 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27320717 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 151811 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136641889 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.527241 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.343736 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28040484 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 196465722 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36128371 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25568930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59455138 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8440333 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 41957570 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27323760 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 153045 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136778320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.524833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.343005 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79944033 58.51% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2167208 1.59% 60.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2997757 2.19% 62.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4111297 3.01% 65.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8027988 5.88% 71.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5053640 3.70% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2897429 2.12% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1474644 1.08% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29967893 21.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 80075177 58.54% 58.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2168654 1.59% 60.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2999031 2.19% 62.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4111689 3.01% 65.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8029506 5.87% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5053851 3.69% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2898853 2.12% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1472297 1.08% 78.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29969262 21.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136641889 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.264334 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.437282 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40756149 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 32464330 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46271327 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9828540 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7321543 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 341364323 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7321543 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46061495 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6368629 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8995 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50367831 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26513396 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 337564097 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5026 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 24245573 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 73928 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 414895608 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1010438546 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1010435932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2614 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 341010940 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 73884668 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 483 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 475 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57387793 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 108215751 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37227533 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 46388866 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7855106 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 331925513 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2461 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 311467723 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186069 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53480941 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 93052835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2015 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136641889 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.279445 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.722907 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 136778320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.264065 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.435982 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40775641 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 32574420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46270758 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9832617 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7324884 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 341365831 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7324884 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46092133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6411510 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9224 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50365166 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 26575403 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 337580749 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5005 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 24325640 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 73870 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 414916926 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1010481124 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1010477953 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3171 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 341010848 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 73906078 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 481 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57495301 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 108229908 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37227556 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 46399442 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8017088 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 331952532 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2380 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 311468511 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188619 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53509766 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 93151802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1934 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136778320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.277177 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.722818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29493706 21.58% 21.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18268502 13.37% 34.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26067174 19.08% 54.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31248056 22.87% 76.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 17426975 12.75% 89.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8824728 6.46% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3769643 2.76% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1473533 1.08% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 69572 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29621399 21.66% 21.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18208303 13.31% 34.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26183268 19.14% 54.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31189173 22.80% 76.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 17472478 12.77% 89.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8789771 6.43% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3781191 2.76% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1461656 1.07% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 71081 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136641889 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136778320 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 22788 1.09% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 22736 1.09% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available @@ -160,15 +160,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1944579 92.77% 93.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 128653 6.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1942986 92.77% 93.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 128630 6.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 29247 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177257579 56.91% 56.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177262228 56.91% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 56.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 143 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.92% # Type of FU issued @@ -194,159 +194,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99693088 32.01% 88.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34487693 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99693377 32.01% 88.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34483516 11.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 311467723 # Type of FU issued -system.cpu.iq.rate 2.278804 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2096020 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006729 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 761858485 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 385440526 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 308377955 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 939 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1362 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 313534078 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 418 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52563213 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 311468511 # Type of FU issued +system.cpu.iq.rate 2.276546 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2094352 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006724 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 761997211 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 385495678 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 308386892 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1102 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1693 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 371 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 313533109 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 507 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52559129 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17436363 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 94862 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33518 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5787782 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17450524 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 94828 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33225 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5787805 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3294 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 766 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3313 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7321543 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 823106 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 106434 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 331927974 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 49382 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 108215751 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37227533 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1169 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29139 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33518 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 614396 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578149 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1192545 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 309546199 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 99164124 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1921524 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7324884 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 821379 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 106718 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 331954912 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 49233 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 108229908 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37227556 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1080 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29147 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33225 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 614391 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 577456 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1191847 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 309549319 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 99164391 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1919192 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 133270548 # number of memory reference insts executed -system.cpu.iew.exec_branches 31554842 # Number of branches executed -system.cpu.iew.exec_stores 34106424 # Number of stores executed -system.cpu.iew.exec_rate 2.264746 # Inst execution rate -system.cpu.iew.wb_sent 308908711 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 308378251 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227159905 # num instructions producing a value -system.cpu.iew.wb_consumers 466461304 # num instructions consuming a value +system.cpu.iew.exec_refs 133267604 # number of memory reference insts executed +system.cpu.iew.exec_branches 31551799 # Number of branches executed +system.cpu.iew.exec_stores 34103213 # Number of stores executed +system.cpu.iew.exec_rate 2.262518 # Inst execution rate +system.cpu.iew.wb_sent 308913193 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 308387263 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227149501 # num instructions producing a value +system.cpu.iew.wb_consumers 466434365 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.256201 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.486986 # average fanout of values written-back +system.cpu.iew.wb_rate 2.254025 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.486991 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions -system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 53739498 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 157988547 # The number of committed instructions +system.cpu.commit.commitCommittedOps 278192462 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 53766564 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1086653 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 129320346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.151189 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.664667 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1086077 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 129453436 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.148977 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.662392 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48978430 37.87% 37.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24328173 18.81% 56.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 16731567 12.94% 69.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12545678 9.70% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3454921 2.67% 82.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3553253 2.75% 84.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2757236 2.13% 86.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1133891 0.88% 87.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15837197 12.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48953386 37.82% 37.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24330343 18.79% 56.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17047293 13.17% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12542277 9.69% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3298814 2.55% 82.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3552746 2.74% 84.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2756547 2.13% 86.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1133806 0.88% 87.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15838224 12.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 129320346 # Number of insts commited each cycle -system.cpu.commit.committedInsts 157988582 # Number of instructions committed -system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 129453436 # Number of insts commited each cycle +system.cpu.commit.committedInsts 157988547 # Number of instructions committed +system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 122219139 # Number of memory references committed -system.cpu.commit.loads 90779388 # Number of loads committed +system.cpu.commit.refs 122219135 # Number of memory references committed +system.cpu.commit.loads 90779384 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 29309710 # Number of branches committed +system.cpu.commit.branches 29309705 # Number of branches committed system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. +system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15837197 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15838224 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 445415166 # The number of ROB reads -system.cpu.rob.rob_writes 671194708 # The number of ROB writes -system.cpu.timesIdled 2012 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38446 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 157988582 # Number of Instructions Simulated -system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated -system.cpu.cpi 0.865128 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.865128 # CPI: Total CPI of All Threads -system.cpu.ipc 1.155898 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.155898 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 705405399 # number of integer regfile reads -system.cpu.int_regfile_writes 373270395 # number of integer regfile writes -system.cpu.fp_regfile_reads 345 # number of floating regfile reads -system.cpu.fp_regfile_writes 188 # number of floating regfile writes -system.cpu.misc_regfile_reads 197984504 # number of misc regfile reads -system.cpu.icache.replacements 90 # number of replacements -system.cpu.icache.tagsinuse 845.686115 # Cycle average of tags in use -system.cpu.icache.total_refs 27319306 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1079 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25319.097312 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 445574238 # The number of ROB reads +system.cpu.rob.rob_writes 671251501 # The number of ROB writes +system.cpu.timesIdled 1985 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37943 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 157988547 # Number of Instructions Simulated +system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated +system.cpu.cpi 0.865988 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.865988 # CPI: Total CPI of All Threads +system.cpu.ipc 1.154750 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.154750 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 705392602 # number of integer regfile reads +system.cpu.int_regfile_writes 373276329 # number of integer regfile writes +system.cpu.fp_regfile_reads 441 # number of floating regfile reads +system.cpu.fp_regfile_writes 230 # number of floating regfile writes +system.cpu.misc_regfile_reads 197984249 # number of misc regfile reads +system.cpu.icache.replacements 87 # number of replacements +system.cpu.icache.tagsinuse 844.199846 # Cycle average of tags in use +system.cpu.icache.total_refs 27322358 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25392.526022 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 845.686115 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.412933 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.412933 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27319307 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27319307 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27319307 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27319307 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27319307 # number of overall hits -system.cpu.icache.overall_hits::total 27319307 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1410 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1410 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1410 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1410 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1410 # number of overall misses -system.cpu.icache.overall_misses::total 1410 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52106500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52106500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52106500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52106500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52106500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52106500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27320717 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27320717 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27320717 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27320717 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27320717 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27320717 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36954.964539 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36954.964539 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36954.964539 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36954.964539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36954.964539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36954.964539 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 844.199846 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.412207 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.412207 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27322358 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27322358 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27322358 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27322358 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27322358 # number of overall hits +system.cpu.icache.overall_hits::total 27322358 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1402 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1402 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1402 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1402 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1402 # number of overall misses +system.cpu.icache.overall_misses::total 1402 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51713500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51713500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51713500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51713500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51713500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51713500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27323760 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27323760 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27323760 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27323760 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27323760 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27323760 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36885.520685 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36885.520685 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36885.520685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36885.520685 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1082 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1082 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39682000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39682000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39682000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39682000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39682000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39682000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36674.676525 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36674.676525 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36674.676525 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36674.676525 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36674.676525 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36674.676525 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 325 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39505500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39505500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39505500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39505500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39505500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36681.058496 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36681.058496 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072150 # number of replacements -system.cpu.dcache.tagsinuse 4072.380318 # Cycle average of tags in use -system.cpu.dcache.total_refs 75593684 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076246 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36.408828 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22734551000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.380318 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994233 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994233 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 44236411 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 44236411 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31357262 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31357262 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 75593673 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 75593673 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 75593673 # number of overall hits -system.cpu.dcache.overall_hits::total 75593673 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2315078 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2315078 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 82489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 82489 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2397567 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2397567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2397567 # number of overall misses -system.cpu.dcache.overall_misses::total 2397567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16784018500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16784018500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571310000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1571310000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18355328500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18355328500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18355328500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18355328500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46551489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46551489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072121 # number of replacements +system.cpu.dcache.tagsinuse 4072.371520 # Cycle average of tags in use +system.cpu.dcache.total_refs 75597840 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076217 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36.411339 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 22802887000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.371520 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994231 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994231 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 44240568 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 44240568 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31357263 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31357263 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 75597831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 75597831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 75597831 # number of overall hits +system.cpu.dcache.overall_hits::total 75597831 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2315103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2315103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 82488 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 82488 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2397591 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2397591 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2397591 # number of overall misses +system.cpu.dcache.overall_misses::total 2397591 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16770812000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16770812000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571570000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1571570000 # 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number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77991240 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049732 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049732 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 77995422 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77995422 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77995422 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77995422 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049728 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049728 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.030741 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.030741 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.030741 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.030741 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7249.871711 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7249.871711 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19048.721648 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19048.721648 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7655.814624 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7655.814624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7655.814624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7655.814624 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.030740 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.030740 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.030740 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.030740 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7244.088924 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7244.088924 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19052.104549 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19052.104549 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7650.338194 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7650.338194 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,140 +451,138 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2064802 # number of writebacks -system.cpu.dcache.writebacks::total 2064802 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320846 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 320846 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2065063 # number of writebacks +system.cpu.dcache.writebacks::total 2065063 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320901 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 320901 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 469 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 469 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 321315 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 321315 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 321315 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 321315 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82020 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82020 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076252 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076252 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076252 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076252 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6184007000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6184007000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1313707000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1313707000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7497714000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7497714000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497714000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7497714000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042839 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 321370 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 321370 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 321370 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 321370 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994202 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82019 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82019 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076221 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076221 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076221 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076221 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6183631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6183631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1313937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1313937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7497568000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7497568000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497568000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7497568000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042835 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042835 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026622 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026622 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.946630 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.946630 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16016.910510 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16016.910510 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.177256 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.177256 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.177256 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.177256 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026620 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026620 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.804733 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.804733 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16019.910021 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16019.910021 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 233.440777 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.597809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.008019 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007124 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.612953 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993528 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993535 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2064802 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2064802 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.occ_blocks::writebacks 19572.608886 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 263.032470 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 232.337716 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.597309 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.008027 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007090 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.612426 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993505 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993513 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2065063 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2065063 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 53141 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 53141 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046669 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2046676 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046669 # number of overall hits -system.cpu.l2cache.overall_hits::total 2046676 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 588 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1660 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses +system.cpu.l2cache.demand_hits::cpu.inst 8 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1048370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 38191500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1010179000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1048370500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1079 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1994116 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995195 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2064802 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2064802 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29574 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30642 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29574 # number of overall misses +system.cpu.l2cache.overall_misses::total 30642 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37986000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20700500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 58686500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 989313000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 989313000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37986000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1010013500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1047999500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37986000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1010013500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1047999500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994087 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995163 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2065063 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2065063 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 82133 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 82133 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1079 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076249 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077328 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076249 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993513 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000832 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076220 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000292 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000827 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352988 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.352988 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993513 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014247 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993513 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014247 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35626.399254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35507.653061 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35584.337349 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.223648 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.223648 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35626.399254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.743746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34202.352212 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.399254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.743746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34202.352212 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014244 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014751 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014244 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014751 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35567.415730 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35567.869416 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35567.575758 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.654801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.654801 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34201.406566 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34201.406566 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,60 +591,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks -system.cpu.l2cache.writebacks::total 317 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1072 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1660 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 318 # number of writebacks +system.cpu.l2cache.writebacks::total 318 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 582 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1650 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28992 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 28992 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1072 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29580 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1072 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29580 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34797000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19023000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53820000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899044500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899044500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34797000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918067500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 952864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34797000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918067500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 952864500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000832 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29574 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30642 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29574 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30642 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34610000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18859500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53469500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34610000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 917904500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 952514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34610000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 917904500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 952514500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000827 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352988 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352988 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32459.888060 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32352.040816 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32421.686747 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014751 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014751 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32406.367041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32404.639175 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32405.757576 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.088990 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.088990 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32459.888060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31036.764706 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31086.535952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32459.888060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31036.764706 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31086.535952 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.106236 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.106236 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 3fd88efc2..2bc190729 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 9f1b85cdf..36c1a507a 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:20:09 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:40:35 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 168950072000 because target called exit() +Exiting @ tick 168950039000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 75d2c32b9..624b796e9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.168950 # Number of seconds simulated -sim_ticks 168950072000 # Number of ticks simulated -final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 168950039000 # Number of ticks simulated +final_tick 168950039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1244063 # Simulator instruction rate (inst/s) -host_op_rate 2190595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1330377575 # Simulator tick rate (ticks/s) -host_mem_usage 351912 # Number of bytes of host memory used -host_seconds 126.99 # Real time elapsed on the host -sim_insts 157988583 # Number of instructions simulated -sim_ops 278192520 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 1741569664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 717246015 # Number of bytes read from this memory -system.physmem.bytes_read::total 2458815679 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1741569664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1741569664 # Number of instructions bytes read from this memory +host_inst_rate 1227990 # Simulator instruction rate (inst/s) +host_op_rate 2162293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1313189467 # Simulator tick rate (ticks/s) +host_mem_usage 359036 # Number of bytes of host memory used +host_seconds 128.66 # Real time elapsed on the host +sim_insts 157988548 # Number of instructions simulated +sim_ops 278192463 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 717246011 # Number of bytes read from this memory +system.physmem.bytes_read::total 2458815323 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 217696208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90779450 # Number of read requests responded to by this memory -system.physmem.num_reads::total 308475658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90779446 # Number of read requests responded to by this memory +system.physmem.num_reads::total 308475610 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10308191310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4245313462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14553504772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10308191310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10308191310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1439319393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1439319393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10308191310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5684632854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15992824164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10308191240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4245314267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14553505507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10308191240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10308191240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1439319674 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1439319674 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10308191240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5684633941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15992825181 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 337900145 # number of cpu cycles simulated +system.cpu.numCycles 337900079 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988583 # Number of instructions committed -system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.committedInsts 157988548 # Number of instructions committed +system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls +system.cpu.num_int_insts 278186171 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read -system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written +system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read +system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_mem_refs 122219139 # number of memory refs -system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_mem_refs 122219135 # number of memory refs +system.cpu.num_load_insts 90779384 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 337900145 # Number of busy cycles +system.cpu.num_busy_cycles 337900079 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 44c2b2c0a..fb9534d75 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 85144f91b..25187946e 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 13:28:56 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:42:54 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 368209254000 because target called exit() +Exiting @ tick 368209206000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index cca34d6d0..be2824a9d 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.368209 # Number of seconds simulated -sim_ticks 368209254000 # Number of ticks simulated -final_tick 368209254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 368209206000 # Number of ticks simulated +final_tick 368209206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 606195 # Simulator instruction rate (inst/s) -host_op_rate 1067413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1412802854 # Simulator tick rate (ticks/s) -host_mem_usage 363612 # Number of bytes of host memory used -host_seconds 260.62 # Real time elapsed on the host -sim_insts 157988583 # Number of instructions simulated -sim_ops 278192520 # Number of ops (including micro ops) simulated +host_inst_rate 651126 # Simulator instruction rate (inst/s) +host_op_rate 1146527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1517517563 # Simulator tick rate (ticks/s) +host_mem_usage 367484 # Number of bytes of host memory used +host_seconds 242.64 # Real time elapsed on the host +sim_insts 157988548 # Number of instructions simulated +sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory @@ -24,54 +24,54 @@ system.physmem.num_reads::total 30178 # Nu system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory system.physmem.num_writes::total 227 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5104923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5245365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5104924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5245366 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5104923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5284821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5104924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5284822 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 736418508 # number of cpu cycles simulated +system.cpu.numCycles 736418412 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988583 # Number of instructions committed -system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.committedInsts 157988548 # Number of instructions committed +system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls +system.cpu.num_int_insts 278186171 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read -system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written +system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read +system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_mem_refs 122219139 # number of memory refs -system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_mem_refs 122219135 # number of memory refs +system.cpu.num_load_insts 90779384 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 736418508 # Number of busy cycles +system.cpu.num_busy_cycles 736418412 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.897663 # Cycle average of tags in use -system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 665.897748 # Cycle average of tags in use +system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.897663 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 665.897748 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits -system.cpu.icache.overall_hits::total 217695401 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits +system.cpu.icache.overall_hits::total 217695357 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 45336000 system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891 system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.463091 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4076.463619 # Cycle average of tags in use +system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126234114000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.463091 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126234066000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.463619 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.995230 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.995230 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits -system.cpu.dcache.overall_hits::total 120152372 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits +system.cpu.dcache.overall_hits::total 120152368 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 30195678000 system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 19722.096664 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19722.099231 # Cycle average of tags in use system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19370.042647 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 209.723692 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 142.330324 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 19370.045173 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 209.723718 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 142.330341 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.591127 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.006400 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy |