diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/long/se/10.mcf | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/long/se/10.mcf')
5 files changed, 1156 insertions, 1151 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 3c2994f97..c6185ffda 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:268435455 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index f91e94134..276747f08 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:55:20 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 01:31:22 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 26773408500 because target called exit() +Exiting @ tick 26780899500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index e47377a85..b4108b98d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026786 # Number of seconds simulated -sim_ticks 26785824500 # Number of ticks simulated -final_tick 26785824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026781 # Number of seconds simulated +sim_ticks 26780899500 # Number of ticks simulated +final_tick 26780899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121944 # Simulator instruction rate (inst/s) -host_op_rate 122819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36056613 # Simulator tick rate (ticks/s) -host_mem_usage 374016 # Number of bytes of host memory used -host_seconds 742.88 # Real time elapsed on the host +host_inst_rate 55932 # Simulator instruction rate (inst/s) +host_op_rate 56334 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16535050 # Simulator tick rate (ticks/s) +host_mem_usage 421208 # Number of bytes of host memory used +host_seconds 1619.64 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory -system.physmem.bytes_read::total 992832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::total 992640 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15513 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1679694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35385881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37065575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1679694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1679694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1679694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35385881 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37065575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15513 # Total number of read requests seen +system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1680003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35385219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37065223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1680003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1680003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1680003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35385219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37065223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15510 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15516 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 992832 # Total number of bytes read from memory +system.physmem.cpureqs 15513 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992640 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992832 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992640 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 998 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1010 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 999 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26785652500 # Total gap between requests +system.physmem.totGap 26780729500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15513 # Categorize read packet sizes +system.physmem.readPktSize::6 15510 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 10163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 55611750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 315006750 # Sum of mem lat for all requests -system.physmem.totBusLat 77565000 # Total cycles spent in databus access -system.physmem.totBankLat 181830000 # Total cycles spent in bank access -system.physmem.avgQLat 3584.85 # Average queueing delay per request -system.physmem.avgBankLat 11721.14 # Average bank access latency per request +system.physmem.totQLat 54693250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 313977000 # Sum of mem lat for all requests +system.physmem.totBusLat 77550000 # Total cycles spent in databus access +system.physmem.totBankLat 181733750 # Total cycles spent in bank access +system.physmem.avgQLat 3526.32 # Average queueing delay per request +system.physmem.avgBankLat 11717.20 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20305.99 # Average memory access latency +system.physmem.avgMemAccLat 20243.52 # Average memory access latency system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s @@ -165,20 +165,20 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 14781 # Number of row buffer hits during reads +system.physmem.readRowHits 14776 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.28 # Row buffer hit rate for reads +system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1726658.45 # Average gap between requests -system.cpu.branchPred.lookups 26682480 # Number of BP lookups -system.cpu.branchPred.condPredicted 22002618 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 841998 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11368270 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11282813 # Number of BTB hits +system.physmem.avgGap 1726675.02 # Average gap between requests +system.cpu.branchPred.lookups 26686067 # Number of BP lookups +system.cpu.branchPred.condPredicted 22003641 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 842721 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11370784 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11281397 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.248285 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69658 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 194 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.213889 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70454 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -222,239 +222,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53571650 # number of cpu cycles simulated +system.cpu.numCycles 53561800 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14170612 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127882618 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26682480 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11352471 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24034762 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4762849 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11235788 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14175164 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127899633 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26686067 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11351851 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24037657 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4765030 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11217249 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13843090 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329835 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53345786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.413719 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215837 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13847383 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 331199 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53336140 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.414591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216158 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29349323 55.02% 55.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389433 6.35% 61.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028287 3.80% 65.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1555177 2.92% 68.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1667492 3.13% 71.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2918592 5.47% 76.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1510888 2.83% 79.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090794 2.04% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9835800 18.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29336778 55.00% 55.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3388806 6.35% 61.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028790 3.80% 65.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1556293 2.92% 68.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1665637 3.12% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2919109 5.47% 76.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1511505 2.83% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1091219 2.05% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9838003 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53345786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498071 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.387132 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16933018 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9083258 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22434897 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 998703 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3895910 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442085 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8696 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126062223 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42630 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3895910 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18712984 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3548131 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 156179 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21551652 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5480930 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123149853 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 423091 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4597179 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1286 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143608098 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536423645 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536418417 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5228 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53336140 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498229 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.387889 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16937190 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9066542 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22437695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 997386 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3897327 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4443416 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8715 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126080182 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42547 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3897327 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18717098 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3539811 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 156330 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21553550 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5472024 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123163469 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 421860 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4589739 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1294 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143620029 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536487458 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536482847 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4611 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36193912 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4607 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4605 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12518412 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29475899 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5522776 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2125822 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1253238 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118167784 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 36205843 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12496499 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29481175 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5524207 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2105622 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1304065 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118177785 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105151160 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 77497 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26739027 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65605268 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 105170475 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79267 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26750487 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65594281 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53345786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.971124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.910487 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 53336140 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.971843 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.910853 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15316861 28.71% 28.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11639595 21.82% 50.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8263506 15.49% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6760248 12.67% 78.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4974624 9.33% 88.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2955128 5.54% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2464546 4.62% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 527827 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443451 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15308492 28.70% 28.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11622242 21.79% 50.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8283131 15.53% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6774123 12.70% 78.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4939733 9.26% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2964995 5.56% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2471425 4.63% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 528847 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 443152 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53345786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53336140 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 44563 6.73% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340033 51.38% 58.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277229 41.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45613 6.89% 6.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340087 51.41% 58.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275830 41.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74420309 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 155 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 201 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25602989 24.35% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5116524 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74428958 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 145 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 185 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25611753 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5118456 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105151160 # Type of FU issued -system.cpu.iq.rate 1.962814 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661852 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006294 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264386671 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144919691 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102682625 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 784 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 339 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105812622 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 390 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 443741 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105170475 # Type of FU issued +system.cpu.iq.rate 1.963535 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661557 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264417181 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144941243 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102695992 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 733 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 321 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105831667 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 444874 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6901933 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6293 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 777932 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6907209 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6633 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6354 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 779363 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31373 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31305 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3895910 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 928973 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127070 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118188976 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309212 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29475899 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5522776 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 3897327 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 927642 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126590 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118198971 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309734 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29481175 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5524207 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66075 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6911 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446439 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445443 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891882 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104175676 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25284542 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 975484 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 66006 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6795 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6354 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446949 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445983 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892932 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104193042 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25290857 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 977433 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12720 # number of nop insts executed -system.cpu.iew.exec_refs 30343976 # number of memory reference insts executed -system.cpu.iew.exec_branches 21325145 # Number of branches executed -system.cpu.iew.exec_stores 5059434 # Number of stores executed -system.cpu.iew.exec_rate 1.944605 # Inst execution rate -system.cpu.iew.wb_sent 102960011 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102682964 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62233069 # num instructions producing a value -system.cpu.iew.wb_consumers 104282875 # num instructions consuming a value +system.cpu.iew.exec_nop 12714 # number of nop insts executed +system.cpu.iew.exec_refs 30352506 # number of memory reference insts executed +system.cpu.iew.exec_branches 21328586 # Number of branches executed +system.cpu.iew.exec_stores 5061649 # Number of stores executed +system.cpu.iew.exec_rate 1.945286 # Inst execution rate +system.cpu.iew.wb_sent 102976105 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102696313 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62237913 # num instructions producing a value +system.cpu.iew.wb_consumers 104299650 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.916741 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back +system.cpu.iew.wb_rate 1.917342 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596722 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26939053 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26949111 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833398 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49449876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.845363 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541608 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834092 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49438813 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.845776 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541803 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19967148 40.38% 40.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13135707 26.56% 66.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4163389 8.42% 75.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3434332 6.95% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1535763 3.11% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 744463 1.51% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 942034 1.91% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 246412 0.50% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5280628 10.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19950290 40.35% 40.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13144948 26.59% 66.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4163783 8.42% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3432949 6.94% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533470 3.10% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 746046 1.51% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 934782 1.89% 88.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 251563 0.51% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5280982 10.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49449876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49438813 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -465,70 +465,70 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5280628 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5280982 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162355527 # The number of ROB reads -system.cpu.rob.rob_writes 240299704 # The number of ROB writes -system.cpu.timesIdled 43654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 225864 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162354168 # The number of ROB reads +system.cpu.rob.rob_writes 240321058 # The number of ROB writes +system.cpu.timesIdled 43778 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 225660 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.591365 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.591365 # CPI: Total CPI of All Threads -system.cpu.ipc 1.691003 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.691003 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495535708 # number of integer regfile reads -system.cpu.int_regfile_writes 120542575 # number of integer regfile writes -system.cpu.fp_regfile_reads 173 # number of floating regfile reads -system.cpu.fp_regfile_writes 431 # number of floating regfile writes -system.cpu.misc_regfile_reads 29089632 # number of misc regfile reads +system.cpu.cpi 0.591256 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.591256 # CPI: Total CPI of All Threads +system.cpu.ipc 1.691314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.691314 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495624515 # number of integer regfile reads +system.cpu.int_regfile_writes 120561799 # number of integer regfile writes +system.cpu.fp_regfile_reads 167 # number of floating regfile reads +system.cpu.fp_regfile_writes 408 # number of floating regfile writes +system.cpu.misc_regfile_reads 29097050 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 630.397373 # Cycle average of tags in use -system.cpu.icache.total_refs 13842106 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19013.881868 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 630.487158 # Cycle average of tags in use +system.cpu.icache.total_refs 13846398 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18993.687243 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 630.397373 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.307811 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.307811 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13842106 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13842106 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13842106 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13842106 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13842106 # number of overall hits -system.cpu.icache.overall_hits::total 13842106 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses -system.cpu.icache.overall_misses::total 983 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49432499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49432499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49432499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49432499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49432499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49432499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13843089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13843089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13843089 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13843089 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13843089 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13843089 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 630.487158 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.307855 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.307855 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13846398 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13846398 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13846398 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13846398 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13846398 # number of overall hits +system.cpu.icache.overall_hits::total 13846398 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses +system.cpu.icache.overall_misses::total 984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49101999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49101999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49101999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49101999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49101999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49101999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13847382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13847382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13847382 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13847382 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13847382 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13847382 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50287.384537 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50287.384537 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50287.384537 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50287.384537 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49900.405488 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49900.405488 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49900.405488 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49900.405488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49900.405488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49900.405488 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -537,128 +537,128 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37907999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37907999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37907999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37907999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37907999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37907999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37481499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37481499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37481499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37481499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37481499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37481499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51716.233288 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51716.233288 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51134.377899 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51134.377899 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51134.377899 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51134.377899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51134.377899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51134.377899 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10760.479556 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 10757.893371 # Cycle average of tags in use system.cpu.l2cache.total_refs 1831525 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15496 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.193405 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15493 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.216291 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9911.805562 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 616.761334 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 231.912660 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.302484 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018822 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007077 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.328384 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 9911.352176 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 616.806864 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 229.734332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.302470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018823 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007011 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.328305 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 903743 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903767 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942900 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942900 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 29045 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 29045 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932788 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932812 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932788 # number of overall hits -system.cpu.l2cache.overall_hits::total 932812 # number of overall hits +system.cpu.l2cache.ReadReq_hits::total 903768 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942899 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942899 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 29037 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 29037 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932780 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932805 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932780 # number of overall hits +system.cpu.l2cache.overall_hits::total 932805 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 985 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 278 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 982 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14539 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14539 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14820 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15524 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15521 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14820 # number of overall misses -system.cpu.l2cache.overall_misses::total 15524 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36918500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15609500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 52528000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 628655000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 628655000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36918500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 644264500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 681183000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36918500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 644264500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 681183000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 728 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 904024 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904752 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942900 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942900 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43584 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43584 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 728 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948336 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 728 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948336 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000311 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333586 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.333586 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015639 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015639 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52441.051136 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55549.822064 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53327.918782 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43239.218653 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43239.218653 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 43879.348106 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 43879.348106 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses +system.cpu.l2cache.overall_misses::total 15521 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36482500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15550500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 52033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 628050000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 628050000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36482500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 643600500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 680083000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36482500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 643600500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 680083000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 729 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 904021 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904750 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942899 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942899 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43576 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43576 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 729 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947597 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948326 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 729 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947597 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948326 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965706 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001085 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333647 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.333647 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965706 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016367 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965706 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016367 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51821.732955 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55937.050360 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52986.761711 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43197.606438 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43197.606438 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51821.732955 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43436.626848 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 43816.957670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51821.732955 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43436.626848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 43816.957670 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -677,183 +677,183 @@ system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 974 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 268 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 971 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14539 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14539 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15513 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15510 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15513 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27943554 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11832709 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39776263 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15510 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27504806 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11810706 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39315512 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 448424221 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 448424221 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27943554 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 460256930 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 488200484 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27943554 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460256930 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 488200484 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001077 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39749.009957 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43663.132841 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40838.052361 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 447813969 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 447813969 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27504806 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 459624675 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 487129481 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27504806 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 459624675 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 487129481 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964335 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000296 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001073 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333647 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333647 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964335 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016355 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964335 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016355 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39124.901849 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44069.798507 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40489.713697 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30842.851709 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30842.851709 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30800.878258 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30800.878258 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39124.901849 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31041.039711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31407.445583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39124.901849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31041.039711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31407.445583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943512 # number of replacements -system.cpu.dcache.tagsinuse 3674.906425 # Cycle average of tags in use -system.cpu.dcache.total_refs 28139228 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.695009 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7938358000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3674.906425 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.897194 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.897194 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23594668 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23594668 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4536751 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4536751 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3908 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3908 # number of LoadLockedReq hits +system.cpu.dcache.replacements 943501 # number of replacements +system.cpu.dcache.tagsinuse 3674.828518 # Cycle average of tags in use +system.cpu.dcache.total_refs 28143712 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947597 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.700086 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7938430000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3674.828518 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.897175 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.897175 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23598974 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23598974 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4536932 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4536932 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28131419 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28131419 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28131419 # number of overall hits -system.cpu.dcache.overall_hits::total 28131419 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1172935 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1172935 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 198230 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 198230 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28135906 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28135906 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28135906 # number of overall hits +system.cpu.dcache.overall_hits::total 28135906 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1174144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1174144 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 198049 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 198049 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1371165 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1371165 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1371165 # number of overall misses -system.cpu.dcache.overall_misses::total 1371165 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884681000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13884681000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5602018407 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5602018407 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1372193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1372193 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1372193 # number of overall misses +system.cpu.dcache.overall_misses::total 1372193 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880291500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13880291500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5594114381 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5594114381 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19486699407 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19486699407 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19486699407 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19486699407 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24767603 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24767603 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19474405881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19474405881 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19474405881 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19474405881 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24773118 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24773118 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3914 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3915 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3915 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29502584 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29502584 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29502584 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29502584 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047358 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047358 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041865 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041865 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 29508099 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29508099 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29508099 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29508099 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047396 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047396 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041827 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041827 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001533 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001533 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046476 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046476 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046476 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046476 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.553658 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.553658 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28260.194759 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28260.194759 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.046502 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046502 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046502 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046502 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11821.626223 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11821.626223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28246.112735 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28246.112735 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14211.782978 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14211.782978 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 152466 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14192.176961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14192.176961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14192.176961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14192.176961 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152397 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23833 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23857 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.397264 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.387936 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942900 # number of writebacks -system.cpu.dcache.writebacks::total 942900 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268897 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 268897 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154655 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154655 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942899 # number of writebacks +system.cpu.dcache.writebacks::total 942899 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270103 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 270103 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154489 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154489 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 423552 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 423552 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 423552 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 423552 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904038 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904038 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43575 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43575 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947613 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947613 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947613 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947613 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990153500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990153500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 984037459 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 984037459 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10974190959 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10974190959 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10974190959 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10974190959 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009203 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009203 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032120 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.590241 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.590241 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22582.615238 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22582.615238 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 424592 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 424592 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 424592 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 424592 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904041 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904041 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43560 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43560 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947601 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947601 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947601 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947601 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990058500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990058500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 983302939 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 983302939 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10973361439 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10973361439 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10973361439 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10973361439 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036493 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036493 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009200 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009200 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032113 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032113 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032113 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032113 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.448486 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.448486 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22573.529362 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22573.529362 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.149703 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.149703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.149703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.149703 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 57123b5c9..989d45db0 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:30:24 +gem5 compiled Mar 26 2013 15:13:59 +gem5 started Mar 27 2013 00:35:52 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 66030660000 because target called exit() +Exiting @ tick 66015916000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index e747d6c9e..2c4cdb31e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.066031 # Number of seconds simulated -sim_ticks 66030660000 # Number of ticks simulated -final_tick 66030660000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066016 # Number of seconds simulated +sim_ticks 66015916000 # Number of ticks simulated +final_tick 66015916000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55728 # Simulator instruction rate (inst/s) -host_op_rate 98128 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23291229 # Simulator tick rate (ticks/s) -host_mem_usage 430752 # Number of bytes of host memory used -host_seconds 2835.00 # Real time elapsed on the host +host_inst_rate 35889 # Simulator instruction rate (inst/s) +host_op_rate 63194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14996247 # Simulator tick rate (ticks/s) +host_mem_usage 431068 # Number of bytes of host memory used +host_seconds 4402.16 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 64768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1881920 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10176 # Number of bytes written to this memory -system.physmem.bytes_written::total 10176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30417 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 159 # Number of write requests responded to by this memory -system.physmem.num_writes::total 159 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 980878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28500700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29481577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 980878 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 980878 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 980878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28500700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29635687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30419 # Total number of read requests seen -system.physmem.writeReqs 159 # Total number of write requests seen -system.physmem.cpureqs 30579 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1946688 # Total number of bytes read from memory -system.physmem.bytesWritten 10176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1946688 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10176 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 38 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882688 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory +system.physmem.bytes_written::total 10816 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29417 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory +system.physmem.num_writes::total 169 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 982066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28518698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29500765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 982066 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 982066 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163839 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163839 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 982066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28518698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29664604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30432 # Total number of read requests seen +system.physmem.writeReqs 169 # Total number of write requests seen +system.physmem.cpureqs 30602 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1947520 # Total number of bytes read from memory +system.physmem.bytesWritten 10816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1947520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1871 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1844 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1894 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 1799 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 39 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 14 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 66030647000 # Total gap between requests +system.physmem.totGap 66015903000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30419 # Categorize read packet sizes +system.physmem.readPktSize::6 30432 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 159 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.writePktSize::6 169 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,14 +124,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see @@ -145,8 +145,8 @@ system.physmem.wrQLenPdf::17 7 # Wh system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -156,266 +156,266 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 12950000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 610712500 # Sum of mem lat for all requests -system.physmem.totBusLat 151905000 # Total cycles spent in databus access -system.physmem.totBankLat 445857500 # Total cycles spent in bank access -system.physmem.avgQLat 426.25 # Average queueing delay per request -system.physmem.avgBankLat 14675.54 # Average bank access latency per request +system.physmem.totQLat 14883000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 612849250 # Sum of mem lat for all requests +system.physmem.totBusLat 151875000 # Total cycles spent in databus access +system.physmem.totBankLat 446091250 # Total cycles spent in bank access +system.physmem.avgQLat 489.98 # Average queueing delay per request +system.physmem.avgBankLat 14686.13 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20101.79 # Average memory access latency -system.physmem.avgRdBW 29.48 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.48 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 20176.11 # Average memory access latency +system.physmem.avgRdBW 29.50 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.50 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.37 # Average write queue length over time -system.physmem.readRowHits 29124 # Number of row buffer hits during reads -system.physmem.writeRowHits 74 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 46.54 # Row buffer hit rate for writes -system.physmem.avgGap 2159416.80 # Average gap between requests -system.cpu.branchPred.lookups 34530822 # Number of BP lookups -system.cpu.branchPred.condPredicted 34530822 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 911360 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24729253 # Number of BTB lookups -system.cpu.branchPred.BTBHits 24630321 # Number of BTB hits +system.physmem.avgWrQLen 12.99 # Average write queue length over time +system.physmem.readRowHits 29112 # Number of row buffer hits during reads +system.physmem.writeRowHits 92 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.44 # Row buffer hit rate for writes +system.physmem.avgGap 2157311.95 # Average gap between requests +system.cpu.branchPred.lookups 34543649 # Number of BP lookups +system.cpu.branchPred.condPredicted 34543649 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 911313 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24748799 # Number of BTB lookups +system.cpu.branchPred.BTBHits 24648647 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.599939 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.595326 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 132061321 # number of cpu cycles simulated +system.cpu.numCycles 132031833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26640465 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 185644154 # Number of instructions fetch has processed -system.cpu.fetch.Branches 34530822 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24630321 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56512430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6116130 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43661882 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 26608466 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 185598145 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34543649 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24648647 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 56505869 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6118180 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43668483 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 168 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25987124 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 190736 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131984046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.483688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.326165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 25960165 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 191907 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131953761 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.484443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326412 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78029555 59.12% 59.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1995729 1.51% 60.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2956074 2.24% 62.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3928612 2.98% 65.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7800232 5.91% 71.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757812 3.60% 75.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2739309 2.08% 77.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1526136 1.16% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28250587 21.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77999092 59.11% 59.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1996445 1.51% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2954879 2.24% 62.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3924320 2.97% 65.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7795201 5.91% 71.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757326 3.61% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2733781 2.07% 77.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1559430 1.18% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28233287 21.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131984046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261476 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.405742 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37482972 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35916557 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44772529 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8642915 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5169073 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 324582822 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 5169073 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43046448 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8564916 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9080 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 47588733 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27605796 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 320159922 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 237 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 45758 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25753634 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 322185741 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 849178580 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 849176902 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1678 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131953761 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261631 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.405708 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37450717 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35919295 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44755686 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8657316 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5170747 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 324590135 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5170747 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43008680 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8572089 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9131 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 47592423 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27600691 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 320189266 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 52468 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25750177 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 322200191 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 849206572 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 849204881 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1691 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42972994 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 471 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 465 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62311011 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 102521831 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 35289955 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39590581 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5948018 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 315836203 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1692 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 302241523 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114427 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 37009178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 54193553 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1247 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131984046 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.289985 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700189 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 42987444 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 470 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 464 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62325140 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 102538299 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35256894 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39591249 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6019659 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 315840251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1684 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 302185420 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114738 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37013163 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 54220323 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1239 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131953761 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700741 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24578568 18.62% 18.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23258852 17.62% 36.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25861899 19.59% 55.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25827751 19.57% 75.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18939781 14.35% 89.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8317897 6.30% 96.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4131388 3.13% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 904597 0.69% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 163313 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24578254 18.63% 18.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23242336 17.61% 36.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25887812 19.62% 55.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25783281 19.54% 75.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18948095 14.36% 89.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8310182 6.30% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4120126 3.12% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 915829 0.69% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 167846 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131984046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131953761 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 38531 1.97% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1832245 93.51% 95.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88531 4.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 38358 1.96% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1827997 93.47% 95.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 89360 4.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 171212053 56.65% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97762843 32.35% 89.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33235315 11.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 171162971 56.64% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97754962 32.35% 89.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33236179 11.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 302241523 # Type of FU issued -system.cpu.iq.rate 2.288645 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1959307 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738540324 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 352878782 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 299597425 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 502 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 804 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 304169320 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 229 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54003142 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 302185420 # Type of FU issued +system.cpu.iq.rate 2.288732 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1955715 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006472 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738394566 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 352887317 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 299540345 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 488 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 781 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 304109629 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54010503 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11742446 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 27574 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33469 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3850203 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11758914 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26738 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3817142 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3240 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8493 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8519 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5169073 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1760712 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159375 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 315837895 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 196193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 102521831 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 35289955 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 5170747 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1767696 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159609 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 315841935 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 195500 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 102538299 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35256894 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3161 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73375 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33469 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 522333 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 968671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 300624260 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97295381 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1617263 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3164 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73504 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 522441 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446022 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 968463 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 300565656 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97285754 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1619764 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 130311532 # number of memory reference insts executed -system.cpu.iew.exec_branches 30892471 # Number of branches executed -system.cpu.iew.exec_stores 33016151 # Number of stores executed -system.cpu.iew.exec_rate 2.276399 # Inst execution rate -system.cpu.iew.wb_sent 300027844 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 299597573 # cumulative count of insts written-back -system.cpu.iew.wb_producers 219555050 # num instructions producing a value -system.cpu.iew.wb_consumers 298061824 # num instructions consuming a value +system.cpu.iew.exec_refs 130302195 # number of memory reference insts executed +system.cpu.iew.exec_branches 30889184 # Number of branches executed +system.cpu.iew.exec_stores 33016441 # Number of stores executed +system.cpu.iew.exec_rate 2.276464 # Inst execution rate +system.cpu.iew.wb_sent 299955561 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 299540489 # cumulative count of insts written-back +system.cpu.iew.wb_producers 219513821 # num instructions producing a value +system.cpu.iew.wb_consumers 298021184 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.268625 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736609 # average fanout of values written-back +system.cpu.iew.wb_rate 2.268699 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736571 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 37658416 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 37662479 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 911380 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126814973 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.193688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.964855 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 911334 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126783014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.194241 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965349 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58216662 45.91% 45.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19288284 15.21% 61.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11866550 9.36% 70.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9593635 7.57% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1717867 1.35% 79.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2074758 1.64% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1297787 1.02% 82.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 717245 0.57% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22042185 17.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58216104 45.92% 45.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19275036 15.20% 61.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11824840 9.33% 70.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9597612 7.57% 78.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1736989 1.37% 79.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2070795 1.63% 81.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1302129 1.03% 82.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 715865 0.56% 82.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22043644 17.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126814973 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126783014 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -426,70 +426,70 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22042185 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22043644 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 420623668 # The number of ROB reads -system.cpu.rob.rob_writes 636875907 # The number of ROB writes -system.cpu.timesIdled 13847 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 77275 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 420594313 # The number of ROB reads +system.cpu.rob.rob_writes 636885752 # The number of ROB writes +system.cpu.timesIdled 13744 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78072 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.835892 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835892 # CPI: Total CPI of All Threads -system.cpu.ipc 1.196327 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.196327 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 592882448 # number of integer regfile reads -system.cpu.int_regfile_writes 300260228 # number of integer regfile writes -system.cpu.fp_regfile_reads 139 # number of floating regfile reads -system.cpu.fp_regfile_writes 69 # number of floating regfile writes -system.cpu.misc_regfile_reads 192732445 # number of misc regfile reads +system.cpu.cpi 0.835705 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835705 # CPI: Total CPI of All Threads +system.cpu.ipc 1.196594 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.196594 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 592843050 # number of integer regfile reads +system.cpu.int_regfile_writes 300182545 # number of integer regfile writes +system.cpu.fp_regfile_reads 134 # number of floating regfile reads +system.cpu.fp_regfile_writes 63 # number of floating regfile writes +system.cpu.misc_regfile_reads 192703630 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 62 # number of replacements -system.cpu.icache.tagsinuse 833.765098 # Cycle average of tags in use -system.cpu.icache.total_refs 25985776 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25253.426628 # Average number of references to valid blocks. +system.cpu.icache.replacements 61 # number of replacements +system.cpu.icache.tagsinuse 834.489266 # Cycle average of tags in use +system.cpu.icache.total_refs 25958820 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1031 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25178.292919 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 833.765098 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.407112 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.407112 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25985776 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25985776 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25985776 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25985776 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25985776 # number of overall hits -system.cpu.icache.overall_hits::total 25985776 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses -system.cpu.icache.overall_misses::total 1348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66423500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66423500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66423500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66423500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66423500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66423500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25987124 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25987124 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25987124 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25987124 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25987124 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25987124 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 834.489266 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.407465 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.407465 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25958820 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25958820 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25958820 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25958820 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25958820 # number of overall hits +system.cpu.icache.overall_hits::total 25958820 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1345 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1345 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1345 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1345 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1345 # number of overall misses +system.cpu.icache.overall_misses::total 1345 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65418500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65418500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65418500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65418500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65418500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65418500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25960165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25960165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25960165 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25960165 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25960165 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25960165 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49275.593472 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49275.593472 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49275.593472 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49275.593472 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49275.593472 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49275.593472 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48638.289963 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48638.289963 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48638.289963 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48638.289963 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48638.289963 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48638.289963 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -498,126 +498,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 26.600000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 318 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 318 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 318 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 318 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 318 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 318 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51809000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51809000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51809000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51809000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51809000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51809000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 313 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 313 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 313 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 313 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1032 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1032 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1032 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1032 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1032 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1032 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51534000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51534000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51534000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51534000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51534000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51534000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50300 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50300 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50300 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50300 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50300 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50300 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49936.046512 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49936.046512 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49936.046512 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49936.046512 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49936.046512 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49936.046512 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 466 # number of replacements -system.cpu.l2cache.tagsinuse 20794.050693 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4028842 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30396 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.545138 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 480 # number of replacements +system.cpu.l2cache.tagsinuse 20799.286466 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4028524 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30409 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.478016 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19862.572081 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 688.563421 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 242.915191 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.606158 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 19864.428387 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 688.567964 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 246.290114 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.606214 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021013 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.634584 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993511 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993528 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2066502 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2066502 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53260 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53260 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046771 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2046788 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046771 # number of overall hits -system.cpu.l2cache.overall_hits::total 2046788 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1012 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1419 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.data 0.007516 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.634744 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993506 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993524 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066214 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066214 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53254 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53254 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2046760 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2046778 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2046760 # number of overall hits +system.cpu.l2cache.overall_hits::total 2046778 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1013 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 420 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1433 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29000 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29000 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1012 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29407 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30419 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1012 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29407 # number of overall misses -system.cpu.l2cache.overall_misses::total 30419 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50601000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20149000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70750000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220932500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1220932500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50601000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1241081500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1291682500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50601000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1241081500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1291682500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1029 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1993918 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1994947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2066502 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2066502 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 28999 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28999 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1013 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29419 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30432 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1013 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29419 # number of overall misses +system.cpu.l2cache.overall_misses::total 30432 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50314000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20518000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70832000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1223231500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1223231500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50314000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1243749500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1294063500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50314000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1243749500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1294063500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1031 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1993926 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1994957 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066214 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066214 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82260 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82260 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1029 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076178 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077207 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1029 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076178 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077207 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983479 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000204 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000711 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82253 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82253 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1031 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076179 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077210 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1031 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076179 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077210 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982541 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000211 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000718 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352541 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352541 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983479 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014164 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983479 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014164 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50000.988142 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49506.142506 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49859.055673 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42101.120690 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42101.120690 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50000.988142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42203.607984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 42463.016536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50000.988142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42203.607984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 42463.016536 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352559 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352559 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982541 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014650 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982541 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014650 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49668.311945 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 48852.380952 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49429.169574 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42181.851098 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42181.851098 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49668.311945 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42277.082838 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42523.117114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49668.311945 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42277.082838 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42523.117114 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -626,168 +626,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 159 # number of writebacks -system.cpu.l2cache.writebacks::total 159 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1012 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1419 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 169 # number of writebacks +system.cpu.l2cache.writebacks::total 169 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 420 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1433 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1012 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29407 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30419 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1012 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29407 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30419 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38046308 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15112341 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53158649 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28999 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28999 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29419 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30432 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29419 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30432 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37747309 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15318354 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53065663 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 863152212 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 863152212 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38046308 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 878264553 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 916310861 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38046308 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 878264553 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 916310861 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983479 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000711 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 865494962 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 865494962 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37747309 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 880813316 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 918560625 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37747309 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 880813316 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 918560625 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982541 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000718 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983479 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983479 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014164 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37595.166008 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37131.058968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37462.050035 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982541 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014650 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982541 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014650 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37262.891412 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36472.271429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37031.167481 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29763.869379 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.869379 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37595.166008 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29865.833067 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30122.977777 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37595.166008 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29865.833067 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30122.977777 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29845.683024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29845.683024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37262.891412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29940.287433 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30184.037362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37262.891412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29940.287433 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30184.037362 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072079 # number of replacements -system.cpu.dcache.tagsinuse 4072.467231 # Cycle average of tags in use -system.cpu.dcache.total_refs 71962219 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076175 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.660960 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21183795000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.467231 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994255 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994255 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40620741 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40620741 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341471 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341471 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71962212 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71962212 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71962212 # number of overall hits -system.cpu.dcache.overall_hits::total 71962212 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2625931 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2625931 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98281 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98281 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2724212 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2724212 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2724212 # number of overall misses -system.cpu.dcache.overall_misses::total 2724212 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31328626500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31328626500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2110180998 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2110180998 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33438807498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33438807498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33438807498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33438807498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43246672 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43246672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072080 # number of replacements +system.cpu.dcache.tagsinuse 4072.471065 # Cycle average of tags in use +system.cpu.dcache.total_refs 71944468 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076176 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.652394 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21165048000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.471065 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40602724 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40602724 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341737 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341737 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71944461 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71944461 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71944461 # number of overall hits +system.cpu.dcache.overall_hits::total 71944461 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2627186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2627186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98015 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98015 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2725201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2725201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2725201 # number of overall misses +system.cpu.dcache.overall_misses::total 2725201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31333887000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31333887000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2111359499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2111359499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33445246499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33445246499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33445246499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33445246499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43229910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43229910 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74686424 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74686424 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74686424 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74686424 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060720 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060720 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036475 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036475 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036475 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036475 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.483512 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.483512 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21470.894659 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21470.894659 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.671537 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12274.671537 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.671537 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12274.671537 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32091 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74669662 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74669662 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74669662 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74669662 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060772 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060772 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003118 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003118 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036497 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036497 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036497 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036497 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11926.786684 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11926.786684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21541.187563 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21541.187563 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.579710 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12272.579710 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.579710 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12272.579710 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32228 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9458 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9462 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.393001 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.406045 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066502 # number of writebacks -system.cpu.dcache.writebacks::total 2066502 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631907 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631907 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16126 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16126 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 648033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 648033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 648033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 648033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994024 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994024 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82155 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82155 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076179 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076179 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076179 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076179 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1835038498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1835038498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23817290498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23817290498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817290498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23817290498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046108 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046108 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066214 # number of writebacks +system.cpu.dcache.writebacks::total 2066214 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 633159 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 633159 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15862 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15862 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 649021 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 649021 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 649021 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 649021 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994027 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994027 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82153 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82153 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076180 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076180 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076180 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076180 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983040000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983040000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1837362499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1837362499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23820402499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23820402499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23820402499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23820402499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027799 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027799 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027799 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027799 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.065909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.065909 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22336.297219 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22336.297219 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.694155 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.694155 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.694155 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.694155 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.444504 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.444504 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22365.129685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22365.129685 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.187536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.187536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.187536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.187536 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |