diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/long/se/10.mcf | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/long/se/10.mcf')
12 files changed, 1102 insertions, 1083 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini index 3938653f4..8b738959d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout index be80117c3..d0ca2b5a8 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 02:29:01 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x45a0240 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -24,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 61589191500 because target called exit() +Exiting @ tick 61240850500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 1f83c039b..8f24165d3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061280 # Number of seconds simulated -sim_ticks 61279840500 # Number of ticks simulated -final_tick 61279840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061241 # Number of seconds simulated +sim_ticks 61240850500 # Number of ticks simulated +final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263178 # Simulator instruction rate (inst/s) -host_op_rate 264489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 178002192 # Simulator tick rate (ticks/s) -host_mem_usage 447788 # Number of bytes of host memory used -host_seconds 344.26 # Real time elapsed on the host +host_inst_rate 182783 # Simulator instruction rate (inst/s) +host_op_rate 183693 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123547949 # Simulator tick rate (ticks/s) +host_mem_usage 442472 # Number of bytes of host memory used +host_seconds 495.69 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15456959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16265316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15456959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16265316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61279747000 # Total gap between requests +system.physmem.totGap 61240757000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 650.032658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 444.829113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.661041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 243 15.87% 15.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186 12.15% 28.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 73 4.77% 32.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 4.25% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 75 4.90% 41.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 100 6.53% 48.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 2.81% 51.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 51 3.33% 54.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 695 45.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation -system.physmem.totQLat 71795500 # Total ticks spent queuing -system.physmem.totMemAccLat 363808000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.totQLat 73458500 # Total ticks spent queuing +system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4609.96 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23359.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14039 # Number of row buffer hits during reads +system.physmem.readRowHits 14026 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3934746.82 # Average gap between requests -system.physmem.pageHitRate 90.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6259680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3415500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 3932243.29 # Average gap between requests +system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4002367200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2491685460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34581139500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41148640140 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.507037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57518843500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2046200000 # Time in different power states +system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.518851 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1713017750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4002367200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2548940535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34530915750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41147955240 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.495861 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57435989500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2046200000 # Time in different power states +system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.514525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1796249000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20766613 # Number of BP lookups -system.cpu.branchPred.condPredicted 17069686 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8958713 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8857097 # Number of BTB hits +system.cpu.branchPred.lookups 20752188 # Number of BP lookups +system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 757746 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8939036 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8856390 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.865730 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.075448 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 61984 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,67 +377,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122559681 # number of cpu cycles simulated +system.cpu.numCycles 122481701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2197712 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.352713 # CPI: cycles per instruction -system.cpu.ipc 0.739255 # IPC: instructions per cycle -system.cpu.tickCycles 109336366 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13223315 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 946108 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.962336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267632 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644203 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20520732500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.962336 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.883047 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883047 # Average percentage of cache occupancy +system.cpu.cpi 1.351853 # CPI: cycles per instruction +system.cpu.ipc 0.739726 # IPC: instructions per cycle +system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 946097 # number of replacements +system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 254 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2248 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463928 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463928 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598652 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598652 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660698 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660698 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55455001 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21594211 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21594211 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660690 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660690 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259858 # number of overall hits -system.cpu.dcache.overall_hits::total 26259858 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914943 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74283 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74283 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26254901 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26254901 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26255409 # number of overall hits +system.cpu.dcache.overall_hits::total 26255409 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74291 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74291 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 989226 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989226 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989230 # number of overall misses -system.cpu.dcache.overall_misses::total 989230 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918923000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918923000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2541568000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2541568000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14460491000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14460491000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14460491000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14460491000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 989217 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses +system.cpu.dcache.overall_misses::total 989221 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27249088 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27249088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 27244118 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27244118 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27244630 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27244630 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040647 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040647 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015690 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015690 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036304 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036304 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.956871 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.956871 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34214.665536 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34214.665536 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14617.985172 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14617.985172 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.926064 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14617.926064 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,109 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks -system.cpu.dcache.writebacks::total 943289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11509 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11509 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks +system.cpu.dcache.writebacks::total 943278 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11501 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11501 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27526 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27526 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39027 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39027 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39027 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39027 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903425 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903425 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46765 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46765 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865211000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865211000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480610000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480610000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345821000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12345821000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345977500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12345977500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.568626 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.568626 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31659.289670 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31659.289670 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.852039 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.852039 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.975719 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.975719 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 690.428077 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27792848 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 5 # number of replacements +system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34654.423940 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.428077 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337123 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337123 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55588102 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55588102 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27792848 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27792848 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27792848 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27792848 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27792848 # number of overall hits -system.cpu.icache.overall_hits::total 27792848 # number of overall hits +system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits +system.cpu.icache.overall_hits::total 27770466 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59599500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59599500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59599500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59599500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59599500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59599500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27793650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27793650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27793650 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27793650 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27793650 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27793650 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74313.591022 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74313.591022 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74313.591022 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74313.591022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74313.591022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74313.591022 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58797500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58797500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58797500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58797500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58797500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58797500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73313.591022 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73313.591022 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73313.591022 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73313.591022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73313.591022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73313.591022 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10246.423743 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1834010 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.889696 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9356.530979 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.454442 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.438322 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020583 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312696 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -632,22 +632,22 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15238060 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15238060 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 943289 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943289 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15237898 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 943278 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 943278 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32221 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32221 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903175 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 903175 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903166 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 903166 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 935398 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935424 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 935387 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 935413 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 935398 # number of overall hits -system.cpu.l2cache.overall_hits::total 935424 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 935387 # number of overall hits +system.cpu.l2cache.overall_hits::total 935413 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 776 # number of ReadCleanReq misses @@ -660,34 +660,34 @@ system.cpu.l2cache.demand_misses::total 15582 # nu system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066648000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1066648000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57320500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 57320500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21756000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21756000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57320500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1088404000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1145724500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57320500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1088404000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1145724500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 943289 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943289 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # 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number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 903437 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903428 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 903428 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 950204 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950193 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 950995 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 950204 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 950193 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 950995 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311002 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311002 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967581 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses @@ -698,18 +698,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73339.383938 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73339.383938 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73866.623711 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73866.623711 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83038.167939 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83038.167939 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73866.623711 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73511.009050 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73528.719035 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73866.623711 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73511.009050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73528.719035 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,73 +740,73 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49433000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940013000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 989446000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63339.383938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63339.383938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63866.925065 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63866.925065 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73457.031250 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73457.031250 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63866.925065 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63514.391892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63531.912161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63866.925065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63514.391892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63531.912161 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2672 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 903437 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846366 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2847973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1897118 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1897118 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1897118 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891848000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1425308994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution @@ -827,9 +827,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21740500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82134000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index a092bf499..86dba512f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,9 +688,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index eaa0003ec..976e948eb 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,13 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 10:58:25 -gem5 started Apr 22 2015 11:34:28 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 02:12:41 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x299b730 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -25,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 58202727500 because target called exit() +Exiting @ tick 58182114500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index 263d31358..a3f3e3177 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -118,7 +118,7 @@ eventq_index=0 size=64 [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -166,7 +166,7 @@ eventq_index=0 size=64 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 009ef705f..e66d5ccc4 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 19:43:22 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing +gem5 compiled Sep 14 2015 22:05:26 +gem5 started Sep 14 2015 22:06:13 +gem5 executing on ribera.cs.wisc.edu +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 361488530000 because target called exit() +Exiting @ tick 361488535500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 399eedece..d4aa178ac 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -156,7 +156,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -513,7 +513,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -579,7 +579,7 @@ system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -642,9 +642,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index d8c79ae54..efb33d70a 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 08:10:29 -gem5 started Apr 22 2015 09:28:24 -gem5 executing on phenom -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +gem5 compiled Sep 14 2015 22:13:36 +gem5 started Sep 14 2015 22:43:54 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -17,12 +19,12 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 +info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 simplex iterations : 2663 -info: Increasing stack size by one page. flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 62113055500 because target called exit() +Exiting @ tick 61602395500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 6f4514f73..40c2eacfb 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062104 # Number of seconds simulated -sim_ticks 62103992500 # Number of ticks simulated -final_tick 62103992500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061602 # Number of seconds simulated +sim_ticks 61602395500 # Number of ticks simulated +final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108853 # Simulator instruction rate (inst/s) -host_op_rate 191673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42789284 # Simulator tick rate (ticks/s) -host_mem_usage 455804 # Number of bytes of host memory used -host_seconds 1451.39 # Real time elapsed on the host +host_inst_rate 83209 # Simulator instruction rate (inst/s) +host_op_rate 146518 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32444685 # Simulator tick rate (ticks/s) +host_mem_usage 451056 # Number of bytes of host memory used +host_seconds 1898.69 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883648 # Number of bytes read from this memory -system.physmem.bytes_read::total 1948480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 11776 # Number of bytes written to this memory system.physmem.bytes_written::total 11776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29432 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 184 # Number of write requests responded to by this memory system.physmem.num_writes::total 184 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30330546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31374472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 189617 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 189617 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 189617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30330546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31564090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30446 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 1036843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30569201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31606044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1036843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1036843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 191161 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 191161 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 191161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1036843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30569201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31797205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30422 # Number of read requests accepted system.physmem.writeReqs 184 # Number of write requests accepted -system.physmem.readBursts 30446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 30422 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 184 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 1941952 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue -system.physmem.bytesWritten 10368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1948544 # Total read bytes from the system interface side +system.physmem.bytesWritten 10304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1947008 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 11776 # Total written bytes from the system interface side system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1927 # Per bank write bursts -system.physmem.perBankRdBursts::1 2069 # Per bank write bursts -system.physmem.perBankRdBursts::2 2026 # Per bank write bursts -system.physmem.perBankRdBursts::3 1929 # Per bank write bursts +system.physmem.perBankRdBursts::0 1928 # Per bank write bursts +system.physmem.perBankRdBursts::1 2065 # Per bank write bursts +system.physmem.perBankRdBursts::2 2023 # Per bank write bursts +system.physmem.perBankRdBursts::3 1928 # Per bank write bursts system.physmem.perBankRdBursts::4 2026 # Per bank write bursts system.physmem.perBankRdBursts::5 1901 # Per bank write bursts -system.physmem.perBankRdBursts::6 1959 # Per bank write bursts -system.physmem.perBankRdBursts::7 1865 # Per bank write bursts +system.physmem.perBankRdBursts::6 1952 # Per bank write bursts +system.physmem.perBankRdBursts::7 1864 # Per bank write bursts system.physmem.perBankRdBursts::8 1938 # Per bank write bursts -system.physmem.perBankRdBursts::9 1937 # Per bank write bursts -system.physmem.perBankRdBursts::10 1805 # Per bank write bursts -system.physmem.perBankRdBursts::11 1796 # Per bank write bursts +system.physmem.perBankRdBursts::9 1932 # Per bank write bursts +system.physmem.perBankRdBursts::10 1804 # Per bank write bursts +system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1819 # Per bank write bursts +system.physmem.perBankRdBursts::14 1818 # Per bank write bursts system.physmem.perBankRdBursts::15 1778 # Per bank write bursts -system.physmem.perBankWrBursts::0 25 # Per bank write bursts -system.physmem.perBankWrBursts::1 94 # Per bank write bursts -system.physmem.perBankWrBursts::2 8 # Per bank write bursts -system.physmem.perBankWrBursts::3 7 # Per bank write bursts -system.physmem.perBankWrBursts::4 7 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 10 # Per bank write bursts +system.physmem.perBankWrBursts::1 82 # Per bank write bursts +system.physmem.perBankWrBursts::2 7 # Per bank write bursts +system.physmem.perBankWrBursts::3 28 # Per bank write bursts +system.physmem.perBankWrBursts::4 6 # Per bank write bursts +system.physmem.perBankWrBursts::5 7 # Per bank write bursts system.physmem.perBankWrBursts::6 13 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62103972000 # Total gap between requests +system.physmem.totGap 61602210500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30446 # Read request sizes (log2) +system.physmem.readPktSize::6 30422 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 184 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,8 +144,8 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see @@ -153,7 +153,7 @@ system.physmem.wrQLenPdf::20 10 # Wh system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see @@ -193,324 +193,326 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2720 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 718.117647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 516.851204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 389.329010 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 349 12.83% 12.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 252 9.26% 22.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 126 4.63% 26.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 106 3.90% 30.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 106 3.90% 34.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 118 4.34% 38.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 88 3.24% 42.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 74 2.72% 44.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1501 55.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2720 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 716.414401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 516.531797 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.717070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 355 13.04% 13.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 240 8.82% 21.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 126 4.63% 26.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 120 4.41% 30.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 92 3.38% 34.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 131 4.81% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 110 4.04% 43.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 2.46% 45.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1481 54.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2722 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3367.333333 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 25.147360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10062.626521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3364.888889 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 25.331779 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10055.293027 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 9 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.888889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.873018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.781736 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 131808750 # Total ticks spent queuing -system.physmem.totMemAccLat 701190000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4340.53 # Average queueing delay per DRAM burst +system.physmem.totQLat 132992250 # Total ticks spent queuing +system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23090.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage -system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 13.82 # Average write queue length when enqueuing -system.physmem.readRowHits 27697 # Number of row buffer hits during reads -system.physmem.writeRowHits 108 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.70 # Row buffer hit rate for writes -system.physmem.avgGap 2027553.77 # Average gap between requests -system.physmem.pageHitRate 91.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10848600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5919375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122421000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 997920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2874471525 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34740567750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41811500730 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.256335 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57777967000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2073760000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.66 # Average write queue length when enqueuing +system.physmem.readRowHits 27667 # Number of row buffer hits during reads +system.physmem.writeRowHits 105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.38 # Row buffer hit rate for writes +system.physmem.avgGap 2012749.48 # Average gap between requests +system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.233667 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2251676750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114371400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3081237030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34559194500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41826144555 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.492132 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57475856750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2073760000 # Time in different power states +system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.432156 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2554341750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37407153 # Number of BP lookups -system.cpu.branchPred.condPredicted 37407153 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 797525 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21397569 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21291133 # Number of BTB hits +system.cpu.branchPred.lookups 36908902 # Number of BP lookups +system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 21094595 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21013332 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.502579 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5522199 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5378 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5443329 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4414 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 124207986 # number of cpu cycles simulated +system.cpu.numCycles 123204792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28243826 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 201531916 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37407153 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26813332 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 95053081 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1666271 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 14570 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27815548 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 199030226 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36908902 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26456661 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 94542157 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1553197 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5286 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 27854872 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 208775 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 124145503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.860655 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.369153 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 27443892 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 182896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 123139971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.847273 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.366420 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 63227150 50.93% 50.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3664165 2.95% 53.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3505505 2.82% 56.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5966108 4.81% 61.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7642313 6.16% 67.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5450974 4.39% 72.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3347715 2.70% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2079081 1.67% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29262492 23.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 62945586 51.12% 51.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3649644 2.96% 54.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3480667 2.83% 56.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5913875 4.80% 61.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7544210 6.13% 67.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5413973 4.40% 72.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3251113 2.64% 74.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2020097 1.64% 76.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28920806 23.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 124145503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.301165 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.622536 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13298609 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63688691 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 36532978 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9792090 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 833135 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 335053232 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 833135 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18606460 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8830273 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16174 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40807487 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55051974 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328692220 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2265 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 765831 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48323645 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4961410 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 330669691 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 873156420 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537756143 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 567 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 123139971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.299574 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.615442 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12941533 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63708539 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 35887594 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9825707 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 776598 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51456944 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 481 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66169497 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106330183 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36531613 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49817317 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8395275 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 325507363 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2500 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 308019505 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 47317399 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68952386 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2055 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 124145503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.481117 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.143684 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 492 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8500454 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322302016 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 306103022 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 44111266 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 63884636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123139971 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30872061 24.87% 24.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19525697 15.73% 40.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16787256 13.52% 54.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17357634 13.98% 68.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14846406 11.96% 80.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12689504 10.22% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6302474 5.08% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3917362 3.16% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1847109 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 124145503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123139971 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 329941 8.31% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3456308 87.04% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 184474 4.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 338797 8.53% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 175410718 56.95% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11212 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 340 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98529790 31.99% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34034069 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174121945 56.88% 56.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 308019505 # Type of FU issued -system.cpu.iq.rate 2.479869 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3970723 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012891 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 744205245 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 372866875 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 306008038 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 524 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 864 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 311956642 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 248 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58273942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued +system.cpu.iq.rate 2.484506 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15550798 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67136 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41716 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5091861 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4729641 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3678 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 142532 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 833135 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5706209 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3030570 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 325509863 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125935 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106330183 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36531613 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 471 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2800 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3033928 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41716 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 402612 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445047 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847659 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 306958421 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98183223 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1061084 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 786456 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 305156723 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97750585 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 946299 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 132003276 # number of memory reference insts executed -system.cpu.iew.exec_branches 31537655 # Number of branches executed -system.cpu.iew.exec_stores 33820053 # Number of stores executed -system.cpu.iew.exec_rate 2.471326 # Inst execution rate -system.cpu.iew.wb_sent 306335531 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 306008206 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231609196 # num instructions producing a value -system.cpu.iew.wb_consumers 336109097 # num instructions consuming a value +system.cpu.iew.exec_refs 131430383 # number of memory reference insts executed +system.cpu.iew.exec_branches 31401847 # Number of branches executed +system.cpu.iew.exec_stores 33679798 # Number of stores executed +system.cpu.iew.exec_rate 2.476825 # Inst execution rate +system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back +system.cpu.iew.wb_producers 230213925 # num instructions producing a value +system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.463676 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689089 # average fanout of values written-back +system.cpu.iew.wb_rate 2.469732 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 47420049 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 44209684 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 798401 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117693042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.363712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.086908 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 742009 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117119203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 53351319 45.33% 45.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15952359 13.55% 58.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10962553 9.31% 68.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8763534 7.45% 75.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1923790 1.63% 77.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1729278 1.47% 78.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 853123 0.72% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 692579 0.59% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23464507 19.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117693042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117119203 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -556,330 +558,334 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23464507 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 419841048 # The number of ROB reads -system.cpu.rob.rob_writes 657686557 # The number of ROB writes -system.cpu.timesIdled 566 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 62483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23512617 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 416008734 # The number of ROB reads +system.cpu.rob.rob_writes 650833809 # The number of ROB writes +system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64821 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.786183 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.786183 # CPI: Total CPI of All Threads -system.cpu.ipc 1.271968 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.271968 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 493729388 # number of integer regfile reads -system.cpu.int_regfile_writes 240917610 # number of integer regfile writes -system.cpu.fp_regfile_reads 146 # number of floating regfile reads -system.cpu.fp_regfile_writes 96 # number of floating regfile writes -system.cpu.cc_regfile_reads 107705980 # number of cc regfile reads -system.cpu.cc_regfile_writes 64576396 # number of cc regfile writes -system.cpu.misc_regfile_reads 196329384 # number of misc regfile reads +system.cpu.cpi 0.779834 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.779834 # CPI: Total CPI of All Threads +system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 491477122 # number of integer regfile reads +system.cpu.int_regfile_writes 239432261 # number of integer regfile writes +system.cpu.fp_regfile_reads 110 # number of floating regfile reads +system.cpu.fp_regfile_writes 84 # number of floating regfile writes +system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads +system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes +system.cpu.misc_regfile_reads 195275944 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072430 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.090496 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68424035 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076526 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.951206 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19739908500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.090496 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993186 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993186 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072313 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.012942 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68071048 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076409 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.783063 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993167 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3373 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 630 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3339 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144493228 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144493228 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37078222 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37078222 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345813 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345813 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68424035 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68424035 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68424035 # number of overall hits -system.cpu.dcache.overall_hits::total 68424035 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2690377 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2690377 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93939 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93939 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2784316 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2784316 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2784316 # number of overall misses -system.cpu.dcache.overall_misses::total 2784316 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32316565000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32316565000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2955969494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2955969494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35272534494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35272534494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35272534494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35272534494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39768599 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39768599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 143788667 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 143788667 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 36725223 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 36725223 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345824 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345824 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68071047 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71208351 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71208351 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71208351 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71208351 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067651 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067651 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 70856129 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 70856129 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 70856129 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 70856129 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039101 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039101 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039101 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039101 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12011.909483 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12011.909483 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31466.903991 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31466.903991 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12668.294293 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12668.294293 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221313 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43094 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135587 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066711 # number of writebacks -system.cpu.dcache.writebacks::total 2066711 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 695911 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 695911 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11877 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11877 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 707788 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 707788 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 707788 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 707788 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82062 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24203306500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24203306500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2798613994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2798613994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27001920494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27001920494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27001920494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27001920494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks +system.cpu.dcache.writebacks::total 2066601 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11884 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11884 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 708672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 708672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 708672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 708672 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994366 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12135.231435 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12135.231435 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34103.653262 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34103.653262 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 64 # number of replacements -system.cpu.icache.tags.tagsinuse 833.320748 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27853507 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1032 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26989.832364 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 53 # number of replacements +system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 833.320748 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.406895 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.406895 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 968 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.472656 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55710776 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55710776 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27853507 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27853507 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27853507 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27853507 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 98783500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27854872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27854872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27854872 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27854872 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27854872 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27854872 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000049 # 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Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 54888798 # Number of tag accesses +system.cpu.icache.tags.data_accesses 54888798 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27442569 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27442569 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27442569 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27442569 # 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number of cycles access was blocked @@ -890,116 +896,118 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 184 # number of writebacks system.cpu.l2cache.writebacks::total 184 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1013 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1013 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 437 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 437 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353213 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353213 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.981589 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000219 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000219 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000214 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 1995466 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6085 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82092 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82092 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994436 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225475 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6227603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265167168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265233216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 495 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4150549 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.000119 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010920 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 487 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4150054 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 495 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4150549 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4141738000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1548000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3114789000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1448 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1424 # Transaction distribution system.membus.trans_dist::Writeback 184 # Transaction distribution -system.membus.trans_dist::CleanEvict 34 # Transaction distribution -system.membus.trans_dist::ReadExReq 28996 # Transaction distribution -system.membus.trans_dist::ReadExResp 28996 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1450 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61108 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1960192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1960192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1960192 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 30 # Transaction distribution +system.membus.trans_dist::ReadExReq 28998 # Transaction distribution +system.membus.trans_dist::ReadExResp 28998 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1424 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61058 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1958784 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30664 # Request fanout histogram +system.membus.snoop_fanout::samples 30636 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30636 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30664 # Request fanout histogram -system.membus.reqLayer0.occupancy 42854000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30636 # Request fanout histogram +system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160427250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index fecf9a5e9..f0cb43f99 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -84,7 +84,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -134,7 +134,7 @@ system=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -200,7 +200,7 @@ system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 42e3e20b3..dc48bfe97 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 20:18:36 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing +gem5 compiled Sep 14 2015 22:13:36 +gem5 started Sep 14 2015 23:02:52 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 365989065000 because target called exit() +Exiting @ tick 365988859500 because target called exit() |