diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/long/se/10.mcf | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/long/se/10.mcf')
5 files changed, 1475 insertions, 1467 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0326fa208..7f5474242 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025283 # Number of seconds simulated -sim_ticks 25283397500 # Number of ticks simulated -final_tick 25283397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.027092 # Number of seconds simulated +sim_ticks 27092156000 # Number of ticks simulated +final_tick 27092156000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115178 # Simulator instruction rate (inst/s) -host_op_rate 116005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32142506 # Simulator tick rate (ticks/s) -host_mem_usage 365228 # Number of bytes of host memory used -host_seconds 786.60 # Real time elapsed on the host -sim_insts 90599358 # Number of instructions simulated -sim_ops 91249911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory +host_inst_rate 163409 # Simulator instruction rate (inst/s) +host_op_rate 164582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48864627 # Simulator tick rate (ticks/s) +host_mem_usage 366512 # Number of bytes of host memory used +host_seconds 554.43 # Real time elapsed on the host +sim_insts 90599363 # Number of instructions simulated +sim_ops 91249916 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory system.physmem.bytes_read::total 993280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45760 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 715 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 45696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45696 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1809883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37475976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39285859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1809883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1809883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1809883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37475976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 39285859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1686687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34976323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36663011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1686687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1686687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1686687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34976323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36663011 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15520 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady @@ -36,21 +36,21 @@ system.physmem.bytesConsumedRd 993280 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 965 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 903 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 937 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1013 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 935 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 999 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 977 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25283243500 # Total gap between requests +system.physmem.totGap 27092026500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,16 +98,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 9030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 43058501 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 270142501 # Sum of mem lat for all requests +system.physmem.totQLat 41952001 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 275602001 # Sum of mem lat for all requests system.physmem.totBusLat 62080000 # Total cycles spent in databus access -system.physmem.totBankLat 165004000 # Total cycles spent in bank access -system.physmem.avgQLat 2774.39 # Average queueing delay per request -system.physmem.avgBankLat 10631.70 # Average bank access latency per request +system.physmem.totBankLat 171570000 # Total cycles spent in bank access +system.physmem.avgQLat 2703.09 # Average queueing delay per request +system.physmem.avgBankLat 11054.77 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 17406.09 # Average memory access latency -system.physmem.avgRdBW 39.29 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 17757.86 # Average memory access latency +system.physmem.avgRdBW 36.66 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 39.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 36.66 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.25 # Data bus utilization in percentage +system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15094 # Number of row buffer hits during reads +system.physmem.readRowHits 15093 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 97.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1629074.97 # Average gap between requests +system.physmem.avgGap 1745620.26 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,628 +228,630 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 50566796 # number of cpu cycles simulated +system.cpu.numCycles 54184313 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26827710 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22074051 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 888543 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11563656 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11363946 # Number of BTB hits +system.cpu.BPredUnit.lookups 26986209 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22240935 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 891955 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11647054 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11461257 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 71231 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 482 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14348377 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128701471 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26827710 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11435177 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24213451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4809546 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8060195 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.BPredUnit.usedRAS 72758 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 485 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14421407 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 129482789 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26986209 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11534015 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24364148 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4949387 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11145499 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14028280 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 377661 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 50539595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.565225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.255897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14072424 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 353920 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53972527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.416768 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215873 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 26364164 52.17% 52.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3431492 6.79% 58.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2034951 4.03% 62.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1571856 3.11% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1677128 3.32% 69.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2962722 5.86% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1482816 2.93% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1106293 2.19% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9908173 19.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29646325 54.93% 54.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3454402 6.40% 61.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2035756 3.77% 65.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1585198 2.94% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1689643 3.13% 71.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2992855 5.55% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1501294 2.78% 79.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1109449 2.06% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9957605 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 50539595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.530540 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.545177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16886092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6166490 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22746907 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 831459 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3908647 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4474881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9055 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126903101 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43084 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3908647 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18602269 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1370571 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 152009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21842488 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4663611 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123722180 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 282360 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3941818 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 144182082 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 538941570 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 538934983 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6587 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36752600 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6474 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6472 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 10800172 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29574364 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5545202 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2016944 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1216593 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118465493 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10340 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105556460 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 69311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27028341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 66448905 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 210 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 50539595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.088589 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.960694 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 53972527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498045 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.389673 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17207234 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9007840 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22744655 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 980413 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4032385 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4494708 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9020 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 127545337 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43010 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4032385 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19020781 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3479230 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 185856 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21813074 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5441201 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124457435 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 413531 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4571711 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1235 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145128165 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 542105971 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 542097092 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8879 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429490 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 37698675 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6572 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6570 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12467133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29726886 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5575716 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2113972 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1267479 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119141743 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10445 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105694934 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 87169 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27699731 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68149614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 314 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53972527 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.958310 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906959 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13663948 27.04% 27.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10566811 20.91% 47.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7991493 15.81% 63.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6436117 12.73% 76.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4858269 9.61% 86.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3518110 6.96% 93.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2381435 4.71% 97.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 601220 1.19% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 522192 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15655199 29.01% 29.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11785517 21.84% 50.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8331092 15.44% 66.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6816137 12.63% 78.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4950230 9.17% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2999113 5.56% 93.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2477964 4.59% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 523647 0.97% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 433628 0.80% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 50539595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53972527 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 142805 18.40% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 357317 46.04% 64.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276029 35.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 46062 6.88% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 347309 51.84% 58.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 276528 41.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74650431 70.72% 70.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10952 0.01% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 213 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 258 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25757662 24.40% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5136941 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74789995 70.76% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10964 0.01% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 273 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 352 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25743831 24.36% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5149514 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105556460 # Type of FU issued -system.cpu.iq.rate 2.087466 # Inst issue rate -system.cpu.iq.fu_busy_cnt 776178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007353 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262497002 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 145505542 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102811583 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1002 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1425 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 429 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106332135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 503 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 448933 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105694934 # Type of FU issued +system.cpu.iq.rate 1.950656 # Inst issue rate +system.cpu.iq.fu_busy_cnt 669926 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006338 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266118166 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146855539 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 103065096 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1324 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1913 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 572 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106364200 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 660 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 431890 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6998486 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7563 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 798446 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7151007 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8111 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6407 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 828959 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13664 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30712 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3908647 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 40058 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10147 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118488563 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 346139 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29574364 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5545202 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6435 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 113 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 475714 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 478249 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 953963 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104402584 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25308083 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1153876 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4032385 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 880978 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 122273 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119164915 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 339993 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29726886 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5575716 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6543 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65097 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6980 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6407 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 480710 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 474427 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 955137 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104665581 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25412111 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1029353 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12730 # number of nop insts executed -system.cpu.iew.exec_refs 30381749 # number of memory reference insts executed -system.cpu.iew.exec_branches 21354330 # Number of branches executed -system.cpu.iew.exec_stores 5073666 # Number of stores executed -system.cpu.iew.exec_rate 2.064647 # Inst execution rate -system.cpu.iew.wb_sent 103125475 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102812012 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62190160 # num instructions producing a value -system.cpu.iew.wb_consumers 104171478 # num instructions consuming a value +system.cpu.iew.exec_nop 12727 # number of nop insts executed +system.cpu.iew.exec_refs 30497033 # number of memory reference insts executed +system.cpu.iew.exec_branches 21398144 # Number of branches executed +system.cpu.iew.exec_stores 5084922 # Number of stores executed +system.cpu.iew.exec_rate 1.931658 # Inst execution rate +system.cpu.iew.wb_sent 103359257 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 103065668 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62382767 # num instructions producing a value +system.cpu.iew.wb_consumers 104584630 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.033192 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596998 # average fanout of values written-back +system.cpu.iew.wb_rate 1.902131 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596481 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27226534 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 879646 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 46630949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.957123 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.526822 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 27905407 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10131 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 883062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49940143 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.827438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.524426 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16429146 35.23% 35.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13384342 28.70% 63.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4483579 9.62% 73.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3865779 8.29% 81.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1521076 3.26% 85.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 802170 1.72% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 837343 1.80% 88.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 265641 0.57% 89.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5041873 10.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20246507 40.54% 40.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13253757 26.54% 67.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4242903 8.50% 75.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3506121 7.02% 82.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1547134 3.10% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 741508 1.48% 87.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 927602 1.86% 89.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253977 0.51% 89.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5220634 10.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 46630949 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611967 # Number of instructions committed -system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 49940143 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611972 # Number of instructions committed +system.cpu.commit.committedOps 91262525 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322634 # Number of memory references committed -system.cpu.commit.loads 22575878 # Number of loads committed +system.cpu.commit.refs 27322636 # Number of memory references committed +system.cpu.commit.loads 22575879 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18734216 # Number of branches committed +system.cpu.commit.branches 18734217 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533326 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5041873 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5220634 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 160072396 # The number of ROB reads -system.cpu.rob.rob_writes 240909016 # The number of ROB writes -system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27201 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599358 # Number of Instructions Simulated -system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated -system.cpu.cpi 0.558136 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558136 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791677 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791677 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 496271114 # number of integer regfile reads -system.cpu.int_regfile_writes 120718739 # number of integer regfile writes -system.cpu.fp_regfile_reads 209 # number of floating regfile reads -system.cpu.fp_regfile_writes 557 # number of floating regfile writes -system.cpu.misc_regfile_reads 182190391 # number of misc regfile reads -system.cpu.misc_regfile_writes 11608 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 643.406523 # Cycle average of tags in use -system.cpu.icache.total_refs 14027306 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18853.905914 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 163881707 # The number of ROB reads +system.cpu.rob.rob_writes 242387570 # The number of ROB writes +system.cpu.timesIdled 40508 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 211786 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599363 # Number of Instructions Simulated +system.cpu.committedOps 91249916 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599363 # Number of Instructions Simulated +system.cpu.cpi 0.598065 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.598065 # CPI: Total CPI of All Threads +system.cpu.ipc 1.672059 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.672059 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 497610089 # number of integer regfile reads +system.cpu.int_regfile_writes 120987803 # number of integer regfile writes +system.cpu.fp_regfile_reads 263 # number of floating regfile reads +system.cpu.fp_regfile_writes 760 # number of floating regfile writes +system.cpu.misc_regfile_reads 183141130 # number of misc regfile reads +system.cpu.misc_regfile_writes 11610 # number of misc regfile writes +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.tagsinuse 641.121517 # Cycle average of tags in use +system.cpu.icache.total_refs 14071405 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 743 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18938.633917 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 643.406523 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.314163 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.314163 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14027306 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14027306 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14027306 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14027306 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14027306 # number of overall hits -system.cpu.icache.overall_hits::total 14027306 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 974 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 974 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 974 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 974 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 974 # number of overall misses -system.cpu.icache.overall_misses::total 974 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30438500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30438500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30438500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30438500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30438500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30438500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14028280 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14028280 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14028280 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14028280 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14028280 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14028280 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31251.026694 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31251.026694 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31251.026694 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31251.026694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31251.026694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31251.026694 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 641.121517 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.313048 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.313048 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14071405 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14071405 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14071405 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14071405 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14071405 # number of overall hits +system.cpu.icache.overall_hits::total 14071405 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1017 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1017 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1017 # number of overall misses +system.cpu.icache.overall_misses::total 1017 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47244499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47244499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47244499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47244499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47244499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47244499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14072422 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14072422 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14072422 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14072422 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14072422 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14072422 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46454.767945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46454.767945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46454.767945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46454.767945 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 230 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 230 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 230 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 230 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 230 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 230 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 744 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 744 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 744 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 744 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 744 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24024500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24024500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 274 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 274 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 274 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 274 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 743 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 743 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 743 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 743 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 743 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 743 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36064499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36064499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36064499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36064499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36064499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36064499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32290.994624 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32290.994624 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32290.994624 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32290.994624 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32290.994624 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32290.994624 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48539.029610 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48539.029610 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48539.029610 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48539.029610 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48539.029610 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48539.029610 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943584 # number of replacements -system.cpu.dcache.tagsinuse 3642.676555 # Cycle average of tags in use -system.cpu.dcache.total_refs 28382023 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947680 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.948952 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8082482000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3642.676555 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.889325 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.889325 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23788332 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23788332 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4582046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4582046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5846 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5846 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28370378 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28370378 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28370378 # number of overall hits -system.cpu.dcache.overall_hits::total 28370378 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1007938 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1007938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 152935 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 152935 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1160873 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1160873 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1160873 # number of overall misses -system.cpu.dcache.overall_misses::total 1160873 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4150084000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4150084000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2674625065 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2674625065 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 118000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6824709065 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6824709065 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6824709065 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6824709065 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24796270 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24796270 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943610 # number of replacements +system.cpu.dcache.tagsinuse 3668.756958 # Cycle average of tags in use +system.cpu.dcache.total_refs 28277834 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947706 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.838192 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8133068000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3668.756958 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.895693 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.895693 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23721969 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23721969 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4544209 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4544209 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5800 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5800 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28266178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28266178 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28266178 # number of overall hits +system.cpu.dcache.overall_hits::total 28266178 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1182969 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1182969 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 190772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 190772 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373741 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373741 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373741 # number of overall misses +system.cpu.dcache.overall_misses::total 1373741 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13927378500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13927378500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5211268429 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5211268429 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19138646929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19138646929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19138646929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19138646929 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24904938 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24904938 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5854 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5854 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29531251 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29531251 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29531251 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29531251 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040649 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040649 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032299 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032299 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039310 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039310 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039310 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039310 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4117.400078 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 4117.400078 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17488.639389 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17488.639389 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 5878.945470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 5878.945470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 5878.945470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 5878.945470 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12644 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5800 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5800 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29639919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29639919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29639919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29639919 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047499 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047499 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040290 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040290 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046348 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046348 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046348 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046348 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11773.240465 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11773.240465 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27316.736361 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27316.736361 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13931.772386 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13931.772386 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 151113 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23634 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.939561 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.393882 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942946 # number of writebacks -system.cpu.dcache.writebacks::total 942946 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 94900 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 94900 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 118293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 118293 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 213193 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 213193 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 213193 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 213193 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 913038 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 913038 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 34642 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 34642 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947680 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947680 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947680 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947680 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1880090500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1880090500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 538394011 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 538394011 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2418484511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2418484511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2418484511 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2418484511 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036822 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036822 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007316 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007316 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032091 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032091 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032091 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032091 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2059.159093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2059.159093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15541.654956 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15541.654956 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2552.005435 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 2552.005435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2552.005435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 2552.005435 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942971 # number of writebacks +system.cpu.dcache.writebacks::total 942971 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 275787 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 275787 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150248 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 150248 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 426035 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 426035 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 426035 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 426035 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907182 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 907182 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40524 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 40524 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947706 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947706 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947706 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947706 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10023226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10023226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 922752968 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 922752968 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945979468 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10945979468 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945979468 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10945979468 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036426 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036426 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008558 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008558 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031974 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031974 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031974 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031974 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11048.749314 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11048.749314 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22770.530254 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22770.530254 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11549.973798 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11549.973798 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11549.973798 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11549.973798 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10470.960701 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1840613 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10724.733108 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1834762 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15503 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.726247 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 118.348836 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9615.271069 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 626.227168 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 229.462463 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.293435 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019111 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007003 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.319548 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 912759 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 912786 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942946 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942946 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 20105 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 20105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932864 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932891 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932864 # number of overall hits -system.cpu.l2cache.overall_hits::total 932891 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 717 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 995 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 717 # number of demand (read+write) misses +system.cpu.l2cache.occ_blocks::writebacks 9870.615236 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 623.470728 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 230.647144 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.301227 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.019027 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007039 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.327293 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 906888 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 906916 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942971 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942971 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26002 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26002 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932890 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932918 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932890 # number of overall hits +system.cpu.l2cache.overall_hits::total 932918 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 715 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 994 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14537 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14537 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 715 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14816 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15533 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 717 # number of overall misses +system.cpu.l2cache.demand_misses::total 15531 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 715 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14816 # number of overall misses -system.cpu.l2cache.overall_misses::total 15533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23240500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9566500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 32807000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 335686000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 335686000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23240500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 345252500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 368493000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23240500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 345252500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 368493000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 744 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 913037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 913781 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942946 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942946 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 34643 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 34643 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 744 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947680 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948424 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 744 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947680 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948424 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963710 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419652 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.419652 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963710 # miss rate for demand accesses +system.cpu.l2cache.overall_misses::total 15531 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35034500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14031000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 49065500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 601080500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 601080500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35034500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 615111500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 650146000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35034500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 615111500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 650146000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 743 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 907167 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 907910 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942971 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942971 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 40539 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 40539 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 743 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947706 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948449 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 743 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947706 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948449 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962315 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358593 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358593 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962315 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015634 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016378 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963710 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016375 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016378 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32413.528591 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34411.870504 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 32971.859296 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 23090.246251 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 23090.246251 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32413.528591 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 23302.679536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 23723.234404 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32413.528591 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 23302.679536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 23723.234404 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 27 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::total 0.016375 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48999.300699 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50290.322581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49361.670020 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41348.318085 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41348.318085 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48999.300699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41516.704914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 41861.180864 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48999.300699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41516.704914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 41861.180864 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 715 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 982 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 715 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 714 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 983 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14537 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14537 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 714 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15520 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 715 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 714 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20653050 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8351373 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 29004423 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 284430809 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 284430809 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20653050 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 292782182 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 313435232 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20653050 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 292782182 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 313435232 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419652 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419652 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26001093 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10248888 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 36249981 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 418962782 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 418962782 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26001093 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 429211670 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 455212763 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26001093 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 429211670 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 455212763 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358593 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358593 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28885.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31278.550562 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29536.072301 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 19564.644999 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 19564.644999 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28885.384615 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 19775.898818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 20195.569072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28885.384615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 19775.898818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 20195.569072 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36416.096639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38099.955390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36876.888098 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28820.443145 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28820.443145 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36416.096639 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28989.036202 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29330.719265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36416.096639 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28989.036202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29330.719265 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 9850fa37f..91d2f15f8 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1039833 # Simulator instruction rate (inst/s) -host_op_rate 1047288 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1689137215 # Simulator tick rate (ticks/s) -host_mem_usage 366884 # Number of bytes of host memory used -host_seconds 87.11 # Real time elapsed on the host +host_inst_rate 1200528 # Simulator instruction rate (inst/s) +host_op_rate 1209136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1950176496 # Simulator tick rate (ticks/s) +host_mem_usage 364464 # Number of bytes of host memory used +host_seconds 75.45 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -280,9 +280,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index e3f69f56e..d610f9b78 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1171246 # Simulator instruction rate (inst/s) -host_op_rate 1171295 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1736457304 # Simulator tick rate (ticks/s) -host_mem_usage 354676 # Number of bytes of host memory used -host_seconds 208.18 # Real time elapsed on the host +host_inst_rate 1414417 # Simulator instruction rate (inst/s) +host_op_rate 1414475 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2096975339 # Simulator tick rate (ticks/s) +host_mem_usage 357072 # Number of bytes of host memory used +host_seconds 172.39 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory @@ -250,9 +250,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index ea6cef3aa..973686ac9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061268 # Number of seconds simulated -sim_ticks 61267871000 # Number of ticks simulated -final_tick 61267871000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.067525 # Number of seconds simulated +sim_ticks 67525253000 # Number of ticks simulated +final_tick 67525253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120787 # Simulator instruction rate (inst/s) -host_op_rate 212686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46841085 # Simulator tick rate (ticks/s) -host_mem_usage 363680 # Number of bytes of host memory used -host_seconds 1307.99 # Real time elapsed on the host +host_inst_rate 116144 # Simulator instruction rate (inst/s) +host_op_rate 204512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49640781 # Simulator tick rate (ticks/s) +host_mem_usage 364964 # Number of bytes of host memory used +host_seconds 1360.28 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1893248 # Number of bytes read from this memory -system.physmem.bytes_read::total 1962048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20608 # Number of bytes written to this memory -system.physmem.bytes_written::total 20608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29582 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30657 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 322 # Number of write requests responded to by this memory -system.physmem.num_writes::total 322 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1122938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30901155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 32024093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1122938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1122938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 336359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 336359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 336359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1122938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30901155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32360452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30662 # Total number of read requests seen -system.physmem.writeReqs 322 # Total number of write requests seen -system.physmem.cpureqs 30989 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1962048 # Total number of bytes read from memory -system.physmem.bytesWritten 20608 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1962048 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 20608 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 28 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 2024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1986 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1877 # Track reads on a per bank basis +system.physmem.bytes_read::cpu.inst 66944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1886080 # Number of bytes read from this memory +system.physmem.bytes_read::total 1953024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 13568 # Number of bytes written to this memory +system.physmem.bytes_written::total 13568 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1046 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29470 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 212 # Number of write requests responded to by this memory +system.physmem.num_writes::total 212 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 991392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 27931476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 28922868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 991392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 991392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 991392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 27931476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29123801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30518 # Total number of read requests seen +system.physmem.writeReqs 212 # Total number of write requests seen +system.physmem.cpureqs 30733 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1953024 # Total number of bytes read from memory +system.physmem.bytesWritten 13568 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1953024 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 13568 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 63 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1916 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2028 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 2002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1873 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1900 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1830 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1826 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1876 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1871 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1771 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 124 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 19 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 11 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 23 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 17 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 12 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 10 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 61267857000 # Total gap between requests +system.physmem.totGap 67525239000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30662 # Categorize read packet sizes +system.physmem.readPktSize::6 30518 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 322 # categorize write packet sizes +system.physmem.writePktSize::6 212 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 5 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 29991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,30 +138,30 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,265 +171,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 14166089 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 582752089 # Sum of mem lat for all requests -system.physmem.totBusLat 122532000 # Total cycles spent in databus access -system.physmem.totBankLat 446054000 # Total cycles spent in bank access -system.physmem.avgQLat 462.43 # Average queueing delay per request -system.physmem.avgBankLat 14560.75 # Average bank access latency per request -system.physmem.avgBusLat 3999.87 # Average bus latency per request -system.physmem.avgMemAccLat 19023.05 # Average memory access latency -system.physmem.avgRdBW 32.02 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.34 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 32.02 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.34 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 11553430 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 574779430 # Sum of mem lat for all requests +system.physmem.totBusLat 121820000 # Total cycles spent in databus access +system.physmem.totBankLat 441406000 # Total cycles spent in bank access +system.physmem.avgQLat 379.36 # Average queueing delay per request +system.physmem.avgBankLat 14493.71 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 18873.07 # Average memory access latency +system.physmem.avgRdBW 28.92 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.20 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 28.92 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.20 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.20 # Data bus utilization in percentage +system.physmem.busUtil 0.18 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 4.97 # Average write queue length over time -system.physmem.readRowHits 29782 # Number of row buffer hits during reads -system.physmem.writeRowHits 175 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.35 # Row buffer hit rate for writes -system.physmem.avgGap 1977403.08 # Average gap between requests +system.physmem.avgWrQLen 2.27 # Average write queue length over time +system.physmem.readRowHits 29673 # Number of row buffer hits during reads +system.physmem.writeRowHits 71 # Number of row buffer hits during writes +system.physmem.readRowHitRate 97.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.49 # Row buffer hit rate for writes +system.physmem.avgGap 2197371.92 # Average gap between requests system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 122535743 # number of cpu cycles simulated +system.cpu.numCycles 135050507 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 35570832 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 35570832 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1084026 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25425275 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25293552 # Number of BTB hits +system.cpu.BPredUnit.lookups 35279612 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 35279612 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1097690 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25134949 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25035866 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27817646 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 193664357 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35570832 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25293552 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 58615511 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7353362 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 29831602 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 154 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27179590 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 325172 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 122507486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.779073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.404197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27689493 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 190877273 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35279612 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25035866 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 58050662 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7148119 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43215578 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26932643 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266231 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 134969887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.491492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.329843 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66630267 54.39% 54.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2068884 1.69% 56.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2984971 2.44% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3999258 3.26% 61.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7980935 6.51% 68.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5030075 4.11% 72.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2863623 2.34% 74.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1430988 1.17% 75.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29518485 24.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79660068 59.02% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2061386 1.53% 60.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3001296 2.22% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4024404 2.98% 65.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7960578 5.90% 71.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4856128 3.60% 75.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2895673 2.15% 77.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1440638 1.07% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29069716 21.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 122507486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.290289 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.580472 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38875412 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 22176556 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 48070998 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7141971 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6242549 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336118074 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 6242549 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43268905 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2886935 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6989 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50676752 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19425356 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 332235244 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9392 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 17753597 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 139 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 334580463 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 881428154 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 881426042 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2112 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 134969887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261233 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.413377 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38714097 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35595607 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46068800 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8577479 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6013904 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 332373669 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 6013904 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44296876 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8440142 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9061 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48816518 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27393386 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 327323595 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 229 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 40548 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25654370 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 357 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 329853596 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 868074055 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 868071866 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2189 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 55367719 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 486 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 482 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 44129062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104954101 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36485312 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 41562946 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5830806 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 323945312 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307769548 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 217281 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 45552285 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 66549913 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1327 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 122507486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.512251 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.799024 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 50640852 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 483 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 61788867 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104142858 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36158946 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40039032 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6050954 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 321707041 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1738 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 307032101 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 190555 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42805778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 61072777 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1292 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 134969887 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.274819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.710764 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21268867 17.36% 17.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 16938160 13.83% 31.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24590210 20.07% 51.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 23966706 19.56% 70.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19077143 15.57% 86.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9190745 7.50% 93.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4997191 4.08% 97.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2322305 1.90% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 156159 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26262527 19.46% 19.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23269182 17.24% 36.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26059494 19.31% 56.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 26258264 19.45% 75.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19354972 14.34% 89.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8435024 6.25% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4232889 3.14% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 903483 0.67% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 194052 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 122507486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 134969887 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 51278 1.98% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1865528 72.01% 73.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 673849 26.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 32987 1.63% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1843971 90.87% 92.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152228 7.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174913911 56.83% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 42 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98825778 32.11% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33996476 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31299 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174160366 56.72% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 56 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99035655 32.26% 88.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33804725 11.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307769548 # Type of FU issued -system.cpu.iq.rate 2.511672 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2590655 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008418 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 740853926 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 369529188 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304569650 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310326577 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 285 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52294659 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307032101 # Type of FU issued +system.cpu.iq.rate 2.273461 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2029186 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006609 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 751253230 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 364547081 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 303801599 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 600 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1091 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 195 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 309029699 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 289 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54104965 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14174717 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50650 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 31690 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5045561 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13363474 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 46851 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34646 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4719195 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3163 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3287 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8523 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6242549 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 128946 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5786 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 323947085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 341652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104954101 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36485312 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 6013904 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1728221 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 160274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 321708779 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 372174 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104142858 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36158946 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 376 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 886 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31690 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 595739 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 583103 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1178842 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 305571382 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98206856 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2198166 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3195 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73111 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34646 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 603719 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 587627 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1191346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 304994543 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98411821 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2037558 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131649773 # number of memory reference insts executed -system.cpu.iew.exec_branches 31223750 # Number of branches executed -system.cpu.iew.exec_stores 33442917 # Number of stores executed -system.cpu.iew.exec_rate 2.493733 # Inst execution rate -system.cpu.iew.wb_sent 304986534 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304569837 # cumulative count of insts written-back -system.cpu.iew.wb_producers 226002140 # num instructions producing a value -system.cpu.iew.wb_consumers 312068538 # num instructions consuming a value +system.cpu.iew.exec_refs 131928718 # number of memory reference insts executed +system.cpu.iew.exec_branches 31180940 # Number of branches executed +system.cpu.iew.exec_stores 33516897 # Number of stores executed +system.cpu.iew.exec_rate 2.258374 # Inst execution rate +system.cpu.iew.wb_sent 304306961 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 303801794 # cumulative count of insts written-back +system.cpu.iew.wb_producers 222946371 # num instructions producing a value +system.cpu.iew.wb_consumers 302902430 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.485559 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.724207 # average fanout of values written-back +system.cpu.iew.wb_rate 2.249542 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736034 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 45756293 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43529723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1084042 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 116264937 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.392746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.783730 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1097716 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 128955983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.157267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.943706 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38380575 33.01% 33.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22255868 19.14% 52.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17068651 14.68% 66.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13099730 11.27% 78.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2025175 1.74% 79.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3235783 2.78% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1359435 1.17% 83.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 653883 0.56% 84.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18185837 15.64% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59867865 46.43% 46.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19620961 15.22% 61.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11973021 9.28% 70.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9656574 7.49% 78.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1838556 1.43% 79.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2079674 1.61% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1347744 1.05% 82.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 756025 0.59% 83.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21815563 16.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 116264937 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 128955983 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,305 +441,307 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 18185837 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 21815563 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 422027855 # The number of ROB reads -system.cpu.rob.rob_writes 654145762 # The number of ROB writes -system.cpu.timesIdled 622 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28257 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 428862605 # The number of ROB reads +system.cpu.rob.rob_writes 649464240 # The number of ROB writes +system.cpu.timesIdled 14220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80620 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.775599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.775599 # CPI: Total CPI of All Threads -system.cpu.ipc 1.289326 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.289326 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 598644238 # number of integer regfile reads -system.cpu.int_regfile_writes 305189502 # number of integer regfile writes -system.cpu.fp_regfile_reads 171 # number of floating regfile reads -system.cpu.fp_regfile_writes 94 # number of floating regfile writes -system.cpu.misc_regfile_reads 195525442 # number of misc regfile reads -system.cpu.icache.replacements 87 # number of replacements -system.cpu.icache.tagsinuse 849.665087 # Cycle average of tags in use -system.cpu.icache.total_refs 27178218 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1083 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25095.307479 # Average number of references to valid blocks. +system.cpu.cpi 0.854812 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.854812 # CPI: Total CPI of All Threads +system.cpu.ipc 1.169848 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.169848 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 599211234 # number of integer regfile reads +system.cpu.int_regfile_writes 304304879 # number of integer regfile writes +system.cpu.fp_regfile_reads 178 # number of floating regfile reads +system.cpu.fp_regfile_writes 115 # number of floating regfile writes +system.cpu.misc_regfile_reads 195413561 # number of misc regfile reads +system.cpu.icache.replacements 78 # number of replacements +system.cpu.icache.tagsinuse 851.671106 # Cycle average of tags in use +system.cpu.icache.total_refs 26931242 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1068 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25216.518727 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 849.665087 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.414876 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.414876 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27178218 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27178218 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27178218 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27178218 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27178218 # number of overall hits -system.cpu.icache.overall_hits::total 27178218 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1372 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1372 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1372 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1372 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1372 # number of overall misses -system.cpu.icache.overall_misses::total 1372 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45099500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45099500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45099500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45099500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45099500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45099500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27179590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27179590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27179590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27179590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27179590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27179590 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32871.355685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 32871.355685 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 32871.355685 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 32871.355685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 32871.355685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 32871.355685 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 851.671106 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.415855 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.415855 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 26931243 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26931243 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26931243 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26931243 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26931243 # number of overall hits +system.cpu.icache.overall_hits::total 26931243 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1400 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1400 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1400 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1400 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1400 # number of overall misses +system.cpu.icache.overall_misses::total 1400 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66418500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66418500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66418500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66418500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66418500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66418500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26932643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26932643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26932643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26932643 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26932643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26932643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47441.785714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47441.785714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47441.785714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47441.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47441.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47441.785714 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 283 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 283 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 283 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 283 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1089 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1089 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1089 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1089 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1089 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1089 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36146000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36146000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36146000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36146000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36146000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36146000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1072 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1072 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1072 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1072 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1072 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52640000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 52640000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52640000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 52640000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52640000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 52640000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33191.919192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33191.919192 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33191.919192 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33191.919192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33191.919192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33191.919192 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49104.477612 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49104.477612 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49104.477612 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49104.477612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49104.477612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49104.477612 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2071993 # number of replacements -system.cpu.dcache.tagsinuse 4071.813370 # Cycle average of tags in use -system.cpu.dcache.total_refs 74974075 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076089 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36.113131 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21436010000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.813370 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994095 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994095 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 43616503 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 43616503 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31357567 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31357567 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 74974070 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 74974070 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 74974070 # number of overall hits -system.cpu.dcache.overall_hits::total 74974070 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2256459 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2256459 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 82184 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 82184 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2338643 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2338643 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2338643 # number of overall misses -system.cpu.dcache.overall_misses::total 2338643 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9093612500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9093612500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 977800000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 977800000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10071412500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10071412500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10071412500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10071412500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45872962 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45872962 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072134 # number of replacements +system.cpu.dcache.tagsinuse 4072.225954 # Cycle average of tags in use +system.cpu.dcache.total_refs 72984548 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076230 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 35.152439 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 22141542000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.225954 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994196 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994196 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 41643096 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 41643096 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341442 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341442 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 72984538 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 72984538 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 72984538 # number of overall hits +system.cpu.dcache.overall_hits::total 72984538 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2617976 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2617976 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98309 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98309 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2716285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2716285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2716285 # number of overall misses +system.cpu.dcache.overall_misses::total 2716285 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31291069500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31291069500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2090661498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2090661498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33381730998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33381730998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33381730998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33381730998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 44261072 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 44261072 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77312713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77312713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77312713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77312713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002614 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002614 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.030249 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.030249 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.030249 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.030249 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4030.036664 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 4030.036664 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11897.692982 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 11897.692982 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 4306.519849 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 4306.519849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 4306.519849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 4306.519849 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 75700823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 75700823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 75700823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 75700823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.059148 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.059148 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003127 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003127 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035882 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035882 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.389747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.389747 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21266.226876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21266.226876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12289.480300 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12289.480300 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12289.480300 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12289.480300 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32223 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.395469 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2064741 # number of writebacks -system.cpu.dcache.writebacks::total 2064741 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262443 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 262443 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 102 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 102 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 262545 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 262545 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 262545 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 262545 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994016 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994016 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82082 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82082 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076098 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076098 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076098 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076098 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4062202500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4062202500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 812900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 812900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4875103000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4875103000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4875103000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4875103000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043468 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043468 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026853 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026853 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026853 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026853 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2037.196542 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2037.196542 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9903.517214 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9903.517214 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2348.204661 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 2348.204661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2348.204661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 2348.204661 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2065967 # number of writebacks +system.cpu.dcache.writebacks::total 2065967 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 623929 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 623929 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16120 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16120 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 640049 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 640049 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 640049 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 640049 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076236 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076236 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076236 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21985403000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21985403000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1815582998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1815582998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23800985998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23800985998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23800985998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23800985998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045052 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045052 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027427 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027427 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027427 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027427 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11025.518957 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11025.518957 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22090.340532 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22090.340532 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11463.526303 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11463.526303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11463.526303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11463.526303 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1477 # number of replacements -system.cpu.l2cache.tagsinuse 19662.234768 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4026933 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30639 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 131.431607 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 547 # number of replacements +system.cpu.l2cache.tagsinuse 20637.745612 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4028284 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30500 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.074885 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19155.060613 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 278.346040 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.828114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.584566 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.008494 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006983 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.600044 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993342 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993350 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2064741 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2064741 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53165 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53165 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046507 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2046515 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046507 # number of overall hits -system.cpu.l2cache.overall_hits::total 2046515 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1076 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 593 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1669 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 28993 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28993 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1076 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29586 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30662 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1076 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29586 # number of overall misses -system.cpu.l2cache.overall_misses::total 30662 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35032500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20747500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 55780000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 676068000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 676068000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35032500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 696815500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 731848000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35032500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 696815500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 731848000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1084 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1993935 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995019 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2064741 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2064741 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82158 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82158 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1084 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076093 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077177 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1084 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076093 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077177 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992620 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000297 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000837 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352893 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352893 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992620 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014251 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014761 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992620 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014251 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014761 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32558.085502 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34987.352445 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 33421.210306 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 23318.318215 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 23318.318215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32558.085502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 23552.203745 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 23868.240819 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32558.085502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 23552.203745 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 23868.240819 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 19684.475463 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 703.345334 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 249.924814 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.600723 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021464 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007627 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.629814 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993488 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993510 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2065967 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2065967 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53272 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53272 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2046760 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2046782 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2046760 # number of overall hits +system.cpu.l2cache.overall_hits::total 2046782 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1046 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 467 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1513 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 29005 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29005 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1046 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29472 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30518 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1046 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29472 # number of overall misses +system.cpu.l2cache.overall_misses::total 30518 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 51338000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23339500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 74677500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1201148000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1201148000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 51338000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1224487500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1275825500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 51338000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1224487500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1275825500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1993955 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995023 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2065967 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2065967 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82277 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82277 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1068 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076232 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077300 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1068 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076232 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077300 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.979401 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000234 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000758 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352529 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352529 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.979401 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014195 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014691 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.979401 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014195 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014691 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49080.305927 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49977.516060 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49357.237277 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41411.756594 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41411.756594 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49080.305927 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41547.485749 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 41805.672062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49080.305927 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41547.485749 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 41805.672062 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,60 +750,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 322 # number of writebacks -system.cpu.l2cache.writebacks::total 322 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 593 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1669 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29586 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30662 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29586 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30662 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31175128 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18631896 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 49807024 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5005 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5005 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 566101870 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 566101870 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31175128 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 584733766 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 615908894 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31175128 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 584733766 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 615908894 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000837 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352893 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352893 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014251 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014761 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014251 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014761 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28973.167286 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31419.723440 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29842.434991 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 19525.467182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 19525.467182 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28973.167286 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 19763.866897 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 20087.042398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28973.167286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 19763.866897 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 20087.042398 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 212 # number of writebacks +system.cpu.l2cache.writebacks::total 212 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1046 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1513 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29005 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29005 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29472 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29472 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30518 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38163141 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17461725 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55624866 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 826405394 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 826405394 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38163141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 843867119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 882030260 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38163141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 843867119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 882030260 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000234 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352529 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352529 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014691 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014691 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36484.838432 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37391.274090 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36764.617317 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28491.825340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28491.825340 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36484.838432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28632.841986 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28901.968019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36484.838432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28632.841986 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28901.968019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 0458ec538..c24d579f7 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365994 # Number of seconds simulated -sim_ticks 365994481000 # Number of ticks simulated -final_tick 365994481000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365989 # Number of seconds simulated +sim_ticks 365989063000 # Number of ticks simulated +final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 452383 # Simulator instruction rate (inst/s) -host_op_rate 796575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1047986231 # Simulator tick rate (ticks/s) -host_mem_usage 363904 # Number of bytes of host memory used -host_seconds 349.24 # Real time elapsed on the host +host_inst_rate 621192 # Simulator instruction rate (inst/s) +host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1439024491 # Simulator tick rate (ticks/s) +host_mem_usage 361884 # Number of bytes of host memory used +host_seconds 254.33 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory -system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory -system.physmem.bytes_written::total 14528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory -system.physmem.num_writes::total 227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 141292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5135815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5277107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 141292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 141292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5135815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5316801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory +system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory +system.physmem.bytes_written::total 6400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory +system.physmem.num_writes::total 100 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731988962 # number of cpu cycles simulated +system.cpu.numCycles 731978126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -54,16 +54,16 @@ system.cpu.num_mem_refs 122219135 # nu system.cpu.num_load_insts 90779384 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 731988962 # Number of busy cycles +system.cpu.num_busy_cycles 731978126 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.633473 # Cycle average of tags in use +system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.633473 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44440000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44440000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44440000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44440000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44440000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44440000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.488929 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.488929 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995237 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995237 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25503766000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25503766000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598582000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598582000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28102348000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28102348000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28102348000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28102348000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.347301 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.347301 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24489.741681 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24489.741681 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13596.842313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13596.842313 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2061794 # number of writebacks -system.cpu.dcache.writebacks::total 2061794 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks +system.cpu.dcache.writebacks::total 2062484 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386364000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386364000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968690000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23968690000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968690000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23968690000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -226,65 +226,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.741681 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.741681 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 19679.255550 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 318 # number of replacements +system.cpu.l2cache.tagsinuse 20041.899874 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19326.193704 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 210.694953 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 142.366893 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.589789 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004345 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.600563 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2061794 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 77082 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 77082 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 2037459 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037459 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 2037459 # number of overall hits -system.cpu.l2cache.overall_hits::total 2037459 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 343 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1151 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29027 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29027 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29370 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30178 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29370 # number of overall misses -system.cpu.l2cache.overall_misses::total 30178 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509435000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1509435000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1527271000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1569287000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1527271000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1569287000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 19330.353270 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 557.646384 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits +system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses +system.cpu.l2cache.overall_misses::total 30049 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2061794 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2061794 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses @@ -293,28 +296,28 @@ system.cpu.l2cache.demand_accesses::total 2067637 # n system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000175 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000587 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273558 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.273558 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014210 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014595 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014210 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014595 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.067971 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.067971 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.027238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.027238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,41 +326,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 227 # number of writebacks -system.cpu.l2cache.writebacks::total 227 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1151 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29027 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29027 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29370 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30178 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29370 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30178 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 46040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1161080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1161080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1174800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1207120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1174800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1207120000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273558 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273558 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks +system.cpu.l2cache.writebacks::total 100 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |