diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/se/10.mcf | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/se/10.mcf')
5 files changed, 1350 insertions, 1350 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 9627a30de..307f030d7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.026877 # Number of seconds simulated -sim_ticks 26876770500 # Number of ticks simulated -final_tick 26876770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26877484000 # Number of ticks simulated +final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124105 # Simulator instruction rate (inst/s) -host_op_rate 124996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36820237 # Simulator tick rate (ticks/s) -host_mem_usage 379416 # Number of bytes of host memory used -host_seconds 729.95 # Real time elapsed on the host +host_inst_rate 175198 # Simulator instruction rate (inst/s) +host_op_rate 176456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51980195 # Simulator tick rate (ticks/s) +host_mem_usage 379404 # Number of bytes of host memory used +host_seconds 517.07 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 992448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1666867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35258998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36925865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1666867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1666867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1666867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35258998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36925865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15507 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory +system.physmem.bytes_read::total 992384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15506 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15509 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 992448 # Total number of bytes read from memory +system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992384 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1078 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1079 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 934 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26876578500 # Total gap between requests +system.physmem.totGap 26877282500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15507 # Categorize read packet sizes +system.physmem.readPktSize::6 15506 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 11266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,17 +150,17 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3465.175627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 823.608896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3831.300006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3465.405018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 823.463699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3831.282142 # Bytes accessed per row activation system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 21 7.53% 31.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 17 6.09% 37.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 11 3.94% 41.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 11 3.94% 45.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 5 1.79% 47.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1 0.36% 48.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 3 1.08% 49.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 22 7.89% 32.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 15 5.38% 37.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 12 4.30% 41.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 10 3.58% 45.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 2.15% 47.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2 0.72% 48.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 2 0.72% 49.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation @@ -178,7 +178,7 @@ system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.36% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.36% 59.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation @@ -186,53 +186,53 @@ system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation -system.physmem.totQLat 33774250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 291406750 # Sum of mem lat for all requests -system.physmem.totBusLat 77535000 # Total cycles spent in databus access -system.physmem.totBankLat 180097500 # Total cycles spent in bank access -system.physmem.avgQLat 2178.00 # Average queueing delay per request -system.physmem.avgBankLat 11613.95 # Average bank access latency per request +system.physmem.totQLat 38456500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 288012750 # Sum of mem lat for all requests +system.physmem.totBusLat 77530000 # Total cycles spent in databus access +system.physmem.totBankLat 172026250 # Total cycles spent in bank access +system.physmem.avgQLat 2480.10 # Average queueing delay per request +system.physmem.avgBankLat 11094.17 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18791.95 # Average memory access latency -system.physmem.avgRdBW 36.93 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 18574.28 # Average memory access latency +system.physmem.avgRdBW 36.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 36.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 36.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15228 # Number of row buffer hits during reads +system.physmem.readRowHits 15227 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1733190.08 # Average gap between requests -system.membus.throughput 36925865 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 969 # Transaction distribution -system.membus.trans_dist::ReadResp 969 # Transaction distribution +system.physmem.avgGap 1733347.25 # Average gap between requests +system.membus.throughput 36922504 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 968 # Transaction distribution +system.membus.trans_dist::ReadResp 968 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 31018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 31018 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992448 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992384 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19245500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145771998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.branchPred.lookups 26679971 # Number of BP lookups -system.cpu.branchPred.condPredicted 21999923 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 841486 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11361779 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11280277 # Number of BTB hits +system.cpu.branchPred.lookups 26677800 # Number of BP lookups +system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 841974 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11370900 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11281126 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.282665 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69760 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 186 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.210493 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69875 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 190 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -276,239 +276,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53753542 # number of cpu cycles simulated +system.cpu.numCycles 53754969 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14168054 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127857393 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26679971 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11350037 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24029267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4759146 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11320906 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14167360 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127859416 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26677800 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11351001 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24030535 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4760658 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11306613 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13839868 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53419540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214764 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13839893 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329843 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53406892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214942 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29428601 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3388763 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2027589 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1554197 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1665441 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2919869 5.47% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1510771 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090381 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9833928 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29414657 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389704 6.35% 61.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028213 3.80% 65.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1552667 2.91% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667858 3.12% 71.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2917621 5.46% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1511775 2.83% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090045 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9834352 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53419540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.496339 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.378585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16932063 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9167037 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22428085 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 999775 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3892580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442872 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8651 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126035469 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42652 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3892580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18713289 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3601391 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 176810 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21544043 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5491427 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123129214 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 413620 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4613636 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1365 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143579054 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536328979 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536324233 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4746 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53406892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.496285 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.378560 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16930336 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9153085 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22398033 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031812 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3893626 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442083 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8660 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126043342 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3893626 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18711323 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3589161 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 177598 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21546569 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5488615 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123125799 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 427703 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4597767 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536314240 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5726 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36164868 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4608 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4606 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12537284 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29472276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5518407 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2148723 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1268677 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118148285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105144607 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78560 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26719178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65548353 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53419540 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968280 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.909780 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12549588 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29468785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5519570 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2135216 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1252898 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118144684 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8486 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105149299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79112 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26716988 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65524839 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 268 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53406892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.909318 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15372134 28.78% 28.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11649287 21.81% 50.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8266991 15.48% 66.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6802353 12.73% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4948394 9.26% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2939644 5.50% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2464571 4.61% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 534271 1.00% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 441895 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15356551 28.75% 28.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11649216 21.81% 50.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8254544 15.46% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6822524 12.77% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4944372 9.26% 88.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2950581 5.52% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2452903 4.59% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 533996 1.00% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442205 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53419540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53406892 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45832 6.94% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 339714 51.41% 58.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275235 41.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45764 6.91% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 341696 51.58% 58.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 274978 41.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74415665 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 126 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 171 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25604813 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5112854 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74418524 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 156 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 210 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25604703 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5114728 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105144607 # Type of FU issued -system.cpu.iq.rate 1.956050 # Inst issue rate -system.cpu.iq.fu_busy_cnt 660808 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006285 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264447444 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144880593 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102675373 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 678 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 959 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105805083 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 332 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 440146 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105149299 # Type of FU issued +system.cpu.iq.rate 1.956085 # Inst issue rate +system.cpu.iq.fu_busy_cnt 662465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264446249 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144874513 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102679810 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 818 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1193 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 350 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105811363 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 401 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 442313 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6898310 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6801 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6412 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 773563 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6894819 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6564 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6306 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 774726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31426 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31505 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3892580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 959936 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127408 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118169460 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310371 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29472276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5518407 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66175 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6842 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6412 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 445895 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891448 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104166950 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25284184 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 977657 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3893626 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 957081 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126869 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118165864 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309166 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29468785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5519570 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4598 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6306 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446848 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 444951 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891799 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104175749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25286286 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 973550 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12698 # number of nop insts executed -system.cpu.iew.exec_refs 30340262 # number of memory reference insts executed -system.cpu.iew.exec_branches 21325081 # Number of branches executed -system.cpu.iew.exec_stores 5056078 # Number of stores executed -system.cpu.iew.exec_rate 1.937862 # Inst execution rate -system.cpu.iew.wb_sent 102951696 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102675661 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62239721 # num instructions producing a value -system.cpu.iew.wb_consumers 104280591 # num instructions consuming a value +system.cpu.iew.exec_nop 12694 # number of nop insts executed +system.cpu.iew.exec_refs 30344072 # number of memory reference insts executed +system.cpu.iew.exec_branches 21323909 # Number of branches executed +system.cpu.iew.exec_stores 5057786 # Number of stores executed +system.cpu.iew.exec_rate 1.937974 # Inst execution rate +system.cpu.iew.wb_sent 102957516 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102680160 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62240823 # num instructions producing a value +system.cpu.iew.wb_consumers 104288348 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.910119 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596849 # average fanout of values written-back +system.cpu.iew.wb_rate 1.910152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596815 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26919455 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26915742 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 832928 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49526960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842491 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540649 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833391 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49513266 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.843000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540951 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20031869 40.45% 40.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13152738 26.56% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4167621 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431174 6.93% 82.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533592 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 731516 1.48% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 947722 1.91% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 252646 0.51% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5278082 10.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20021121 40.44% 40.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13151741 26.56% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4165163 8.41% 75.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3429722 6.93% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1536672 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 726445 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951437 1.92% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253528 0.51% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5277437 10.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49526960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49513266 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -519,97 +519,97 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5278082 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5277437 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162415559 # The number of ROB reads -system.cpu.rob.rob_writes 240257118 # The number of ROB writes -system.cpu.timesIdled 46037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 334002 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162398797 # The number of ROB reads +system.cpu.rob.rob_writes 240250691 # The number of ROB writes +system.cpu.timesIdled 46136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 348077 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.593373 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.593373 # CPI: Total CPI of All Threads -system.cpu.ipc 1.685281 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.685281 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495496517 # number of integer regfile reads -system.cpu.int_regfile_writes 120533542 # number of integer regfile writes -system.cpu.fp_regfile_reads 149 # number of floating regfile reads -system.cpu.fp_regfile_writes 362 # number of floating regfile writes -system.cpu.misc_regfile_reads 29086571 # number of misc regfile reads +system.cpu.cpi 0.593389 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.593389 # CPI: Total CPI of All Threads +system.cpu.ipc 1.685236 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.685236 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495533268 # number of integer regfile reads +system.cpu.int_regfile_writes 120542090 # number of integer regfile writes +system.cpu.fp_regfile_reads 173 # number of floating regfile reads +system.cpu.fp_regfile_writes 448 # number of floating regfile writes +system.cpu.misc_regfile_reads 29087390 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4503595847 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942920 # Transaction distribution +system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43775 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2839649 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120995392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 121041920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121041920 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888563000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1095499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1421456489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 627.794494 # Cycle average of tags in use -system.cpu.icache.total_refs 13838883 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 727 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19035.602476 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.794494 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306540 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13838883 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13838883 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13838883 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13838883 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13838883 # number of overall hits -system.cpu.icache.overall_hits::total 13838883 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses -system.cpu.icache.overall_misses::total 984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66043999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66043999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66043999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66043999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66043999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66043999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13839867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13839867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13839867 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13839867 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13839867 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13839867 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits +system.cpu.icache.overall_hits::total 13838909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses +system.cpu.icache.overall_misses::total 983 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64555998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64555998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64555998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64555998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64555998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64555998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13839892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13839892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13839892 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13839892 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13839892 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13839892 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67117.885163 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67117.885163 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67117.885163 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67117.885163 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65672.429298 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65672.429298 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65672.429298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65672.429298 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 629 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.300000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.900000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -619,122 +619,122 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 254 system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 730 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 730 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 730 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 730 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 730 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 730 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49961500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49961500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49961500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49961500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49961500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49961500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 729 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 729 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 729 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 729 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 729 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 729 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49190750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49190750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49190750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49190750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49190750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49190750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68440.410959 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68440.410959 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68440.410959 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68440.410959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68440.410959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68440.410959 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67477.023320 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67477.023320 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10730.679646 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1831381 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15490 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.229890 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9888.279908 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 613.185142 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 229.214596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.301766 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006995 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.327474 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903579 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903605 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942920 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942920 # number of Writeback hits +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942919 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942919 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 29237 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 29237 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932816 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932842 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932816 # number of overall hits -system.cpu.l2cache.overall_hits::total 932842 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 701 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 980 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 29198 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 29198 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932813 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932836 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932813 # number of overall hits +system.cpu.l2cache.overall_hits::total 932836 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 703 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 979 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15518 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses -system.cpu.l2cache.overall_misses::total 15518 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48961500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19173000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 68134500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 895149000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 895149000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48961500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 914322000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 963283500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 48961500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 914322000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 963283500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 727 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903858 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904585 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942920 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942920 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 703 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15517 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 703 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses +system.cpu.l2cache.overall_misses::total 15517 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48235000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19323500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 67558500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 897218750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 897218750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 48235000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 916542250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 964777250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 48235000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 916542250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 964777250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 726 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903891 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904617 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942919 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43775 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43775 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 727 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947633 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948360 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 727 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947633 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948360 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964237 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 726 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947627 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948353 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 726 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947627 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948353 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968320 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001082 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332107 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.332107 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964237 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016363 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964237 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016363 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69845.221113 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68720.430108 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69525 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61573.049938 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61573.049938 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69845.221113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61707.633124 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62075.235211 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69845.221113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61707.633124 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62075.235211 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332404 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.332404 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968320 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016362 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968320 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016362 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.086771 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70012.681159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69007.660878 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61715.418214 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61715.418214 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68613.086771 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61870.004725 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 62175.501063 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68613.086771 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61870.004725 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 62175.501063 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -752,184 +752,184 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 700 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 702 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 266 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15507 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15507 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40240750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15233500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55474250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 702 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15506 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 702 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15506 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39349250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15357000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54706250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714861250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714861250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40240750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730094750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 770335500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40240750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730094750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 770335500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714814750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714814750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39349250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730171750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 769521000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39349250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730171750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 769521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001070 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57486.785714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56630.111524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57248.968008 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332404 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332404 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016350 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016350 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56053.062678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57733.082707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56514.721074 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49171.911542 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49171.911542 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49168.713028 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49168.713028 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943537 # number of replacements -system.cpu.dcache.tagsinuse 3672.136580 # Cycle average of tags in use -system.cpu.dcache.total_refs 28138091 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947633 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.693026 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7986158000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3672.136580 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.896518 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.896518 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23597541 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23597541 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532751 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532751 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3906 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3906 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 943531 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532905 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3915 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3915 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28130292 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28130292 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28130292 # number of overall hits -system.cpu.dcache.overall_hits::total 28130292 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173737 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173737 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202230 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202230 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1375967 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1375967 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1375967 # number of overall misses -system.cpu.dcache.overall_misses::total 1375967 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13887682000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7842358356 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7842358356 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 236000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 236000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21730040356 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21730040356 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21730040356 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21730040356 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24771278 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24771278 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 28130035 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28130035 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28130035 # number of overall hits +system.cpu.dcache.overall_hits::total 28130035 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173788 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173788 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202076 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1375864 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1375864 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1375864 # number of overall misses +system.cpu.dcache.overall_misses::total 1375864 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887695479 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13887695479 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7918602355 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7918602355 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 251250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21806297834 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21806297834 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21806297834 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21806297834 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24770918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24770918 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3913 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3913 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29506259 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29506259 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29506259 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29506259 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047383 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047383 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042710 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042710 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11832.021995 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11832.021995 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38779.401454 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38779.401454 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33714.285714 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33714.285714 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15792.559237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15792.559237 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 153985 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29505899 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29505899 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29505899 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29505899 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047386 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047386 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042677 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042677 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046630 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046630 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046630 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046630 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.519388 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.519388 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39186.258413 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39186.258413 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31406.250000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31406.250000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15849.166657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15849.166657 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154131 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23865 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23950 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.452336 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.435532 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942920 # number of writebacks -system.cpu.dcache.writebacks::total 942920 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269859 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269859 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158472 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158472 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428331 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428331 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428331 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428331 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903878 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903878 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43758 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43758 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947636 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947636 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947636 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947636 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9991782011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9991782011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1252450464 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1252450464 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11244232475 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11244232475 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11244232475 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11244232475 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036489 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009241 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.348055 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.348055 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28622.205402 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28622.205402 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942919 # number of writebacks +system.cpu.dcache.writebacks::total 942919 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269877 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269877 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158357 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 428234 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428234 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428234 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428234 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903911 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903911 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43719 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43719 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947630 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947630 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947630 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9992457010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9992457010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254142688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254142688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11246599698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11246599698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11246599698 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11246599698 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009233 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009233 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.691236 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.691236 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28686.444978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28686.444978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index bffef2d47..5c365748d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 294271952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 510.071144 # Cycle average of tags in use -system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 119.244078 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.291909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 942702 # number of replacements -system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use -system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b41c1d4fe..2c81bb996 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 722977060 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use -system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 25 # number of replacements +system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits @@ -279,15 +279,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index a8ad328fe..eb92ec68e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065490 # Number of seconds simulated -sim_ticks 65489948000 # Number of ticks simulated -final_tick 65489948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065502 # Number of seconds simulated +sim_ticks 65501881000 # Number of ticks simulated +final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99083 # Simulator instruction rate (inst/s) -host_op_rate 174470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41072394 # Simulator tick rate (ticks/s) -host_mem_usage 386708 # Number of bytes of host memory used -host_seconds 1594.50 # Real time elapsed on the host +host_inst_rate 72627 # Simulator instruction rate (inst/s) +host_op_rate 127885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30111215 # Simulator tick rate (ticks/s) +host_mem_usage 386704 # Number of bytes of host memory used +host_seconds 2175.33 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882624 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10112 # Number of bytes written to this memory -system.physmem.bytes_written::total 10112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29416 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 975295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28746763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29722057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28746763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29876463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30415 # Total number of read requests seen -system.physmem.writeReqs 158 # Total number of write requests seen +system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory +system.physmem.bytes_written::total 10432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30408 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 971209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28739572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29710780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 971209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 971209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 159263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 159263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 159263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30410 # Total number of read requests seen +system.physmem.writeReqs 163 # Total number of write requests seen system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1946496 # Total number of bytes read from memory -system.physmem.bytesWritten 10112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 47 # Number of read reqs serviced by write Q +system.physmem.bytesRead 1946112 # Total number of bytes read from memory +system.physmem.bytesWritten 10432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1901 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 2030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1939 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1934 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1796 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1818 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis @@ -77,26 +77,26 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65489931000 # Total gap between requests +system.physmem.totGap 65501859000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30415 # Categorize read packet sizes +system.physmem.readPktSize::6 30410 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 158 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see @@ -144,9 +144,9 @@ system.physmem.wrQLenPdf::16 7 # Wh system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -156,231 +156,231 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 551 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3522.090744 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 829.782913 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3844.695710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 143 25.95% 25.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 46 8.35% 34.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 23 4.17% 38.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 15 2.72% 41.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 11 2.00% 43.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10 1.81% 45.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 9 1.63% 46.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 0.91% 47.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.91% 48.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.81% 50.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.73% 51.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.09% 52.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 2 0.36% 52.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1 0.18% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.54% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1 0.18% 53.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.18% 55.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.54% 56.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.36% 56.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.18% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.18% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.36% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.18% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.18% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.18% 58.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.18% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.36% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.18% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.18% 59.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.18% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 216 39.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 551 # Bytes accessed per row activation -system.physmem.totQLat 7172750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 582609000 # Sum of mem lat for all requests -system.physmem.totBusLat 151840000 # Total cycles spent in databus access -system.physmem.totBankLat 423596250 # Total cycles spent in bank access -system.physmem.avgQLat 236.19 # Average queueing delay per request -system.physmem.avgBankLat 13948.77 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 552 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3503.884058 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 832.064707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3839.690246 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 138 25.00% 25.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 47 8.51% 33.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 28 5.07% 38.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 12 2.17% 40.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 14 2.54% 43.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 11 1.99% 45.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8 1.45% 46.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 4 0.72% 47.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.63% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 7 1.27% 50.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.72% 51.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 7 1.27% 52.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 2 0.36% 52.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 2 0.36% 53.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.54% 53.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.18% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.18% 56.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.36% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.18% 56.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.18% 57.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.36% 57.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.36% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.18% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.18% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.18% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.18% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.18% 59.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.18% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.36% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.18% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 215 38.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 552 # Bytes accessed per row activation +system.physmem.totQLat 7596000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 583088500 # Sum of mem lat for all requests +system.physmem.totBusLat 151800000 # Total cycles spent in databus access +system.physmem.totBankLat 423692500 # Total cycles spent in bank access +system.physmem.avgQLat 250.20 # Average queueing delay per request +system.physmem.avgBankLat 13955.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19184.96 # Average memory access latency -system.physmem.avgRdBW 29.72 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.72 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 19205.81 # Average memory access latency +system.physmem.avgRdBW 29.71 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 0.64 # Average write queue length over time -system.physmem.readRowHits 29867 # Number of row buffer hits during reads -system.physmem.writeRowHits 88 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.70 # Row buffer hit rate for writes -system.physmem.avgGap 2142083.90 # Average gap between requests -system.membus.throughput 29875486 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1414 # Transaction distribution -system.membus.trans_dist::ReadResp 1412 # Transaction distribution -system.membus.trans_dist::Writeback 158 # Transaction distribution -system.membus.trans_dist::ReadExReq 29001 # Transaction distribution -system.membus.trans_dist::ReadExResp 29001 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60986 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1956544 # Total data (bytes) +system.physmem.avgWrQLen 12.43 # Average write queue length over time +system.physmem.readRowHits 29868 # Number of row buffer hits during reads +system.physmem.writeRowHits 101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.96 # Row buffer hit rate for writes +system.physmem.avgGap 2142474.05 # Average gap between requests +system.membus.throughput 29869066 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1406 # Transaction distribution +system.membus.trans_dist::ReadResp 1403 # Transaction distribution +system.membus.trans_dist::Writeback 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 29004 # Transaction distribution +system.membus.trans_dist::ReadExResp 29004 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1956480 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34719000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 35091000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 283984750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284259500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.branchPred.lookups 33857873 # Number of BP lookups -system.cpu.branchPred.condPredicted 33857873 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774323 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19304335 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19204317 # Number of BTB hits +system.cpu.branchPred.lookups 33859772 # Number of BP lookups +system.cpu.branchPred.condPredicted 33859772 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774888 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19298286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19204033 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.481888 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5017100 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5401 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.511599 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5017180 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5379 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 130979906 # number of cpu cycles simulated +system.cpu.numCycles 131003766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26132901 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182254705 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33857873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24221417 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55457387 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5351238 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44744671 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 26135908 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182273755 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33859772 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24221213 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55461769 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5355546 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44756866 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 388 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25573947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 130876974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.455077 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.315032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 25575264 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 165870 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 130900361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.454854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314999 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77895599 59.52% 59.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1961064 1.50% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2941506 2.25% 63.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3833280 2.93% 66.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7768261 5.94% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757709 3.64% 75.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2666396 2.04% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316117 1.01% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27737042 21.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77915453 59.52% 59.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1959993 1.50% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2942167 2.25% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3834775 2.93% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7768215 5.93% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757692 3.63% 75.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2664580 2.04% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316041 1.01% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27741445 21.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 130876974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258497 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.391471 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36825046 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36962033 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43884335 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8664000 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4541560 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318828995 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4541560 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42312169 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9511401 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7346 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46756594 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27747904 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 314994654 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26642 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25895040 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 476 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 317170346 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836475154 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 836474392 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 762 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 130900361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258464 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.391363 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36822089 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36980976 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43893831 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8658090 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4545375 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318858939 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4545375 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42309692 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9552635 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46756316 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27728938 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 315018359 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 180 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26669 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25876041 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 477 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 317189446 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836531493 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 836530400 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1093 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37957599 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 473 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 471 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62618763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101546098 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34776490 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39628981 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5872628 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311460641 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1620 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300263242 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89194 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32692736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46075932 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1175 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 130876974 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.294240 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698248 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37976699 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 479 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 477 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62612991 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101555768 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34778786 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39638216 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5865755 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311479938 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1623 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300277679 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89964 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32707513 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46093052 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 130900361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.293941 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.699121 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24131864 18.44% 18.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23200747 17.73% 36.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25515846 19.50% 55.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25800196 19.71% 75.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18908821 14.45% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8226578 6.29% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3966533 3.03% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 948269 0.72% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 178120 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24175636 18.47% 18.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23209060 17.73% 36.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25458730 19.45% 55.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25817772 19.72% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18910783 14.45% 89.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8235477 6.29% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3954804 3.02% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 956290 0.73% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181809 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 130876974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 130900361 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31350 1.52% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1914118 93.02% 94.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 112203 5.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31412 1.53% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1912178 93.02% 94.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111979 5.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31269 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169831463 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11173 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169839925 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11359 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued @@ -406,84 +406,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97296683 32.40% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33092294 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97303672 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33091082 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300263242 # Type of FU issued -system.cpu.iq.rate 2.292437 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2057671 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006853 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733550061 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344187115 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298012847 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 328 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302289511 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54160833 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300277679 # Type of FU issued +system.cpu.iq.rate 2.292130 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2055569 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006846 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733600907 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344221068 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298025850 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 456 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302301800 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54184658 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10766713 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30678 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33261 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3336738 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10776383 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30894 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33570 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3339034 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3210 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8599 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3237 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8568 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4541560 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2575832 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162156 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311462261 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197211 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101546098 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34776490 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 463 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2580 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73528 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33261 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393064 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427262 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 820326 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298861022 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96886540 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1402220 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4545375 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2618322 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 161863 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311481561 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 197279 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101555768 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34778786 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73457 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33570 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427979 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821632 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298876380 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891177 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1401299 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129814002 # number of memory reference insts executed -system.cpu.iew.exec_branches 30818579 # Number of branches executed -system.cpu.iew.exec_stores 32927462 # Number of stores executed -system.cpu.iew.exec_rate 2.281732 # Inst execution rate -system.cpu.iew.wb_sent 298381528 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298012951 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218258094 # num instructions producing a value -system.cpu.iew.wb_consumers 296763752 # num instructions consuming a value +system.cpu.iew.exec_refs 129818452 # number of memory reference insts executed +system.cpu.iew.exec_branches 30820594 # Number of branches executed +system.cpu.iew.exec_stores 32927275 # Number of stores executed +system.cpu.iew.exec_rate 2.281433 # Inst execution rate +system.cpu.iew.wb_sent 298395371 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298025973 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218267458 # num instructions producing a value +system.cpu.iew.wb_consumers 296778027 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.275257 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735461 # average fanout of values written-back +system.cpu.iew.wb_rate 2.274942 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735457 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33282582 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33301924 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774373 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126335414 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.202015 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.972310 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774937 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126354986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.201674 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.972574 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58023185 45.93% 45.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19157211 15.16% 61.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11690918 9.25% 70.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9453779 7.48% 77.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1822705 1.44% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2075367 1.64% 80.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1288633 1.02% 81.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 696301 0.55% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22127315 17.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58072502 45.96% 45.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19158205 15.16% 61.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11637077 9.21% 70.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9445238 7.48% 77.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1852713 1.47% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2072442 1.64% 80.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1294957 1.02% 81.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 693229 0.55% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22128623 17.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126335414 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126354986 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -494,212 +494,212 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22127315 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22128623 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415683145 # The number of ROB reads -system.cpu.rob.rob_writes 627495486 # The number of ROB writes -system.cpu.timesIdled 13953 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 102932 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415720751 # The number of ROB reads +system.cpu.rob.rob_writes 627537958 # The number of ROB writes +system.cpu.timesIdled 13918 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 103405 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.829047 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829047 # CPI: Total CPI of All Threads -system.cpu.ipc 1.206204 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.206204 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 590786274 # number of integer regfile reads -system.cpu.int_regfile_writes 298589380 # number of integer regfile writes -system.cpu.fp_regfile_reads 94 # number of floating regfile reads -system.cpu.fp_regfile_writes 64 # number of floating regfile writes -system.cpu.misc_regfile_reads 191820132 # number of misc regfile reads +system.cpu.cpi 0.829198 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829198 # CPI: Total CPI of All Threads +system.cpu.ipc 1.205985 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.205985 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 590807496 # number of integer regfile reads +system.cpu.int_regfile_writes 298603166 # number of integer regfile writes +system.cpu.fp_regfile_reads 109 # number of floating regfile reads +system.cpu.fp_regfile_writes 74 # number of floating regfile writes +system.cpu.misc_regfile_reads 191829835 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4049838977 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995271 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066544 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82308 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2026 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 6221700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265158912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 265223744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265223744 # Total data (bytes) +system.cpu.toL2Bus.throughput 4049183259 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 6221783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265164480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 265229120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138605500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1519500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1707500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3114846499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.replacements 52 # number of replacements -system.cpu.icache.tagsinuse 824.208577 # Cycle average of tags in use -system.cpu.icache.total_refs 25572646 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1013 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25244.467917 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 824.208577 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.402446 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.402446 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25572646 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25572646 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25572646 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25572646 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25572646 # number of overall hits -system.cpu.icache.overall_hits::total 25572646 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1301 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1301 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1301 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1301 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1301 # number of overall misses -system.cpu.icache.overall_misses::total 1301 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 86424000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 86424000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 86424000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 86424000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 86424000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 86424000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25573947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25573947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25573947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25573947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25573947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25573947 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 57 # number of replacements +system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25573967 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25573967 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25573967 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25573967 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25573967 # number of overall hits +system.cpu.icache.overall_hits::total 25573967 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1297 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1297 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1297 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1297 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1297 # number of overall misses +system.cpu.icache.overall_misses::total 1297 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 86393250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86393250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 86393250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 86393250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 86393250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 86393250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25575264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25575264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25575264 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25575264 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25575264 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25575264 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66428.900846 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66428.900846 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66428.900846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66428.900846 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66610.061681 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66610.061681 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66610.061681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66610.061681 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 288 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 288 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 288 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 288 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 288 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1013 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1013 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1013 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68779000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68779000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68779000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68779000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68779000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68779000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67896.347483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67896.347483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67896.347483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67896.347483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67896.347483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67896.347483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 287 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 287 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 287 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 287 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 287 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1010 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1010 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1010 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68485500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 68485500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68485500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 68485500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68485500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 68485500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67807.425743 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67807.425743 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 473 # number of replacements -system.cpu.l2cache.tagsinuse 20826.388210 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4029249 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30396 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.558527 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19907.583487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 670.159667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 248.645055 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.607531 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020452 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007588 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.635571 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 15 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993842 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993857 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2066544 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2066544 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53307 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53307 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 15 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2047149 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2047164 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 15 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2047149 # number of overall hits -system.cpu.l2cache.overall_hits::total 2047164 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 998 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 416 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1414 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29417 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30415 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29417 # number of overall misses -system.cpu.l2cache.overall_misses::total 30415 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 67606500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28450500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 96057000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1775245500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1775245500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 67606500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1803696000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1871302500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 67606500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1803696000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1871302500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1013 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1994258 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995271 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2066544 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2066544 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82308 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82308 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1013 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076566 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077579 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1013 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076566 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077579 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985192 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000209 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000709 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352347 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352347 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985192 # miss rate for demand accesses +system.cpu.l2cache.tags.replacements 474 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 19907.577759 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.404621 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 245.423625 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.607531 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020368 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.635388 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993851 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993867 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066630 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066630 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53301 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53301 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2047152 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2047168 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2047152 # number of overall hits +system.cpu.l2cache.overall_hits::total 2047168 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 994 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 412 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1406 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 29004 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29004 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 994 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29416 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30410 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29416 # number of overall misses +system.cpu.l2cache.overall_misses::total 30410 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 67308000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28553000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 95861000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1783241500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1783241500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 67308000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1811794500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1879102500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 67308000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1811794500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1879102500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994263 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995273 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066630 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066630 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82305 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82305 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1010 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076568 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077578 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1010 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076568 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077578 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000207 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000705 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352397 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352397 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984158 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.014166 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014640 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985192 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.014637 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984158 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014166 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014640 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67741.983968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68390.625000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67932.814710 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61213.251267 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61213.251267 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67741.983968 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61314.749975 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61525.645241 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67741.983968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61314.749975 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61525.645241 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.014637 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67714.285714 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69303.398058 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68179.943101 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61482.605847 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61482.605847 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67714.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61592.143731 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 61792.255837 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67714.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61592.143731 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 61792.255837 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -708,160 +708,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 158 # number of writebacks -system.cpu.l2cache.writebacks::total 158 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 998 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 416 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1414 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30415 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29417 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30415 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55248500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23325000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 78573500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1417505250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1417505250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55248500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1440830250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1496078750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55248500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1440830250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1496078750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352347 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352347 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for demand accesses +system.cpu.l2cache.writebacks::writebacks 163 # number of writebacks +system.cpu.l2cache.writebacks::total 163 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 994 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 412 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1406 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29004 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29004 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 994 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30410 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 994 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29416 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30410 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 54811000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23413500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 78224500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1417981500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1417981500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 54811000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1441395000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1496206000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 54811000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1441395000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1496206000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000207 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000705 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984158 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014166 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014640 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014637 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984158 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014166 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014640 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55359.218437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56069.711538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55568.246110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48877.805938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48877.805938 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55359.218437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.510147 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49188.845964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55359.218437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.510147 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49188.845964 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014637 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55141.851107 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56828.883495 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55636.201991 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48889.170459 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48889.170459 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55141.851107 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55141.851107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072468 # number of replacements -system.cpu.dcache.tagsinuse 4069.997432 # Cycle average of tags in use -system.cpu.dcache.total_refs 71397556 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076564 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.382545 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 20655836000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4069.997432 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.993652 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.993652 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40055849 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40055849 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71397556 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71397556 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71397556 # number of overall hits -system.cpu.dcache.overall_hits::total 71397556 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2625767 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2625767 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98045 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98045 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2723812 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2723812 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2723812 # number of overall misses -system.cpu.dcache.overall_misses::total 2723812 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31384094500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31384094500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2663792498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2663792498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34047886998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34047886998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34047886998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34047886998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42681616 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42681616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 2072469 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40036076 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40036076 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341699 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341699 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71377775 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71377775 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71377775 # number of overall hits +system.cpu.dcache.overall_hits::total 71377775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2626397 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2626397 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98053 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98053 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2724450 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2724450 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2724450 # number of overall misses +system.cpu.dcache.overall_misses::total 2724450 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31390082250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31390082250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2686066747 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2686066747 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34076148997 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34076148997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34076148997 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34076148997 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42662473 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42662473 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74121368 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74121368 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74121368 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74121368 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061520 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061520 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74102225 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74102225 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74102225 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74102225 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061562 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061562 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036748 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036748 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036748 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036748 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.353160 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.353160 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.080504 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.080504 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12500.087010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12500.087010 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32905 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036766 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036766 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11951.765955 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11951.765955 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27394.029219 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27394.029219 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12507.533262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12507.533262 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32680 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9507 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9460 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.461134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.454545 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066544 # number of writebacks -system.cpu.dcache.writebacks::total 2066544 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631390 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631390 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15856 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647246 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647246 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647246 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647246 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994377 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994377 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076566 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076566 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994900501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994900501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2389827998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2389827998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24384728499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24384728499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24384728499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24384728499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046727 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046727 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066630 # number of writebacks +system.cpu.dcache.writebacks::total 2066630 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632021 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 632021 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15861 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15861 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647882 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647882 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647882 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647882 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994376 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994376 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82192 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076568 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076568 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076568 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076568 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397806497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397806497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392651497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24392651497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392651497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24392651497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046748 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046748 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.456757 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.456757 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29077.224422 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29077.224422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028023 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028023 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.434458 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.434458 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29173.234585 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29173.234585 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index c0ade68d4..d47d4ffea 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 731978130 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.632508 # Cycle average of tags in use -system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24 # number of replacements +system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 318 # number of replacements -system.cpu.l2cache.tagsinuse 20041.899765 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 318 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits @@ -293,15 +293,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.488619 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits |